DBT-RISE/DBT-RISE-TGC
11
0
Fork 0
Code Issues 1 Pull Requests 1 Projects Releases Wiki Activity

Compare commits

base: DBT-RISE:a45fcd28db032099aaa24b3a6472f957cbe3c4b9
Branches Tags
DBT-RISE:main
DBT-RISE:develop
DBT-RISE:feature/htif
DBT-RISE:feature/iss_factory
DBT-RISE:feature/core_factory
DBT-RISE:Trace_enhancement
DBT-RISE:feature/reduced_output
DBT-RISE:msvc_compat
DBT-RISE:hotfix/latest_scc
DBT-RISE:feature/interpreter
..
compare: DBT-RISE:c28e8fd00c9c58472cf9495737c20034e3390723
Branches Tags
DBT-RISE:main
DBT-RISE:develop
DBT-RISE:feature/htif
DBT-RISE:feature/iss_factory
DBT-RISE:feature/core_factory
DBT-RISE:Trace_enhancement
DBT-RISE:feature/reduced_output
DBT-RISE:msvc_compat
DBT-RISE:hotfix/latest_scc
DBT-RISE:feature/interpreter

No commits in common. "a45fcd28db032099aaa24b3a6472f957cbe3c4b9" and "c28e8fd00c9c58472cf9495737c20034e3390723" have entirely different histories.
a45fcd28db ... c28e8fd00c

9 changed files with 877 additions and 937 deletions
Show Stats Expand all files Collapse all files

18
gen_input/templates/asmjit/CORENAME.cpp.gtl
View File

@ -38,9 +38,7 @@
#include <asmjit/asmjit.h>
#include <util/logging.h>
#include <iss/instruction_decoder.h>
<%def fcsr = registers.find {it.name=='FCSR'}
if(fcsr != null) {%>
#include <vm/fp_functions.h><%}%>
#ifndef FMT_HEADER_ONLY
#define FMT_HEADER_ONLY
#endif
@ -90,6 +88,7 @@ protected:
using super::write_reg_to_mem;
using super::gen_read_mem;
using super::gen_write_mem;
using super::gen_wait;
using super::gen_leave;
using super::gen_sync;
@ -101,9 +100,7 @@ protected:
void gen_block_prologue(jit_holder& jh) override;
void gen_block_epilogue(jit_holder& jh) override;
inline const char *name(size_t index){return traits::reg_aliases.at(index);}
<%if(fcsr != null) {%>
inline const char *fname(size_t index){return index < 32?name(index+traits::F0):"illegal";}
<%}%>
void gen_instr_prologue(jit_holder& jh);
void gen_instr_epilogue(jit_holder& jh);
inline void gen_raise(jit_holder& jh, uint16_t trap_id, uint16_t cause);
@ -116,9 +113,6 @@ protected:
auto sign_mask = 1ULL<<(W-1);
return (from & mask) | ((from & sign_mask) ? ~mask : 0);
}
<%functions.each{ it.eachLine { %>
${it}<%}%>
<%}%>
private:
/****************************************************************************
* start opcode definitions
@ -201,7 +195,7 @@ private:
gen_raise(jh, 0, 2);
gen_sync(jh, POST_SYNC, instr_descr.size());
gen_instr_epilogue(jh);
return ILLEGAL_INSTR;
return BRANCH;
}
};
@ -230,9 +224,9 @@ continuation_e vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, unsigned
paddr = this->core.virt2phys(pc);
auto res = this->core.read(paddr, 4, data);
if (res != iss::Ok)
return ILLEGAL_FETCH;
throw trap_access(TRAP_ID, pc.val);
if (instr == 0x0000006f || (instr&0xffff)==0xa001)
return JUMP_TO_SELF;
throw simulation_stopped(0); // 'J 0' or 'C.J 0'
++inst_cnt;
uint32_t inst_index = instr_decoder.decode_instr(instr);
compile_func f = nullptr;

3
gen_input/templates/interp/CORENAME.cpp.gtl
View File

@ -267,7 +267,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
uint32_t inst_index = instr_decoder.decode_instr(instr);
opcode_e inst_id = arch::traits<ARCH>::opcode_e::MAX_OPCODE;;
if(inst_index <instr_descr.size())
inst_id = instr_descr[inst_index].op;
inst_id = instr_descr.at(instr_decoder.decode_instr(instr)).op;
// pre execution stuff
this->core.reg.last_branch = 0;
@ -279,7 +279,6 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
<%}%>if(this->disass_enabled){
/* generate console output when executing the command */<%instr.disass.eachLine{%>
${it}<%}%>
this->core.disass_output(pc.val, mnemonic);
}
// used registers<%instr.usedVariables.each{ k,v->
if(v.isArray) {%>

30
gen_input/templates/llvm/CORENAME.cpp.gtl
View File

@ -37,9 +37,7 @@
#include <iss/llvm/vm_base.h>
#include <util/logging.h>
#include <iss/instruction_decoder.h>
<%def fcsr = registers.find {it.name=='FCSR'}
if(fcsr != null) {%>
#include <vm/fp_functions.h><%}%>
#ifndef FMT_HEADER_ONLY
#define FMT_HEADER_ONLY
#endif
@ -85,9 +83,7 @@ protected:
using vm_base<ARCH>::get_reg_ptr;
inline const char *name(size_t index){return traits::reg_aliases.at(index);}
<%if(fcsr != null) {%>
inline const char *fname(size_t index){return index < 32?name(index+traits::F0):"illegal";}
<%}%>
template <typename T> inline ConstantInt *size(T type) {
return ConstantInt::get(getContext(), APInt(32, type->getType()->getScalarSizeInBits()));
}
@ -135,9 +131,7 @@ protected:
auto sign_mask = 1ULL<<(W-1);
return (from & mask) | ((from & sign_mask) ? ~mask : 0);
}
<%functions.each{ it.eachLine { %>
${it}<%}%>
<%}%>
private:
/****************************************************************************
* start opcode definitions
@ -218,7 +212,7 @@ private:
bb = this->leave_blk;
this->gen_instr_epilogue(bb);
this->builder.CreateBr(bb);
return std::make_tuple(ILLEGAL_INSTR, nullptr);
return std::make_tuple(BRANCH, nullptr);
}
};
@ -253,11 +247,19 @@ vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, unsigned int &inst_cnt,
auto *const data = (uint8_t *)&instr;
if(this->core.has_mmu())
paddr = this->core.virt2phys(pc);
//TODO: re-add page handling
// if ((pc.val & upper_bits) != ((pc.val + 2) & upper_bits)) { // we may cross a page boundary
// auto res = this->core.read(paddr, 2, data);
// if (res != iss::Ok) throw trap_access(TRAP_ID, pc.val);
// if ((instr & 0x3) == 0x3) { // this is a 32bit instruction
// res = this->core.read(this->core.v2p(pc + 2), 2, data + 2);
// }
// } else {
auto res = this->core.read(paddr, 4, data);
if (res != iss::Ok)
return std::make_tuple(ILLEGAL_FETCH, nullptr);
if (instr == 0x0000006f || (instr&0xffff)==0xa001)
return std::make_tuple(JUMP_TO_SELF, nullptr);
if (res != iss::Ok) throw trap_access(TRAP_ID, pc.val);
// }
if (instr == 0x0000006f || (instr&0xffff)==0xa001) throw simulation_stopped(0); // 'J 0' or 'C.J 0'
// curr pc on stack
++inst_cnt;
uint32_t inst_index = instr_decoder.decode_instr(instr);
compile_func f = nullptr;

71
gen_input/templates/tcc/CORENAME.cpp.gtl
View File

@ -38,9 +38,7 @@
#include <util/logging.h>
#include <sstream>
#include <iss/instruction_decoder.h>
<%def fcsr = registers.find {it.name=='FCSR'}
if(fcsr != null) {%>
#include <vm/fp_functions.h><%}%>
#ifndef FMT_HEADER_ONLY
#define FMT_HEADER_ONLY
#endif
@ -87,12 +85,7 @@ protected:
using compile_func = compile_ret_t (this_class::*)(virt_addr_t &pc, code_word_t instr, tu_builder&);
inline const char *name(size_t index){return traits::reg_aliases.at(index);}
<%
if(fcsr != null) {%>
inline const char *fname(size_t index){return index < 32?name(index+traits::F0):"illegal";}
void add_prologue(tu_builder& tu) override;
<%}%>
void setup_module(std::string m) override {
super::setup_module(m);
}
@ -105,6 +98,8 @@ if(fcsr != null) {%>
void gen_leave_trap(tu_builder& tu, unsigned lvl);
void gen_wait(tu_builder& tu, unsigned type);
inline void gen_set_tval(tu_builder& tu, uint64_t new_tval);
inline void gen_set_tval(tu_builder& tu, value new_tval);
@ -138,9 +133,6 @@ if(fcsr != null) {%>
return (from & mask) | ((from & sign_mask) ? ~mask : 0);
}
<%functions.each{ it.eachLine { %>
${it}<%}%>
<%}%>
private:
/****************************************************************************
* start opcode definitions
@ -171,7 +163,6 @@ private:
<%}%>if(this->disass_enabled){
/* generate console output when executing the command */<%instr.disass.eachLine{%>
${it}<%}%>
tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic);
}
auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]);
pc=pc+ ${instr.length/8};
@ -196,11 +187,11 @@ private:
tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, std::string("illegal_instruction"));
}
pc = pc + ((instr & 3) == 3 ? 4 : 2);
gen_raise_trap(tu, 0, static_cast<int32_t>(traits:: RV_CAUSE_ILLEGAL_INSTRUCTION));
gen_raise_trap(tu, 0, 2); // illegal instruction trap
this->gen_set_tval(tu, instr);
vm_impl::gen_sync(tu, iss::POST_SYNC, instr_descr.size());
vm_impl::gen_trap_check(tu);
return ILLEGAL_INSTR;
return BRANCH;
}
};
@ -233,11 +224,19 @@ vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, unsigned int &inst_cnt,
phys_addr_t paddr(pc);
if(this->core.has_mmu())
paddr = this->core.virt2phys(pc);
//TODO: re-add page handling
// if ((pc.val & upper_bits) != ((pc.val + 2) & upper_bits)) { // we may cross a page boundary
// auto res = this->core.read(paddr, 2, data);
// if (res != iss::Ok) throw trap_access(TRAP_ID, pc.val);
// if ((insn & 0x3) == 0x3) { // this is a 32bit instruction
// res = this->core.read(this->core.v2p(pc + 2), 2, data + 2);
// }
// } else {
auto res = this->core.read(paddr, 4, reinterpret_cast<uint8_t*>(&instr));
if (res != iss::Ok)
return ILLEGAL_FETCH;
if (instr == 0x0000006f || (instr&0xffff)==0xa001)
return JUMP_TO_SELF;
if (res != iss::Ok) throw trap_access(TRAP_ID, pc.val);
// }
if (instr == 0x0000006f || (instr&0xffff)==0xa001) throw simulation_stopped(0); // 'J 0' or 'C.J 0'
// curr pc on stack
++inst_cnt;
uint32_t inst_index = instr_decoder.decode_instr(instr);
compile_func f = nullptr;
@ -259,6 +258,9 @@ template <typename ARCH> void vm_impl<ARCH>::gen_leave_trap(tu_builder& tu, unsi
tu.store(traits::LAST_BRANCH, tu.constant(static_cast<int>(UNKNOWN_JUMP), 32));
}
template <typename ARCH> void vm_impl<ARCH>::gen_wait(tu_builder& tu, unsigned type) {
}
template <typename ARCH> void vm_impl<ARCH>::gen_set_tval(tu_builder& tu, uint64_t new_tval) {
tu(fmt::format("tval = {};", new_tval));
}
@ -273,39 +275,6 @@ template <typename ARCH> void vm_impl<ARCH>::gen_trap_behavior(tu_builder& tu) {
tu.store(traits::LAST_BRANCH, tu.constant(static_cast<int>(UNKNOWN_JUMP),32));
tu("return *next_pc;");
}
<%
if(fcsr != null) {%>
template <typename ARCH> void vm_impl<ARCH>::add_prologue(tu_builder& tu){
std::ostringstream os;
os << "uint32_t (*fget_flags)()=" << (uintptr_t)&fget_flags << ";\\n";
os << "uint32_t (*fadd_s)(uint32_t v1, uint32_t v2, uint8_t mode)=" << (uintptr_t)&fadd_s << ";\\n";
os << "uint32_t (*fsub_s)(uint32_t v1, uint32_t v2, uint8_t mode)=" << (uintptr_t)&fsub_s << ";\\n";
os << "uint32_t (*fmul_s)(uint32_t v1, uint32_t v2, uint8_t mode)=" << (uintptr_t)&fmul_s << ";\\n";
os << "uint32_t (*fdiv_s)(uint32_t v1, uint32_t v2, uint8_t mode)=" << (uintptr_t)&fdiv_s << ";\\n";
os << "uint32_t (*fsqrt_s)(uint32_t v1, uint8_t mode)=" << (uintptr_t)&fsqrt_s << ";\\n";
os << "uint32_t (*fcmp_s)(uint32_t v1, uint32_t v2, uint32_t op)=" << (uintptr_t)&fcmp_s << ";\\n";
os << "uint32_t (*fcvt_s)(uint32_t v1, uint32_t op, uint8_t mode)=" << (uintptr_t)&fcvt_s << ";\\n";
os << "uint32_t (*fmadd_s)(uint32_t v1, uint32_t v2, uint32_t v3, uint32_t op, uint8_t mode)=" << (uintptr_t)&fmadd_s << ";\\n";
os << "uint32_t (*fsel_s)(uint32_t v1, uint32_t v2, uint32_t op)=" << (uintptr_t)&fsel_s << ";\\n";
os << "uint32_t (*fclass_s)( uint32_t v1 )=" << (uintptr_t)&fclass_s << ";\\n";
os << "uint32_t (*fconv_d2f)(uint64_t v1, uint8_t mode)=" << (uintptr_t)&fconv_d2f << ";\\n";
os << "uint64_t (*fconv_f2d)(uint32_t v1, uint8_t mode)=" << (uintptr_t)&fconv_f2d << ";\\n";
os << "uint64_t (*fadd_d)(uint64_t v1, uint64_t v2, uint8_t mode)=" << (uintptr_t)&fadd_d << ";\\n";
os << "uint64_t (*fsub_d)(uint64_t v1, uint64_t v2, uint8_t mode)=" << (uintptr_t)&fsub_d << ";\\n";
os << "uint64_t (*fmul_d)(uint64_t v1, uint64_t v2, uint8_t mode)=" << (uintptr_t)&fmul_d << ";\\n";
os << "uint64_t (*fdiv_d)(uint64_t v1, uint64_t v2, uint8_t mode)=" << (uintptr_t)&fdiv_d << ";\\n";
os << "uint64_t (*fsqrt_d)(uint64_t v1, uint8_t mode)=" << (uintptr_t)&fsqrt_d << ";\\n";
os << "uint64_t (*fcmp_d)(uint64_t v1, uint64_t v2, uint32_t op)=" << (uintptr_t)&fcmp_d << ";\\n";
os << "uint64_t (*fcvt_d)(uint64_t v1, uint32_t op, uint8_t mode)=" << (uintptr_t)&fcvt_d << ";\\n";
os << "uint64_t (*fmadd_d)(uint64_t v1, uint64_t v2, uint64_t v3, uint32_t op, uint8_t mode)=" << (uintptr_t)&fmadd_d << ";\\n";
os << "uint64_t (*fsel_d)(uint64_t v1, uint64_t v2, uint32_t op)=" << (uintptr_t)&fsel_d << ";\\n";
os << "uint64_t (*fclass_d)(uint64_t v1 )=" << (uintptr_t)&fclass_d << ";\\n";
os << "uint64_t (*fcvt_32_64)(uint32_t v1, uint32_t op, uint8_t mode)=" << (uintptr_t)&fcvt_32_64 << ";\\n";
os << "uint32_t (*fcvt_64_32)(uint64_t v1, uint32_t op, uint8_t mode)=" << (uintptr_t)&fcvt_64_32 << ";\\n";
os << "uint32_t (*unbox_s)(uint64_t v)=" << (uintptr_t)&unbox_s << ";\\n";
tu.add_prologue(os.str());
}
<%}%>
} // namespace ${coreDef.name.toLowerCase()}

14
src/main.cpp
View File

@ -69,8 +69,7 @@ int main(int argc, char* argv[]) {
("logfile,l", po::value<std::string>(), "Sets default log file.")
("disass,d", po::value<std::string>()->implicit_value(""), "Enables disassembly")
("gdb-port,g", po::value<unsigned>()->default_value(0), "enable gdb server and specify port to use")
("ilimit,i", po::value<uint64_t>()->default_value(std::numeric_limits<uint64_t>::max()), "max. number of instructions to simulate")
("flimit", po::value<uint64_t>()->default_value(std::numeric_limits<uint64_t>::max()), "max. number of fetches to simulate")
("instructions,i", po::value<uint64_t>()->default_value(std::numeric_limits<uint64_t>::max()), "max. number of instructions to simulate")
("reset,r", po::value<std::string>(), "reset address")
("dump-ir", "dump the intermediate representation")
("elf,f", po::value<std::vector<std::string>>(), "ELF file(s) to load")
@ -216,15 +215,8 @@ int main(int argc, char* argv[]) {
start_address = str.find("0x") == 0 ? std::stoull(str.substr(2), nullptr, 16) : std::stoull(str, nullptr, 10);
}
vm->reset(start_address);
auto limit = clim["ilimit"].as<uint64_t>();
auto cond = iss::finish_cond_e::JUMP_TO_SELF;
if(clim.count("flimit")) {
cond = cond | iss::finish_cond_e::FCOUNT_LIMIT;
limit = clim["flimit"].as<uint64_t>();
} else {
cond = cond | iss::finish_cond_e::ICOUNT_LIMIT;
}
res = vm->start(limit, dump, cond);
auto cycles = clim["instructions"].as<uint64_t>();
res = vm->start(cycles, dump);
auto instr_if = vm->get_arch()->get_instrumentation_if();
// this assumes a single input file

119
src/vm/asmjit/vm_tgc5c.cpp
View File

@ -88,6 +88,7 @@ protected:
using super::write_reg_to_mem;
using super::gen_read_mem;
using super::gen_write_mem;
using super::gen_wait;
using super::gen_leave;
using super::gen_sync;
@ -112,7 +113,6 @@ protected:
auto sign_mask = 1ULL<<(W-1);
return (from & mask) | ((from & sign_mask) ? ~mask : 0);
}
private:
/****************************************************************************
* start opcode definitions
@ -500,7 +500,6 @@ private:
(gen_operation(cc, band, (gen_operation(cc, add, load_reg_from_mem(jh, traits::X0 + rs1), (int16_t)sext<12>(imm))
), addr_mask)
), 32, true);
{
auto label_merge = cc.newLabel();
cmp(cc, gen_operation(cc, urem, new_pc, static_cast<uint32_t>(traits::INSTR_ALIGNMENT))
,0);
@ -523,7 +522,6 @@ private:
}
cc.bind(label_merge);
}
}
auto returnValue = BRANCH;
gen_sync(jh, POST_SYNC, 3);
@ -568,7 +566,6 @@ private:
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
}
else{
{
auto label_merge = cc.newLabel();
cmp(cc, gen_operation(cc, eq, load_reg_from_mem(jh, traits::X0 + rs1), load_reg_from_mem(jh, traits::X0 + rs2))
,0);
@ -587,7 +584,6 @@ private:
}
cc.bind(label_merge);
}
}
auto returnValue = BRANCH;
gen_sync(jh, POST_SYNC, 4);
@ -632,7 +628,6 @@ private:
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
}
else{
{
auto label_merge = cc.newLabel();
cmp(cc, gen_operation(cc, ne, load_reg_from_mem(jh, traits::X0 + rs1), load_reg_from_mem(jh, traits::X0 + rs2))
,0);
@ -651,7 +646,6 @@ private:
}
cc.bind(label_merge);
}
}
auto returnValue = BRANCH;
gen_sync(jh, POST_SYNC, 5);
@ -696,7 +690,6 @@ private:
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
}
else{
{
auto label_merge = cc.newLabel();
cmp(cc, gen_operation(cc, lt, gen_ext(cc,
load_reg_from_mem(jh, traits::X0 + rs1), 32, false), gen_ext(cc,
@ -717,7 +710,6 @@ private:
}
cc.bind(label_merge);
}
}
auto returnValue = BRANCH;
gen_sync(jh, POST_SYNC, 6);
@ -762,7 +754,6 @@ private:
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
}
else{
{
auto label_merge = cc.newLabel();
cmp(cc, gen_operation(cc, gte, gen_ext(cc,
load_reg_from_mem(jh, traits::X0 + rs1), 32, false), gen_ext(cc,
@ -783,7 +774,6 @@ private:
}
cc.bind(label_merge);
}
}
auto returnValue = BRANCH;
gen_sync(jh, POST_SYNC, 7);
@ -828,7 +818,6 @@ private:
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
}
else{
{
auto label_merge = cc.newLabel();
cmp(cc, gen_operation(cc, ltu, load_reg_from_mem(jh, traits::X0 + rs1), load_reg_from_mem(jh, traits::X0 + rs2))
,0);
@ -847,7 +836,6 @@ private:
}
cc.bind(label_merge);
}
}
auto returnValue = BRANCH;
gen_sync(jh, POST_SYNC, 8);
@ -892,7 +880,6 @@ private:
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
}
else{
{
auto label_merge = cc.newLabel();
cmp(cc, gen_operation(cc, gteu, load_reg_from_mem(jh, traits::X0 + rs1), load_reg_from_mem(jh, traits::X0 + rs2))
,0);
@ -911,7 +898,6 @@ private:
}
cc.bind(label_merge);
}
}
auto returnValue = BRANCH;
gen_sync(jh, POST_SYNC, 9);
@ -2378,7 +2364,7 @@ private:
if(this->disass_enabled){
/* generate disass */
//No disass specified, using instruction name
//This disass is not yet implemented
std::string mnemonic = "ecall";
InvokeNode* call_print_disass;
char* mnemonic_ptr = strdup(mnemonic.c_str());
@ -2415,7 +2401,7 @@ private:
if(this->disass_enabled){
/* generate disass */
//No disass specified, using instruction name
//This disass is not yet implemented
std::string mnemonic = "ebreak";
InvokeNode* call_print_disass;
char* mnemonic_ptr = strdup(mnemonic.c_str());
@ -2452,7 +2438,7 @@ private:
if(this->disass_enabled){
/* generate disass */
//No disass specified, using instruction name
//This disass is not yet implemented
std::string mnemonic = "mret";
InvokeNode* call_print_disass;
char* mnemonic_ptr = strdup(mnemonic.c_str());
@ -2489,7 +2475,7 @@ private:
if(this->disass_enabled){
/* generate disass */
//No disass specified, using instruction name
//This disass is not yet implemented
std::string mnemonic = "wfi";
InvokeNode* call_print_disass;
char* mnemonic_ptr = strdup(mnemonic.c_str());
@ -2511,10 +2497,7 @@ private:
gen_instr_prologue(jh);
cc.comment("//behavior:");
/*generate behavior*/
InvokeNode* call_wait;
jh.cc.comment("//call_wait");
jh.cc.invoke(&call_wait, &wait, FuncSignature::build<void, int32_t>());
setArg(call_wait, 0, 1);
gen_wait(jh, 1);
auto returnValue = CONT;
gen_sync(jh, POST_SYNC, 41);
@ -3133,7 +3116,6 @@ private:
auto divisor = gen_ext(cc,
load_reg_from_mem(jh, traits::X0 + rs2), 32, true);
if(rd!=0){
{
auto label_merge = cc.newLabel();
cmp(cc, gen_operation(cc, ne, divisor, 0)
,0);
@ -3141,7 +3123,6 @@ private:
cc.je(label_else);
{
auto MMIN = ((uint32_t)1)<<(static_cast<uint32_t>(traits::XLEN)-1);
{
auto label_merge = cc.newLabel();
cmp(cc, gen_operation(cc, land, gen_operation(cc, eq, load_reg_from_mem(jh, traits::X0 + rs1), MMIN)
, gen_operation(cc, eq, divisor, - 1)
@ -3163,7 +3144,6 @@ private:
}
cc.bind(label_merge);
}
}
cc.jmp(label_merge);
cc.bind(label_else);
{
@ -3173,7 +3153,6 @@ private:
cc.bind(label_merge);
}
}
}
auto returnValue = CONT;
gen_sync(jh, POST_SYNC, 53);
@ -3217,7 +3196,6 @@ private:
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
}
else{
{
auto label_merge = cc.newLabel();
cmp(cc, gen_operation(cc, ne, load_reg_from_mem(jh, traits::X0 + rs2), 0)
,0);
@ -3240,7 +3218,6 @@ private:
}
cc.bind(label_merge);
}
}
auto returnValue = CONT;
gen_sync(jh, POST_SYNC, 54);
@ -3284,7 +3261,6 @@ private:
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
}
else{
{
auto label_merge = cc.newLabel();
cmp(cc, gen_operation(cc, ne, load_reg_from_mem(jh, traits::X0 + rs2), 0)
,0);
@ -3292,7 +3268,6 @@ private:
cc.je(label_else);
{
auto MMIN = (uint32_t)1<<(static_cast<uint32_t>(traits::XLEN)-1);
{
auto label_merge = cc.newLabel();
cmp(cc, gen_operation(cc, land, gen_operation(cc, eq, load_reg_from_mem(jh, traits::X0 + rs1), MMIN)
, gen_operation(cc, eq, gen_ext(cc,
@ -3322,7 +3297,6 @@ private:
}
cc.bind(label_merge);
}
}
cc.jmp(label_merge);
cc.bind(label_else);
{
@ -3333,7 +3307,6 @@ private:
}
cc.bind(label_merge);
}
}
auto returnValue = CONT;
gen_sync(jh, POST_SYNC, 55);
@ -3377,7 +3350,6 @@ private:
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
}
else{
{
auto label_merge = cc.newLabel();
cmp(cc, gen_operation(cc, ne, load_reg_from_mem(jh, traits::X0 + rs2), 0)
,0);
@ -3400,7 +3372,6 @@ private:
}
cc.bind(label_merge);
}
}
auto returnValue = CONT;
gen_sync(jh, POST_SYNC, 56);
@ -3417,7 +3388,7 @@ private:
/* generate disass */
auto mnemonic = fmt::format(
"{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "c.addi4spn"),
"{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "c__addi4spn"),
fmt::arg("rd", name(8+rd)), fmt::arg("imm", imm));
InvokeNode* call_print_disass;
char* mnemonic_ptr = strdup(mnemonic.c_str());
@ -3465,7 +3436,7 @@ private:
/* generate disass */
auto mnemonic = fmt::format(
"{mnemonic:10} {rd}, {uimm:#05x}({rs1})", fmt::arg("mnemonic", "c.lw"),
"{mnemonic:10} {rd}, {uimm:#05x}({rs1})", fmt::arg("mnemonic", "c__lw"),
fmt::arg("rd", name(8+rd)), fmt::arg("uimm", uimm), fmt::arg("rs1", name(8+rs1)));
InvokeNode* call_print_disass;
char* mnemonic_ptr = strdup(mnemonic.c_str());
@ -3511,7 +3482,7 @@ private:
/* generate disass */
auto mnemonic = fmt::format(
"{mnemonic:10} {rs2}, {uimm:#05x}({rs1})", fmt::arg("mnemonic", "c.sw"),
"{mnemonic:10} {rs2}, {uimm:#05x}({rs1})", fmt::arg("mnemonic", "c__sw"),
fmt::arg("rs2", name(8+rs2)), fmt::arg("uimm", uimm), fmt::arg("rs1", name(8+rs1)));
InvokeNode* call_print_disass;
char* mnemonic_ptr = strdup(mnemonic.c_str());
@ -3554,7 +3525,7 @@ private:
/* generate disass */
auto mnemonic = fmt::format(
"{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c.addi"),
"{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c__addi"),
fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm));
InvokeNode* call_print_disass;
char* mnemonic_ptr = strdup(mnemonic.c_str());
@ -3601,8 +3572,8 @@ private:
if(this->disass_enabled){
/* generate disass */
//No disass specified, using instruction name
std::string mnemonic = "c.nop";
//This disass is not yet implemented
std::string mnemonic = "c__nop";
InvokeNode* call_print_disass;
char* mnemonic_ptr = strdup(mnemonic.c_str());
jh.disass_collection.push_back(mnemonic_ptr);
@ -3638,7 +3609,7 @@ private:
/* generate disass */
auto mnemonic = fmt::format(
"{mnemonic:10} {imm:#05x}", fmt::arg("mnemonic", "c.jal"),
"{mnemonic:10} {imm:#05x}", fmt::arg("mnemonic", "c__jal"),
fmt::arg("imm", imm));
InvokeNode* call_print_disass;
char* mnemonic_ptr = strdup(mnemonic.c_str());
@ -3682,7 +3653,7 @@ private:
/* generate disass */
auto mnemonic = fmt::format(
"{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "c.li"),
"{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "c__li"),
fmt::arg("rd", name(rd)), fmt::arg("imm", imm));
InvokeNode* call_print_disass;
char* mnemonic_ptr = strdup(mnemonic.c_str());
@ -3729,7 +3700,7 @@ private:
/* generate disass */
auto mnemonic = fmt::format(
"{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "c.lui"),
"{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "c__lui"),
fmt::arg("rd", name(rd)), fmt::arg("imm", imm));
InvokeNode* call_print_disass;
char* mnemonic_ptr = strdup(mnemonic.c_str());
@ -3773,7 +3744,7 @@ private:
/* generate disass */
auto mnemonic = fmt::format(
"{mnemonic:10} {nzimm:#05x}", fmt::arg("mnemonic", "c.addi16sp"),
"{mnemonic:10} {nzimm:#05x}", fmt::arg("mnemonic", "c__addi16sp"),
fmt::arg("nzimm", nzimm));
InvokeNode* call_print_disass;
char* mnemonic_ptr = strdup(mnemonic.c_str());
@ -3818,8 +3789,8 @@ private:
if(this->disass_enabled){
/* generate disass */
//No disass specified, using instruction name
std::string mnemonic = ".reserved_clui";
//This disass is not yet implemented
std::string mnemonic = "__reserved_clui";
InvokeNode* call_print_disass;
char* mnemonic_ptr = strdup(mnemonic.c_str());
jh.disass_collection.push_back(mnemonic_ptr);
@ -3857,7 +3828,7 @@ private:
/* generate disass */
auto mnemonic = fmt::format(
"{mnemonic:10} {rs1}, {shamt}", fmt::arg("mnemonic", "c.srli"),
"{mnemonic:10} {rs1}, {shamt}", fmt::arg("mnemonic", "c__srli"),
fmt::arg("rs1", name(8+rs1)), fmt::arg("shamt", shamt));
InvokeNode* call_print_disass;
char* mnemonic_ptr = strdup(mnemonic.c_str());
@ -3898,7 +3869,7 @@ private:
/* generate disass */
auto mnemonic = fmt::format(
"{mnemonic:10} {rs1}, {shamt}", fmt::arg("mnemonic", "c.srai"),
"{mnemonic:10} {rs1}, {shamt}", fmt::arg("mnemonic", "c__srai"),
fmt::arg("rs1", name(8+rs1)), fmt::arg("shamt", shamt));
InvokeNode* call_print_disass;
char* mnemonic_ptr = strdup(mnemonic.c_str());
@ -3952,7 +3923,7 @@ private:
/* generate disass */
auto mnemonic = fmt::format(
"{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c.andi"),
"{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c__andi"),
fmt::arg("rs1", name(8+rs1)), fmt::arg("imm", imm));
InvokeNode* call_print_disass;
char* mnemonic_ptr = strdup(mnemonic.c_str());
@ -3994,7 +3965,7 @@ private:
/* generate disass */
auto mnemonic = fmt::format(
"{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c.sub"),
"{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c__sub"),
fmt::arg("rd", name(8+rd)), fmt::arg("rs2", name(8+rs2)));
InvokeNode* call_print_disass;
char* mnemonic_ptr = strdup(mnemonic.c_str());
@ -4036,7 +4007,7 @@ private:
/* generate disass */
auto mnemonic = fmt::format(
"{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c.xor"),
"{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c__xor"),
fmt::arg("rd", name(8+rd)), fmt::arg("rs2", name(8+rs2)));
InvokeNode* call_print_disass;
char* mnemonic_ptr = strdup(mnemonic.c_str());
@ -4077,7 +4048,7 @@ private:
/* generate disass */
auto mnemonic = fmt::format(
"{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c.or"),
"{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c__or"),
fmt::arg("rd", name(8+rd)), fmt::arg("rs2", name(8+rs2)));
InvokeNode* call_print_disass;
char* mnemonic_ptr = strdup(mnemonic.c_str());
@ -4118,7 +4089,7 @@ private:
/* generate disass */
auto mnemonic = fmt::format(
"{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c.and"),
"{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c__and"),
fmt::arg("rd", name(8+rd)), fmt::arg("rs2", name(8+rs2)));
InvokeNode* call_print_disass;
char* mnemonic_ptr = strdup(mnemonic.c_str());
@ -4158,7 +4129,7 @@ private:
/* generate disass */
auto mnemonic = fmt::format(
"{mnemonic:10} {imm:#05x}", fmt::arg("mnemonic", "c.j"),
"{mnemonic:10} {imm:#05x}", fmt::arg("mnemonic", "c__j"),
fmt::arg("imm", imm));
InvokeNode* call_print_disass;
char* mnemonic_ptr = strdup(mnemonic.c_str());
@ -4200,7 +4171,7 @@ private:
/* generate disass */
auto mnemonic = fmt::format(
"{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c.beqz"),
"{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c__beqz"),
fmt::arg("rs1", name(8+rs1)), fmt::arg("imm", imm));
InvokeNode* call_print_disass;
char* mnemonic_ptr = strdup(mnemonic.c_str());
@ -4223,7 +4194,6 @@ private:
cc.comment("//behavior:");
/*generate behavior*/
mov(jh.cc, get_ptr_for(jh, traits::LAST_BRANCH), static_cast<int>(NO_JUMP));
{
auto label_merge = cc.newLabel();
cmp(cc, gen_operation(cc, eq, load_reg_from_mem(jh, traits::X0 + rs1+8), 0)
,0);
@ -4234,7 +4204,6 @@ private:
mov(cc, get_ptr_for(jh, traits::LAST_BRANCH), static_cast<int>(KNOWN_JUMP));
}
cc.bind(label_merge);
}
auto returnValue = BRANCH;
gen_sync(jh, POST_SYNC, 75);
@ -4251,7 +4220,7 @@ private:
/* generate disass */
auto mnemonic = fmt::format(
"{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c.bnez"),
"{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c__bnez"),
fmt::arg("rs1", name(8+rs1)), fmt::arg("imm", imm));
InvokeNode* call_print_disass;
char* mnemonic_ptr = strdup(mnemonic.c_str());
@ -4274,7 +4243,6 @@ private:
cc.comment("//behavior:");
/*generate behavior*/
mov(jh.cc, get_ptr_for(jh, traits::LAST_BRANCH), static_cast<int>(NO_JUMP));
{
auto label_merge = cc.newLabel();
cmp(cc, gen_operation(cc, ne, load_reg_from_mem(jh, traits::X0 + rs1+8), 0)
,0);
@ -4285,7 +4253,6 @@ private:
mov(cc, get_ptr_for(jh, traits::LAST_BRANCH), static_cast<int>(KNOWN_JUMP));
}
cc.bind(label_merge);
}
auto returnValue = BRANCH;
gen_sync(jh, POST_SYNC, 76);
@ -4302,7 +4269,7 @@ private:
/* generate disass */
auto mnemonic = fmt::format(
"{mnemonic:10} {rs1}, {nzuimm}", fmt::arg("mnemonic", "c.slli"),
"{mnemonic:10} {rs1}, {nzuimm}", fmt::arg("mnemonic", "c__slli"),
fmt::arg("rs1", name(rs1)), fmt::arg("nzuimm", nzuimm));
InvokeNode* call_print_disass;
char* mnemonic_ptr = strdup(mnemonic.c_str());
@ -4350,7 +4317,7 @@ private:
/* generate disass */
auto mnemonic = fmt::format(
"{mnemonic:10} {rd}, sp, {uimm:#05x}", fmt::arg("mnemonic", "c.lwsp"),
"{mnemonic:10} {rd}, sp, {uimm:#05x}", fmt::arg("mnemonic", "c__lwsp"),
fmt::arg("rd", name(rd)), fmt::arg("uimm", uimm));
InvokeNode* call_print_disass;
char* mnemonic_ptr = strdup(mnemonic.c_str());
@ -4400,7 +4367,7 @@ private:
/* generate disass */
auto mnemonic = fmt::format(
"{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c.mv"),
"{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c__mv"),
fmt::arg("rd", name(rd)), fmt::arg("rs2", name(rs2)));
InvokeNode* call_print_disass;
char* mnemonic_ptr = strdup(mnemonic.c_str());
@ -4446,7 +4413,7 @@ private:
/* generate disass */
auto mnemonic = fmt::format(
"{mnemonic:10} {rs1}", fmt::arg("mnemonic", "c.jr"),
"{mnemonic:10} {rs1}", fmt::arg("mnemonic", "c__jr"),
fmt::arg("rs1", name(rs1)));
InvokeNode* call_print_disass;
char* mnemonic_ptr = strdup(mnemonic.c_str());
@ -4492,8 +4459,8 @@ private:
if(this->disass_enabled){
/* generate disass */
//No disass specified, using instruction name
std::string mnemonic = ".reserved_cmv";
//This disass is not yet implemented
std::string mnemonic = "__reserved_cmv";
InvokeNode* call_print_disass;
char* mnemonic_ptr = strdup(mnemonic.c_str());
jh.disass_collection.push_back(mnemonic_ptr);
@ -4531,7 +4498,7 @@ private:
/* generate disass */
auto mnemonic = fmt::format(
"{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c.add"),
"{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c__add"),
fmt::arg("rd", name(rd)), fmt::arg("rs2", name(rs2)));
InvokeNode* call_print_disass;
char* mnemonic_ptr = strdup(mnemonic.c_str());
@ -4579,7 +4546,7 @@ private:
/* generate disass */
auto mnemonic = fmt::format(
"{mnemonic:10} {rs1}", fmt::arg("mnemonic", "c.jalr"),
"{mnemonic:10} {rs1}", fmt::arg("mnemonic", "c__jalr"),
fmt::arg("rs1", name(rs1)));
InvokeNode* call_print_disass;
char* mnemonic_ptr = strdup(mnemonic.c_str());
@ -4628,8 +4595,8 @@ private:
if(this->disass_enabled){
/* generate disass */
//No disass specified, using instruction name
std::string mnemonic = "c.ebreak";
//This disass is not yet implemented
std::string mnemonic = "c__ebreak";
InvokeNode* call_print_disass;
char* mnemonic_ptr = strdup(mnemonic.c_str());
jh.disass_collection.push_back(mnemonic_ptr);
@ -4667,7 +4634,7 @@ private:
/* generate disass */
auto mnemonic = fmt::format(
"{mnemonic:10} {rs2}, {uimm:#05x}(sp)", fmt::arg("mnemonic", "c.swsp"),
"{mnemonic:10} {rs2}, {uimm:#05x}(sp)", fmt::arg("mnemonic", "c__swsp"),
fmt::arg("rs2", name(rs2)), fmt::arg("uimm", uimm));
InvokeNode* call_print_disass;
char* mnemonic_ptr = strdup(mnemonic.c_str());
@ -4712,7 +4679,7 @@ private:
if(this->disass_enabled){
/* generate disass */
//No disass specified, using instruction name
//This disass is not yet implemented
std::string mnemonic = "dii";
InvokeNode* call_print_disass;
char* mnemonic_ptr = strdup(mnemonic.c_str());
@ -4768,7 +4735,7 @@ private:
gen_raise(jh, 0, 2);
gen_sync(jh, POST_SYNC, instr_descr.size());
gen_instr_epilogue(jh);
return ILLEGAL_INSTR;
return BRANCH;
}
};
@ -4797,9 +4764,9 @@ continuation_e vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, unsigned
paddr = this->core.virt2phys(pc);
auto res = this->core.read(paddr, 4, data);
if (res != iss::Ok)
return ILLEGAL_FETCH;
throw trap_access(TRAP_ID, pc.val);
if (instr == 0x0000006f || (instr&0xffff)==0xa001)
return JUMP_TO_SELF;
throw simulation_stopped(0); // 'J 0' or 'C.J 0'
++inst_cnt;
uint32_t inst_index = instr_decoder.decode_instr(instr);
compile_func f = nullptr;

40
src/vm/interp/vm_tgc5c.cpp
View File

@ -343,7 +343,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
uint32_t inst_index = instr_decoder.decode_instr(instr);
opcode_e inst_id = arch::traits<ARCH>::opcode_e::MAX_OPCODE;;
if(inst_index <instr_descr.size())
inst_id = instr_descr[inst_index].op;
inst_id = instr_descr.at(instr_decoder.decode_instr(instr)).op;
// pre execution stuff
this->core.reg.last_branch = 0;
@ -1458,9 +1458,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
case arch::traits<ARCH>::opcode_e::ECALL: {
if(this->disass_enabled){
/* generate console output when executing the command */
//No disass specified, using instruction name
std::string mnemonic = "ecall";
this->core.disass_output(pc.val, mnemonic);
this->core.disass_output(pc.val, "ecall");
}
// used registers// calculate next pc value
*NEXT_PC = *PC + 4;
@ -1473,9 +1471,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
case arch::traits<ARCH>::opcode_e::EBREAK: {
if(this->disass_enabled){
/* generate console output when executing the command */
//No disass specified, using instruction name
std::string mnemonic = "ebreak";
this->core.disass_output(pc.val, mnemonic);
this->core.disass_output(pc.val, "ebreak");
}
// used registers// calculate next pc value
*NEXT_PC = *PC + 4;
@ -1488,9 +1484,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
case arch::traits<ARCH>::opcode_e::MRET: {
if(this->disass_enabled){
/* generate console output when executing the command */
//No disass specified, using instruction name
std::string mnemonic = "mret";
this->core.disass_output(pc.val, mnemonic);
this->core.disass_output(pc.val, "mret");
}
// used registers// calculate next pc value
*NEXT_PC = *PC + 4;
@ -1503,9 +1497,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
case arch::traits<ARCH>::opcode_e::WFI: {
if(this->disass_enabled){
/* generate console output when executing the command */
//No disass specified, using instruction name
std::string mnemonic = "wfi";
this->core.disass_output(pc.val, mnemonic);
this->core.disass_output(pc.val, "wfi");
}
// used registers// calculate next pc value
*NEXT_PC = *PC + 4;
@ -1729,7 +1721,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
if(this->disass_enabled){
/* generate console output when executing the command */
auto mnemonic = fmt::format(
"{mnemonic:10} {rs1}, {rd}, {imm}", fmt::arg("mnemonic", "fence_i"),
"{mnemonic:10} {rs1}, {rd}, {imm}", fmt::arg("mnemonic", "fence.i"),
fmt::arg("rs1", name(rs1)), fmt::arg("rd", name(rd)), fmt::arg("imm", imm));
this->core.disass_output(pc.val, mnemonic);
}
@ -2103,9 +2095,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
uint8_t nzimm = ((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5));
if(this->disass_enabled){
/* generate console output when executing the command */
//No disass specified, using instruction name
std::string mnemonic = "c.nop";
this->core.disass_output(pc.val, mnemonic);
this->core.disass_output(pc.val, "c.nop");
}
// used registers// calculate next pc value
*NEXT_PC = *PC + 2;
@ -2211,9 +2201,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
uint8_t rd = ((bit_sub<7,5>(instr)));
if(this->disass_enabled){
/* generate console output when executing the command */
//No disass specified, using instruction name
std::string mnemonic = ".reserved_clui";
this->core.disass_output(pc.val, mnemonic);
this->core.disass_output(pc.val, ".reserved_clui");
}
// used registers// calculate next pc value
*NEXT_PC = *PC + 2;
@ -2532,9 +2520,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
case arch::traits<ARCH>::opcode_e::__reserved_cmv: {
if(this->disass_enabled){
/* generate console output when executing the command */
//No disass specified, using instruction name
std::string mnemonic = ".reserved_cmv";
this->core.disass_output(pc.val, mnemonic);
this->core.disass_output(pc.val, ".reserved_cmv");
}
// used registers// calculate next pc value
*NEXT_PC = *PC + 2;
@ -2600,9 +2586,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
case arch::traits<ARCH>::opcode_e::C__EBREAK: {
if(this->disass_enabled){
/* generate console output when executing the command */
//No disass specified, using instruction name
std::string mnemonic = "c.ebreak";
this->core.disass_output(pc.val, mnemonic);
this->core.disass_output(pc.val, "c.ebreak");
}
// used registers// calculate next pc value
*NEXT_PC = *PC + 2;
@ -2641,9 +2625,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
case arch::traits<ARCH>::opcode_e::DII: {
if(this->disass_enabled){
/* generate console output when executing the command */
//No disass specified, using instruction name
std::string mnemonic = "dii";
this->core.disass_output(pc.val, mnemonic);
this->core.disass_output(pc.val, "dii");
}
// used registers// calculate next pc value
*NEXT_PC = *PC + 2;

350
src/vm/llvm/vm_tgc5c.cpp
View File

File diff suppressed because it is too large Load Diff

531
src/vm/tcc/vm_tgc5c.cpp
View File

File diff suppressed because it is too large Load Diff