add missing change

incl/iss/factory.h

@@ -0,0 +1,62 @@
+/*******************************************************************************
+ * Copyright (C) 2021 MINRES Technologies GmbH
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ *******************************************************************************/
+
+#ifndef _ISS_FACTORY_H_
+#define _ISS_FACTORY_H_
+
+#include <iss/iss.h>
+
+namespace iss {
+
+using cpu_ptr = std::unique_ptr<iss::arch_if>;
+using vm_ptr= std::unique_ptr<iss::vm_if>;
+
+template<typename PLAT>
+std::tuple<cpu_ptr, vm_ptr> create_cpu(std::string const& backend, unsigned gdb_port){
+    using core_type = typename PLAT::super;
+    core_type* lcpu = new PLAT();
+    if(backend == "interp")
+        return {cpu_ptr{lcpu}, vm_ptr{iss::interp::create(lcpu, gdb_port)}};
+#ifdef WITH_LLVM
+    if(backend == "llvm")
+        return {cpu_ptr{lcpu}, vm_ptr{iss::llvm::create(lcpu, gdb_port)}};
+#endif
+#ifdef WITH_LLVM
+    if(backend == "tcc")
+        return {cpu_ptr{lcpu}, vm_ptr{iss::tcc::create(lcpu, gdb_port)}};
+#endif
+    return {nullptr, nullptr};
+}
+
+}
+
+#endif /* _ISS_FACTORY_H_ */

src/main.cpp

@@ -31,18 +31,23 @@
  *******************************************************************************/
 
 #include <iostream>
-#include <iss/iss.h>
+#include <iss/factory.h>
 
 #include <boost/lexical_cast.hpp>
 #include <boost/program_options.hpp>
 #include <iss/arch/riscv_hart_m_p.h>
-#ifdef CORE_TGC_C
+#include "iss/arch/riscv_hart_m_p.h"
 #include "iss/arch/tgc_c.h"
-using core_type = iss::arch::tgc_c;
+using tgc_c_plat_type = iss::arch::riscv_hart_m_p<iss::arch::tgc_c>;
+#ifdef CORE_TGC_B
+#include "iss/arch/riscv_hart_m_p.h"
+#include "iss/arch/tgc_b.h"
+using tgc_b_plat_type = iss::arch::riscv_hart_m_p<iss::arch::tgc_b>;
 #endif
 #ifdef CORE_TGC_D
+#include "iss/arch/riscv_hart_mu_p.h"
 #include "iss/arch/tgc_d.h"
-using core_type = iss::arch::tgc_d;
+using tgc_d_plat_type = iss::arch::riscv_hart_mu_p<iss::arch::tgc_d>;
 #endif
 #ifdef WITH_LLVM
 #include <iss/llvm/jit_helper.h>
@@ -53,23 +58,6 @@ using core_type = iss::arch::tgc_d;
 
 namespace po = boost::program_options;
 
-using cpu_ptr = std::unique_ptr<iss::arch_if>;
-using vm_ptr= std::unique_ptr<iss::vm_if>;
-
-template<typename CORE>
-std::tuple<cpu_ptr, vm_ptr> create_cpu(std::string const& backend, unsigned gdb_port){
-    CORE* lcpu = new iss::arch::riscv_hart_m_p<CORE>();
-    if(backend == "interp")
-        return {cpu_ptr{lcpu}, vm_ptr{iss::interp::create(lcpu, gdb_port)}};
-#ifdef WITH_LLVM
-    if(backend == "llvm")
-        return {cpu_ptr{lcpu}, vm_ptr{iss::llvm::create(lcpu, gdb_port)}};
-#endif
-//    if(backend == "tcc")
-//        return {cpu_ptr{lcpu}, vm_ptr{iss::tcc::create(lcpu, gdb_port)}};
-    return {nullptr, nullptr};
-}
-
 int main(int argc, char *argv[]) {
     /*
      *  Define and parse the program options
@@ -132,19 +120,26 @@ int main(int argc, char *argv[]) {
 #endif
         bool dump = clim.count("dump-ir");
         // instantiate the simulator
-        vm_ptr vm{nullptr};
+        iss::vm_ptr vm{nullptr};
-        cpu_ptr cpu{nullptr};
+        iss::cpu_ptr cpu{nullptr};
         std::string isa_opt(clim["isa"].as<std::string>());
-#ifdef WITH_TGF_B
-        if (isa_opt == "tgf_b") {
-            std::tie(cpu, vm) =
-                create_cpu<iss::arch::tgf_b>(clim["backend"].as<std::string>(), clim["gdb-port"].as<unsigned>());
-        } else
-#endif
         if (isa_opt == "tgf_c") {
             std::tie(cpu, vm) =
-                create_cpu<core_type>(clim["backend"].as<std::string>(), clim["gdb-port"].as<unsigned>());
+                iss::create_cpu<tgc_c_plat_type>(clim["backend"].as<std::string>(), clim["gdb-port"].as<unsigned>());
-        } else {
+        } else
+#ifdef CORE_TGC_B
+        if (isa_opt == "tgf_b") {
+            std::tie(cpu, vm) =
+                iss::create_cpu<tgc_b_plat_type>(clim["backend"].as<std::string>(), clim["gdb-port"].as<unsigned>());
+        } else
+#endif
+#ifdef CORE_TGC_D
+        if (isa_opt == "tgf_d") {
+            std::tie(cpu, vm) =
+                iss::create_cpu<tgc_d_plat_type>(clim["backend"].as<std::string>(), clim["gdb-port"].as<unsigned>());
+        } else
+#endif
+        {
             LOG(ERROR) << "Illegal argument value for '--isa': " << clim["isa"].as<std::string>() << std::endl;
             return 127;
         }
@@ -183,7 +178,7 @@ int main(int argc, char *argv[]) {
         }
         uint64_t start_address = 0;
         if (clim.count("mem"))
-            vm->get_arch()->load_file(clim["mem"].as<std::string>(), iss::arch::traits<core_type>::MEM);
+            vm->get_arch()->load_file(clim["mem"].as<std::string>());
         if (clim.count("elf"))
             for (std::string input : clim["elf"].as<std::vector<std::string>>()) {
                 auto start_addr = vm->get_arch()->load_file(input);

src/sysc/core_complex.cpp

@@ -58,7 +58,7 @@ using tgc_d_plat_type = iss::arch::riscv_hart_mu_p<iss::arch::tgc_d>;
 
 #define STR(X) #X
 #define CREATE_CORE(CN) \
-else if (type == STR(CN)) { std::tie(cpu, vm) = create_core<CN ## _plat_type>(backend, gdb_port, hart_id); }
+if (type == STR(CN)) { std::tie(cpu, vm) = create_core<CN ## _plat_type>(backend, gdb_port, hart_id); } else
 
 #ifdef WITH_SCV
 #include <array>
@@ -261,19 +261,14 @@ public:
     }
 
     void create_cpu(std::string const& type, std::string const& backend, unsigned gdb_port, uint32_t hart_id){
-       if (type == "") {
-           LOG(ERROR) << "Illegal argument value for core type: " << type << std::endl;
-       }
-#ifdef CORE_TGC_B
         CREATE_CORE(tgc_c)
-#endif
+#ifdef CORE_TGC_B
-#ifdef CORE_TGC_C
         CREATE_CORE(tgc_c)
 #endif
 #ifdef CORE_TGC_D
         CREATE_CORE(tgc_d)
 #endif
-        else {
+        {
             LOG(ERROR) << "Illegal argument value for core type: " << type << std::endl;
         }
         auto *srv = debugger::server<debugger::gdb_session>::get();
@@ -286,7 +281,6 @@ public:
 
     }
 
-
     core_complex * const owner;
     vm_ptr vm{nullptr};
     cpu_ptr cpu{nullptr};