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base: DBT-RISE:75e81ce2361f343017b0a06ed32bcd851ee4716c
Branches Tags
DBT-RISE:main
DBT-RISE:develop
DBT-RISE:feature/htif
DBT-RISE:feature/iss_factory
DBT-RISE:feature/core_factory
DBT-RISE:Trace_enhancement
DBT-RISE:feature/reduced_output
DBT-RISE:msvc_compat
DBT-RISE:hotfix/latest_scc
DBT-RISE:feature/interpreter
..
compare: DBT-RISE:ad604490738a9e5115804c3ab366b39c251f9137
Branches Tags
DBT-RISE:main
DBT-RISE:develop
DBT-RISE:feature/htif
DBT-RISE:feature/iss_factory
DBT-RISE:feature/core_factory
DBT-RISE:Trace_enhancement
DBT-RISE:feature/reduced_output
DBT-RISE:msvc_compat
DBT-RISE:hotfix/latest_scc
DBT-RISE:feature/interpreter

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75e81ce236 ... ad60449073

3 changed files with 171 additions and 225 deletions
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132
src/iss/arch/riscv_hart_m_p.h
View File

@ -354,7 +354,7 @@ protected:
using csr_page_type = typename csr_type::page_type; using csr_page_type = typename csr_type::page_type;
mem_type mem; mem_type mem;
csr_type csr; csr_type csr;
std::stringstream io_buf; std::stringstream uart_buf;
std::unordered_map<reg_t, uint64_t> ptw; std::unordered_map<reg_t, uint64_t> ptw;
std::unordered_map<uint64_t, uint8_t> atomic_reservation; std::unordered_map<uint64_t, uint8_t> atomic_reservation;
std::unordered_map<unsigned, rd_csr_f> csr_rd_cb; std::unordered_map<unsigned, rd_csr_f> csr_rd_cb;
@ -446,7 +446,7 @@ riscv_hart_m_p<BASE, FEAT, LOGCAT>::riscv_hart_m_p(feature_config cfg)
csr[marchid] = traits<BASE>::MARCHID_VAL; csr[marchid] = traits<BASE>::MARCHID_VAL;
csr[mimpid] = 1; csr[mimpid] = 1;
io_buf.str(""); uart_buf.str("");
if(traits<BASE>::FLEN > 0) { if(traits<BASE>::FLEN > 0) {
csr_rd_cb[fcsr] = &this_class::read_fcsr; csr_rd_cb[fcsr] = &this_class::read_fcsr;
csr_wr_cb[fcsr] = &this_class::write_fcsr; csr_wr_cb[fcsr] = &this_class::write_fcsr;
@ -720,7 +720,7 @@ iss::status riscv_hart_m_p<BASE, FEAT, LOGCAT>::write(const address_type type, c
return iss::Err; return iss::Err;
} }
try { try {
if(length > 1 && (addr & (length - 1)) && !is_debug(access)) { if(length > 1 && (addr & (length - 1)) && (access & access_type::DEBUG) != access_type::DEBUG) {
this->reg.trap_state = (1UL << 31) | 6 << 16; this->reg.trap_state = (1UL << 31) | 6 << 16;
fault_data = addr; fault_data = addr;
return iss::Err; return iss::Err;
@ -740,7 +740,7 @@ iss::status riscv_hart_m_p<BASE, FEAT, LOGCAT>::write(const address_type type, c
} else { } else {
res = write_mem(phys_addr, length, data); res = write_mem(phys_addr, length, data);
} }
if(unlikely(res != iss::Ok && !is_debug(access))) { if(unlikely(res != iss::Ok && (access & access_type::DEBUG) == 0)) {
this->reg.trap_state = (1UL << 31) | (7UL << 16); // issue trap 7 (Store/AMO access fault) this->reg.trap_state = (1UL << 31) | (7UL << 16); // issue trap 7 (Store/AMO access fault)
fault_data = addr; fault_data = addr;
} }
@ -756,10 +756,10 @@ iss::status riscv_hart_m_p<BASE, FEAT, LOGCAT>::write(const address_type type, c
switch(addr) { switch(addr) {
case 0x10013000: // UART0 base, TXFIFO reg case 0x10013000: // UART0 base, TXFIFO reg
case 0x10023000: // UART1 base, TXFIFO reg case 0x10023000: // UART1 base, TXFIFO reg
io_buf << (char)data[0]; uart_buf << (char)data[0];
if(((char)data[0]) == '\n' || data[0] == 0) { if(((char)data[0]) == '\n' || data[0] == 0) {
std::cout << io_buf.str(); std::cout << uart_buf.str();
io_buf.str(""); uart_buf.str("");
} }
return iss::Ok; return iss::Ok;
case 0x10008000: { // HFROSC base, hfrosccfg reg case 0x10008000: { // HFROSC base, hfrosccfg reg
@ -1094,79 +1094,59 @@ iss::status riscv_hart_m_p<BASE, FEAT, LOGCAT>::read_mem(phys_addr_t paddr, unsi
template <typename BASE, features_e FEAT, typename LOGCAT> template <typename BASE, features_e FEAT, typename LOGCAT>
iss::status riscv_hart_m_p<BASE, FEAT, LOGCAT>::write_mem(phys_addr_t paddr, unsigned length, const uint8_t* const data) { iss::status riscv_hart_m_p<BASE, FEAT, LOGCAT>::write_mem(phys_addr_t paddr, unsigned length, const uint8_t* const data) {
mem_type::page_type& p = mem(paddr.val / mem.page_size); switch(paddr.val) {
std::copy(data, data + length, p.data() + (paddr.val & mem.page_addr_mask)); // TODO remove UART, Peripherals should not be part of the ISS
// tohost handling in case of riscv-test case 0xFFFF0000: // UART0 base, TXFIFO reg
// according to https://github.com/riscv-software-src/riscv-isa-sim/issues/364#issuecomment-607657754: if(((char)data[0]) == '\n' || data[0] == 0) {
if(paddr.access && iss::access_type::FUNC) { CPPLOG(INFO) << "UART" << ((paddr.val >> 12) & 0x3) << " send '" << uart_buf.str() << "'";
if(paddr.val == tohost) { uart_buf.str("");
if(traits<BASE>::XLEN == 32) } else if(((char)data[0]) != '\r')
tohost &= 0x00000000ffffffff; uart_buf << (char)data[0];
// Extract Device (bits 63:56) break;
uint8_t device = (tohost >> 56) & 0xFF; default: {
// Extract Command (bits 55:48) mem_type::page_type& p = mem(paddr.val / mem.page_size);
uint8_t command = (tohost >> 48) & 0xFF; std::copy(data, data + length, p.data() + (paddr.val & mem.page_addr_mask));
// Extract payload (bits 47:0) // tohost handling in case of riscv-test
uint64_t payload = tohost & 0xFFFFFFFFFFFFULL; if(paddr.access && iss::access_type::FUNC) {
if(payload & 1) { auto tohost_upper =
CPPLOG(FATAL) << "tohost value is 0x" << std::hex << payload << std::dec << " (" << payload << "), stopping simulation"; (traits<BASE>::XLEN == 32 && paddr.val == (tohost + 4)) || (traits<BASE>::XLEN == 64 && paddr.val == tohost);
this->reg.trap_state = std::numeric_limits<uint32_t>::max(); auto tohost_lower = (traits<BASE>::XLEN == 32 && paddr.val == tohost) || (traits<BASE>::XLEN == 64 && paddr.val == tohost);
this->interrupt_sim = payload; if(tohost_lower || tohost_upper) {
return iss::Ok; uint64_t hostvar = *reinterpret_cast<uint64_t*>(p.data() + (tohost & mem.page_addr_mask));
} else if(device == 0 && command == 0) { // in case of 32 bit system, two writes to tohost are needed, only evaluate on the second (high) write
reg_t payload_addr; if(tohost_upper && (tohost_lower || tohost_lower_written)) {
// payload contains the addr of the struct containing information about the syscall switch(hostvar >> 48) {
read(address_type::PHYSICAL, access_type::READ, traits<BASE>::MEM, payload, sizeof(reg_t), case 0:
reinterpret_cast<uint8_t*>(&payload_addr)); if(hostvar != 0x1) {
// If the payload_addr is missaligned end simulation CPPLOG(FATAL) << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar
if(payload_addr & 1) { << "), stopping simulation";
CPPLOG(FATAL) << "tohost payload value is 0x" << std::hex << payload_addr << std::dec << " (" << payload_addr } else {
<< "), stopping simulation"; CPPLOG(INFO) << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar
this->reg.trap_state = std::numeric_limits<uint32_t>::max(); << "), stopping simulation";
this->interrupt_sim = payload; }
return iss::Ok; this->reg.trap_state = std::numeric_limits<uint32_t>::max();
} this->interrupt_sim = hostvar;
// read the entire struct into an array break;
reg_t loaded_payload[8]; case 0x0101: {
read(address_type::PHYSICAL, access_type::READ, traits<BASE>::MEM, payload_addr, sizeof(loaded_payload), char c = static_cast<char>(hostvar & 0xff);
reinterpret_cast<uint8_t*>(loaded_payload)); if(c == '\n' || c == 0) {
reg_t syscall_num = loaded_payload[0]; CPPLOG(INFO) << "tohost send '" << uart_buf.str() << "'";
if(syscall_num == 64) { // SYS_WRITE uart_buf.str("");
reg_t fd = loaded_payload[1];
reg_t buf_ptr = loaded_payload[2];
reg_t len = loaded_payload[3];
std::vector<char> buf(len);
read(address_type::PHYSICAL, access_type::READ, traits<BASE>::MEM, buf_ptr, len,
reinterpret_cast<uint8_t*>(buf.data()));
// we disregard the fd and just log to stdout
for(size_t i = 0; i < len; i++) {
if(buf[i] == '\n') {
CPPLOG(INFO) << "tohost send '" << io_buf.str() << "'";
io_buf.str("");
} else } else
io_buf << buf[i]; uart_buf << c;
} break;
default:
break;
} }
// Not sure what the correct return value should be tohost_lower_written = false;
uint8_t ret_val = 1; } else if(tohost_lower)
write(address_type::PHYSICAL, access_type::WRITE, traits<BASE>::MEM, fromhost, 1, &ret_val); tohost_lower_written = true;
} else { } else if((traits<BASE>::XLEN == 32 && paddr.val == fromhost + 4) || (traits<BASE>::XLEN == 64 && paddr.val == fromhost)) {
CPPLOG(ERR) << "tohost syscall with number " << std::hex << syscall_num << std::dec << " (" << syscall_num uint64_t fhostvar = *reinterpret_cast<uint64_t*>(p.data() + (fromhost & mem.page_addr_mask));
<< ") not implemented"; *reinterpret_cast<uint64_t*>(p.data() + (tohost & mem.page_addr_mask)) = fhostvar;
this->reg.trap_state = std::numeric_limits<uint32_t>::max();
this->interrupt_sim = payload;
return iss::Ok;
}
} else {
CPPLOG(ERR) << "tohost functionality not implemented for device " << device << " and command " << command;
this->reg.trap_state = std::numeric_limits<uint32_t>::max();
this->interrupt_sim = payload;
return iss::Ok;
} }
} }
if((traits<BASE>::XLEN == 32 && paddr.val == fromhost + 4) || (traits<BASE>::XLEN == 64 && paddr.val == fromhost)) { }
uint64_t fhostvar = *reinterpret_cast<uint64_t*>(p.data() + (fromhost & mem.page_addr_mask));
*reinterpret_cast<uint64_t*>(p.data() + (tohost & mem.page_addr_mask)) = fhostvar;
}
} }
return iss::Ok; return iss::Ok;
} }

132
src/iss/arch/riscv_hart_msu_vp.h
View File

@ -404,7 +404,7 @@ protected:
mem_type mem; mem_type mem;
csr_type csr; csr_type csr;
void update_vm_info(); void update_vm_info();
std::stringstream io_buf; std::stringstream uart_buf;
std::unordered_map<reg_t, uint64_t> ptw; std::unordered_map<reg_t, uint64_t> ptw;
std::unordered_map<uint64_t, uint8_t> atomic_reservation; std::unordered_map<uint64_t, uint8_t> atomic_reservation;
std::unordered_map<unsigned, rd_csr_f> csr_rd_cb; std::unordered_map<unsigned, rd_csr_f> csr_rd_cb;
@ -459,7 +459,7 @@ riscv_hart_msu_vp<BASE>::riscv_hart_msu_vp()
csr[marchid] = traits<BASE>::MARCHID_VAL; csr[marchid] = traits<BASE>::MARCHID_VAL;
csr[mimpid] = 1; csr[mimpid] = 1;
io_buf.str(""); uart_buf.str("");
for(unsigned addr = mhpmcounter3; addr <= mhpmcounter31; ++addr) { for(unsigned addr = mhpmcounter3; addr <= mhpmcounter31; ++addr) {
csr_rd_cb[addr] = &this_class::read_null; csr_rd_cb[addr] = &this_class::read_null;
csr_wr_cb[addr] = &this_class::write_csr_reg; csr_wr_cb[addr] = &this_class::write_csr_reg;
@ -727,12 +727,12 @@ iss::status riscv_hart_msu_vp<BASE>::write(const address_type type, const access
switch(paddr.val) { switch(paddr.val) {
case 0x10013000: // UART0 base, TXFIFO reg case 0x10013000: // UART0 base, TXFIFO reg
case 0x10023000: // UART1 base, TXFIFO reg case 0x10023000: // UART1 base, TXFIFO reg
io_buf << (char)data[0]; uart_buf << (char)data[0];
if(((char)data[0]) == '\n' || data[0] == 0) { if(((char)data[0]) == '\n' || data[0] == 0) {
// CPPLOG(INFO)<<"UART"<<((paddr.val>>16)&0x3)<<" send // CPPLOG(INFO)<<"UART"<<((paddr.val>>16)&0x3)<<" send
// '"<<io_buf.str()<<"'"; // '"<<uart_buf.str()<<"'";
std::cout << io_buf.str(); std::cout << uart_buf.str();
io_buf.str(""); uart_buf.str("");
} }
return iss::Ok; return iss::Ok;
case 0x10008000: { // HFROSC base, hfrosccfg reg case 0x10008000: { // HFROSC base, hfrosccfg reg
@ -1024,79 +1024,61 @@ template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::read_mem(phys_addr
} }
template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::write_mem(phys_addr_t paddr, unsigned length, const uint8_t* const data) { template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::write_mem(phys_addr_t paddr, unsigned length, const uint8_t* const data) {
mem_type::page_type& p = mem(paddr.val / mem.page_size); switch(paddr.val) {
std::copy(data, data + length, p.data() + (paddr.val & mem.page_addr_mask)); case 0xFFFF0000: // UART0 base, TXFIFO reg
// tohost handling in case of riscv-test if(((char)data[0]) == '\n' || data[0] == 0) {
// according to https://github.com/riscv-software-src/riscv-isa-sim/issues/364#issuecomment-607657754: CPPLOG(INFO) << "UART" << ((paddr.val >> 12) & 0x3) << " send '" << uart_buf.str() << "'";
if(paddr.access && iss::access_type::FUNC) { uart_buf.str("");
if(paddr.val == tohost) { } else if(((char)data[0]) != '\r')
if(traits<BASE>::XLEN == 32) uart_buf << (char)data[0];
tohost &= 0x00000000ffffffff; break;
// Extract Device (bits 63:56) default: {
uint8_t device = (tohost >> 56) & 0xFF; mem_type::page_type& p = mem(paddr.val / mem.page_size);
// Extract Command (bits 55:48) std::copy(data, data + length, p.data() + (paddr.val & mem.page_addr_mask));
uint8_t command = (tohost >> 48) & 0xFF; // tohost handling in case of riscv-test
// Extract payload (bits 47:0) if(paddr.access && iss::access_type::FUNC) {
uint64_t payload = tohost & 0xFFFFFFFFFFFFULL; auto tohost_upper =
if(payload & 1) { (traits<BASE>::XLEN == 32 && paddr.val == (tohost + 4)) || (traits<BASE>::XLEN == 64 && paddr.val == tohost);
CPPLOG(FATAL) << "tohost value is 0x" << std::hex << payload << std::dec << " (" << payload << "), stopping simulation"; auto tohost_lower = (traits<BASE>::XLEN == 32 && paddr.val == tohost) || (traits<BASE>::XLEN == 64 && paddr.val == tohost);
this->reg.trap_state = std::numeric_limits<uint32_t>::max(); if(tohost_lower || tohost_upper) {
this->interrupt_sim = payload; uint64_t hostvar = *reinterpret_cast<uint64_t*>(p.data() + (tohost & mem.page_addr_mask));
return iss::Ok; // in case of 32 bit system, two writes to tohost are needed, only evaluate on the second (high) write
} else if(device == 0 && command == 0) { if(tohost_upper && (tohost_lower || tohost_lower_written)) {
reg_t payload_addr; switch(hostvar >> 48) {
// payload contains the addr of the struct containing information about the syscall case 0:
read(address_type::PHYSICAL, access_type::READ, traits<BASE>::MEM, payload, sizeof(reg_t), if(hostvar != 0x1) {
reinterpret_cast<uint8_t*>(&payload_addr)); CPPLOG(FATAL) << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar
// If the payload_addr is missaligned end simulation << "), stopping simulation";
if(payload_addr & 1) { } else {
CPPLOG(FATAL) << "tohost payload value is 0x" << std::hex << payload_addr << std::dec << " (" << payload_addr CPPLOG(INFO) << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar
<< "), stopping simulation"; << "), stopping simulation";
this->reg.trap_state = std::numeric_limits<uint32_t>::max(); }
this->interrupt_sim = payload; this->reg.trap_state = std::numeric_limits<uint32_t>::max();
return iss::Ok; this->interrupt_sim = hostvar;
} #ifndef WITH_TCC
// read the entire struct into an array throw(iss::simulation_stopped(hostvar));
reg_t loaded_payload[8]; #endif
read(address_type::PHYSICAL, access_type::READ, traits<BASE>::MEM, payload_addr, sizeof(loaded_payload), break;
reinterpret_cast<uint8_t*>(loaded_payload)); case 0x0101: {
reg_t syscall_num = loaded_payload[0]; char c = static_cast<char>(hostvar & 0xff);
if(syscall_num == 64) { // SYS_WRITE if(c == '\n' || c == 0) {
reg_t fd = loaded_payload[1]; CPPLOG(INFO) << "tohost send '" << uart_buf.str() << "'";
reg_t buf_ptr = loaded_payload[2]; uart_buf.str("");
reg_t len = loaded_payload[3];
std::vector<char> buf(len);
read(address_type::PHYSICAL, access_type::READ, traits<BASE>::MEM, buf_ptr, len,
reinterpret_cast<uint8_t*>(buf.data()));
// we disregard the fd and just log to stdout
for(size_t i = 0; i < len; i++) {
if(buf[i] == '\n') {
CPPLOG(INFO) << "tohost send '" << io_buf.str() << "'";
io_buf.str("");
} else } else
io_buf << buf[i]; uart_buf << c;
} break;
default:
break;
} }
// Not sure what the correct return value should be tohost_lower_written = false;
uint8_t ret_val = 1; } else if(tohost_lower)
write(address_type::PHYSICAL, access_type::WRITE, traits<BASE>::MEM, fromhost, 1, &ret_val); tohost_lower_written = true;
} else { } else if((traits<BASE>::XLEN == 32 && paddr.val == fromhost + 4) || (traits<BASE>::XLEN == 64 && paddr.val == fromhost)) {
CPPLOG(ERR) << "tohost syscall with number " << std::hex << syscall_num << std::dec << " (" << syscall_num uint64_t fhostvar = *reinterpret_cast<uint64_t*>(p.data() + (fromhost & mem.page_addr_mask));
<< ") not implemented"; *reinterpret_cast<uint64_t*>(p.data() + (tohost & mem.page_addr_mask)) = fhostvar;
this->reg.trap_state = std::numeric_limits<uint32_t>::max();
this->interrupt_sim = payload;
return iss::Ok;
}
} else {
CPPLOG(ERR) << "tohost functionality not implemented for device " << device << " and command " << command;
this->reg.trap_state = std::numeric_limits<uint32_t>::max();
this->interrupt_sim = payload;
return iss::Ok;
} }
} }
if((traits<BASE>::XLEN == 32 && paddr.val == fromhost + 4) || (traits<BASE>::XLEN == 64 && paddr.val == fromhost)) { }
uint64_t fhostvar = *reinterpret_cast<uint64_t*>(p.data() + (fromhost & mem.page_addr_mask));
*reinterpret_cast<uint64_t*>(p.data() + (tohost & mem.page_addr_mask)) = fhostvar;
}
} }
return iss::Ok; return iss::Ok;
} }

132
src/iss/arch/riscv_hart_mu_p.h
View File

@ -380,7 +380,7 @@ protected:
using csr_page_type = typename csr_type::page_type; using csr_page_type = typename csr_type::page_type;
mem_type mem; mem_type mem;
csr_type csr; csr_type csr;
std::stringstream io_buf; std::stringstream uart_buf;
std::unordered_map<reg_t, uint64_t> ptw; std::unordered_map<reg_t, uint64_t> ptw;
std::unordered_map<uint64_t, uint8_t> atomic_reservation; std::unordered_map<uint64_t, uint8_t> atomic_reservation;
std::unordered_map<unsigned, rd_csr_f> csr_rd_cb; std::unordered_map<unsigned, rd_csr_f> csr_rd_cb;
@ -475,7 +475,7 @@ riscv_hart_mu_p<BASE, FEAT, LOGCAT>::riscv_hart_mu_p(feature_config cfg)
csr[marchid] = traits<BASE>::MARCHID_VAL; csr[marchid] = traits<BASE>::MARCHID_VAL;
csr[mimpid] = 1; csr[mimpid] = 1;
io_buf.str(""); uart_buf.str("");
if(traits<BASE>::FLEN > 0) { if(traits<BASE>::FLEN > 0) {
csr_rd_cb[fcsr] = &this_class::read_fcsr; csr_rd_cb[fcsr] = &this_class::read_fcsr;
csr_wr_cb[fcsr] = &this_class::write_fcsr; csr_wr_cb[fcsr] = &this_class::write_fcsr;
@ -938,10 +938,10 @@ iss::status riscv_hart_mu_p<BASE, FEAT, LOGCAT>::write(const address_type type,
switch(addr) { switch(addr) {
case 0x10013000: // UART0 base, TXFIFO reg case 0x10013000: // UART0 base, TXFIFO reg
case 0x10023000: // UART1 base, TXFIFO reg case 0x10023000: // UART1 base, TXFIFO reg
io_buf << (char)data[0]; uart_buf << (char)data[0];
if(((char)data[0]) == '\n' || data[0] == 0) { if(((char)data[0]) == '\n' || data[0] == 0) {
std::cout << io_buf.str(); std::cout << uart_buf.str();
io_buf.str(""); uart_buf.str("");
} }
return iss::Ok; return iss::Ok;
case 0x10008000: { // HFROSC base, hfrosccfg reg case 0x10008000: { // HFROSC base, hfrosccfg reg
@ -1312,81 +1312,65 @@ iss::status riscv_hart_mu_p<BASE, FEAT, LOGCAT>::read_mem(phys_addr_t paddr, uns
} }
return iss::Ok; return iss::Ok;
} }
template <typename BASE, features_e FEAT, typename LOGCAT> template <typename BASE, features_e FEAT, typename LOGCAT>
iss::status riscv_hart_mu_p<BASE, FEAT, LOGCAT>::write_mem(phys_addr_t paddr, unsigned length, const uint8_t* const data) { iss::status riscv_hart_mu_p<BASE, FEAT, LOGCAT>::write_mem(phys_addr_t paddr, unsigned length, const uint8_t* const data) {
mem_type::page_type& p = mem(paddr.val / mem.page_size); switch(paddr.val) {
std::copy(data, data + length, p.data() + (paddr.val & mem.page_addr_mask)); // TODO remove UART, Peripherals should not be part of the ISS
// tohost handling in case of riscv-test case 0xFFFF0000: // UART0 base, TXFIFO reg
// according to https://github.com/riscv-software-src/riscv-isa-sim/issues/364#issuecomment-607657754: if(((char)data[0]) == '\n' || data[0] == 0) {
if(paddr.access && iss::access_type::FUNC) { CPPLOG(INFO) << "UART" << ((paddr.val >> 12) & 0x3) << " send '" << uart_buf.str() << "'";
if(paddr.val == tohost) { uart_buf.str("");
if(traits<BASE>::XLEN == 32) } else if(((char)data[0]) != '\r')
tohost &= 0x00000000ffffffff; uart_buf << (char)data[0];
// Extract Device (bits 63:56) break;
uint8_t device = (tohost >> 56) & 0xFF; default: {
// Extract Command (bits 55:48) mem_type::page_type& p = mem(paddr.val / mem.page_size);
uint8_t command = (tohost >> 48) & 0xFF; std::copy(data, data + length, p.data() + (paddr.val & mem.page_addr_mask));
// Extract payload (bits 47:0) // tohost handling in case of riscv-test
uint64_t payload = tohost & 0xFFFFFFFFFFFFULL; if(paddr.access && iss::access_type::FUNC) {
if(payload & 1) { auto tohost_upper =
CPPLOG(FATAL) << "tohost value is 0x" << std::hex << payload << std::dec << " (" << payload << "), stopping simulation"; (traits<BASE>::XLEN == 32 && paddr.val == (tohost + 4)) || (traits<BASE>::XLEN == 64 && paddr.val == tohost);
this->reg.trap_state = std::numeric_limits<uint32_t>::max(); auto tohost_lower = (traits<BASE>::XLEN == 32 && paddr.val == tohost) || (traits<BASE>::XLEN == 64 && paddr.val == tohost);
this->interrupt_sim = payload; if(tohost_lower || tohost_upper) {
return iss::Ok; uint64_t hostvar = *reinterpret_cast<uint64_t*>(p.data() + (tohost & mem.page_addr_mask));
} else if(device == 0 && command == 0) { // in case of 32 bit system, two writes to tohost are needed, only evaluate on the second (high) write
reg_t payload_addr; if(tohost_upper && (tohost_lower || tohost_lower_written)) {
// payload contains the addr of the struct containing information about the syscall switch(hostvar >> 48) {
read(address_type::PHYSICAL, access_type::READ, traits<BASE>::MEM, payload, sizeof(reg_t), case 0:
reinterpret_cast<uint8_t*>(&payload_addr)); if(hostvar != 0x1) {
// If the payload_addr is missaligned end simulation CPPLOG(FATAL) << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar
if(payload_addr & 1) { << "), stopping simulation";
CPPLOG(FATAL) << "tohost payload value is 0x" << std::hex << payload_addr << std::dec << " (" << payload_addr } else {
<< "), stopping simulation"; CPPLOG(INFO) << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar
this->reg.trap_state = std::numeric_limits<uint32_t>::max(); << "), stopping simulation";
this->interrupt_sim = payload; }
return iss::Ok; this->reg.trap_state = std::numeric_limits<uint32_t>::max();
} this->interrupt_sim = hostvar;
// read the entire struct into an array #ifndef WITH_TCC
reg_t loaded_payload[8]; throw(iss::simulation_stopped(hostvar));
read(address_type::PHYSICAL, access_type::READ, traits<BASE>::MEM, payload_addr, sizeof(loaded_payload), #endif
reinterpret_cast<uint8_t*>(loaded_payload)); break;
reg_t syscall_num = loaded_payload[0]; case 0x0101: {
if(syscall_num == 64) { // SYS_WRITE char c = static_cast<char>(hostvar & 0xff);
reg_t fd = loaded_payload[1]; if(c == '\n' || c == 0) {
reg_t buf_ptr = loaded_payload[2]; CPPLOG(INFO) << "tohost send '" << uart_buf.str() << "'";
reg_t len = loaded_payload[3]; uart_buf.str("");
std::vector<char> buf(len);
read(address_type::PHYSICAL, access_type::READ, traits<BASE>::MEM, buf_ptr, len,
reinterpret_cast<uint8_t*>(buf.data()));
// we disregard the fd and just log to stdout
for(size_t i = 0; i < len; i++) {
if(buf[i] == '\n') {
CPPLOG(INFO) << "tohost send '" << io_buf.str() << "'";
io_buf.str("");
} else } else
io_buf << buf[i]; uart_buf << c;
} break;
default:
break;
} }
// Not sure what the correct return value should be tohost_lower_written = false;
uint8_t ret_val = 1; } else if(tohost_lower)
write(address_type::PHYSICAL, access_type::WRITE, traits<BASE>::MEM, fromhost, 1, &ret_val); tohost_lower_written = true;
} else { } else if((traits<BASE>::XLEN == 32 && paddr.val == fromhost + 4) || (traits<BASE>::XLEN == 64 && paddr.val == fromhost)) {
CPPLOG(ERR) << "tohost syscall with number " << std::hex << syscall_num << std::dec << " (" << syscall_num uint64_t fhostvar = *reinterpret_cast<uint64_t*>(p.data() + (fromhost & mem.page_addr_mask));
<< ") not implemented"; *reinterpret_cast<uint64_t*>(p.data() + (tohost & mem.page_addr_mask)) = fhostvar;
this->reg.trap_state = std::numeric_limits<uint32_t>::max();
this->interrupt_sim = payload;
return iss::Ok;
}
} else {
CPPLOG(ERR) << "tohost functionality not implemented for device " << device << " and command " << command;
this->reg.trap_state = std::numeric_limits<uint32_t>::max();
this->interrupt_sim = payload;
return iss::Ok;
} }
} }
if((traits<BASE>::XLEN == 32 && paddr.val == fromhost + 4) || (traits<BASE>::XLEN == 64 && paddr.val == fromhost)) { }
uint64_t fhostvar = *reinterpret_cast<uint64_t*>(p.data() + (fromhost & mem.page_addr_mask));
*reinterpret_cast<uint64_t*>(p.data() + (tohost & mem.page_addr_mask)) = fhostvar;
}
} }
return iss::Ok; return iss::Ok;
} }