DBT-RISE/DBT-RISE-TGC
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base: DBT-RISE:72b11beac51606ed547000cfce962d1c12fe30cf
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DBT-RISE:main DBT-RISE:develop DBT-RISE:featture/interp_instr_cache DBT-RISE:feature/privilege_refactor DBT-RISE:feature/htif DBT-RISE:feature/eve_checkin DBT-RISE:feature/iss_factory DBT-RISE:feature/core_factory DBT-RISE:Trace_enhancement DBT-RISE:feature/reduced_output DBT-RISE:msvc_compat DBT-RISE:hotfix/latest_scc DBT-RISE:feature/interpreter
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compare: DBT-RISE:d2efb23ff74a3b68de1228653c28cb05c4eaebc1
Branches Tags
DBT-RISE:develop DBT-RISE:featture/interp_instr_cache DBT-RISE:feature/privilege_refactor DBT-RISE:feature/htif DBT-RISE:feature/eve_checkin DBT-RISE:main DBT-RISE:feature/iss_factory DBT-RISE:feature/core_factory DBT-RISE:Trace_enhancement DBT-RISE:feature/reduced_output DBT-RISE:msvc_compat DBT-RISE:hotfix/latest_scc DBT-RISE:feature/interpreter

2 Commits
72b11beac5 ... d2efb23ff7

Author SHA1 Message Date
Eyck Jentzsch
d2efb23ff7 fixes cache behavior for fetches 2024-07-25 19:33:50 +02:00
Eyck-Alexander Jentzsch
04b7a09b19 updates date in templates 2024-07-25 17:25:12 +02:00
4 changed files with 4 additions and 4 deletions
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2
gen_input/templates/CORENAME.cpp.gtl
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@ -1,5 +1,5 @@
/******************************************************************************* /*******************************************************************************
* Copyright (C) 2017 - 2020 MINRES Technologies GmbH * Copyright (C) 2024 MINRES Technologies GmbH
* All rights reserved. * All rights reserved.
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without

2
gen_input/templates/CORENAME.h.gtl
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@ -1,5 +1,5 @@
/******************************************************************************* /*******************************************************************************
* Copyright (C) 2017 - 2021 MINRES Technologies GmbH * Copyright (C) 2024 MINRES Technologies GmbH
* All rights reserved. * All rights reserved.
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without

2
gen_input/templates/CORENAME_sysc.cpp.gtl
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@ -1,5 +1,5 @@
/******************************************************************************* /*******************************************************************************
* Copyright (C) 2023 MINRES Technologies GmbH * Copyright (C) 2024 MINRES Technologies GmbH
* All rights reserved. * All rights reserved.
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without

2
src/iss/arch/wt_cache.h
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@ -119,7 +119,7 @@ template <typename BASE> iss::status iss::arch::wt_cache<BASE>::read_cache(phys_
icache_ptr.reset(new cache::cache(size, line_sz, ways)); icache_ptr.reset(new cache::cache(size, line_sz, ways));
dcache_ptr.reset(new cache::cache(size, line_sz, ways)); dcache_ptr.reset(new cache::cache(size, line_sz, ways));
} }
if((a.val & io_addr_mask) != io_address) { if((a.access & iss::access_type::FETCH)== iss::access_type::FETCH || (a.val & io_addr_mask) != io_address) {
auto set_addr = (a.val & (size - 1)) >> util::ilog2(line_sz * ways); auto set_addr = (a.val & (size - 1)) >> util::ilog2(line_sz * ways);
auto tag_addr = a.val >> util::ilog2(line_sz); auto tag_addr = a.val >> util::ilog2(line_sz);
auto& set = (is_fetch(a.access) ? icache_ptr : dcache_ptr)->sets[set_addr]; auto& set = (is_fetch(a.access) ? icache_ptr : dcache_ptr)->sets[set_addr];