fixes CSR to match latest fast interrupts spec

src/iss/arch/riscv_hart_common.h

@@ -115,10 +115,9 @@ enum riscv_csr {
     mip = 0x344,
     mxnti = 0x345, //CLIC
     mintstatus   = 0x346, // MRW Current interrupt levels (CLIC) - addr subject to change
+    mintthresh   = 0x347, // MRW Interrupt-level threshold (CLIC) - addr subject to change
     mscratchcsw  = 0x348, // MRW Conditional scratch swap on priv mode change (CLIC)
     mscratchcswl = 0x349, // MRW Conditional scratch swap on level change (CLIC)
-    mintthresh   = 0x350, // MRW Interrupt-level threshold (CLIC) - addr subject to change
-    mclicbase    = 0x351, // MRW Base address for CLIC memory mapped registers (CLIC) - addr subject to change
     // Physical Memory Protection
     pmpcfg0 = 0x3A0,
     pmpcfg1 = 0x3A1,

src/iss/arch/riscv_hart_m_p.h

@@ -351,7 +351,6 @@ riscv_hart_m_p<BASE, FEAT>::riscv_hart_m_p(feature_config cfg)
     csr[mvendorid] = 0x669;
     csr[marchid] = traits<BASE>::MARCHID_VAL;
     csr[mimpid] = 1;
-    csr[mclicbase] = cfg.clic_base; // TODO: should be taken from YAML file
 
     uart_buf.str("");
     for (unsigned addr = mhpmcounter3; addr <= mhpmcounter31; ++addr){
@@ -425,8 +424,6 @@ riscv_hart_m_p<BASE, FEAT>::riscv_hart_m_p(feature_config cfg)
         csr_wr_cb[mscratchcswl] = &this_class::write_csr_reg;
         csr_rd_cb[mintthresh] = &this_class::read_csr_reg;
         csr_wr_cb[mintthresh] = &this_class::write_intthresh;
-        csr_rd_cb[mclicbase] = &this_class::read_csr_reg;
-        csr_wr_cb[mclicbase] = &this_class::write_null;
 
         clic_int_reg.resize(cfg.clic_num_irq,  clic_int_reg_t{.raw=0});
         clic_cfg_reg=0x20;

src/iss/arch/riscv_hart_mu_p.h

@@ -369,7 +369,6 @@ riscv_hart_mu_p<BASE, FEAT>::riscv_hart_mu_p(feature_config cfg)
     csr[mvendorid] = 0x669;
     csr[marchid] = traits<BASE>::MARCHID_VAL;
     csr[mimpid] = 1;
-    csr[mclicbase] = cfg.clic_base; // TODO: should be taken from YAML file
 
     uart_buf.str("");
     for (unsigned addr = mhpmcounter3; addr <= mhpmcounter31; ++addr){
@@ -472,8 +471,6 @@ riscv_hart_mu_p<BASE, FEAT>::riscv_hart_mu_p(feature_config cfg)
         csr_wr_cb[mscratchcswl] = &this_class::write_csr_reg;
         csr_rd_cb[mintthresh] = &this_class::read_csr_reg;
         csr_wr_cb[mintthresh] = &this_class::write_intthresh;
-        csr_rd_cb[mclicbase] = &this_class::read_csr_reg;
-        csr_wr_cb[mclicbase] = &this_class::write_null;
 
         clic_int_reg.resize(cfg.clic_num_irq,  clic_int_reg_t{.raw=0});
         clic_cfg_reg=0x20;