adaptes to changes in dbt-rise-core

gen_input/templates/interp/CORENAME.cpp.gtl

@@ -36,11 +36,10 @@ def nativeTypeSize(int size){
     if(size<=8) return 8; else if(size<=16) return 16; else if(size<=32) return 32; else return 64;
 }
 %>
-#include <vm/fp_functions.h>
-#include <iss/arch/${coreDef.name.toLowerCase()}.h>
-#include <iss/arch/riscv_hart_m_p.h>
 #include <iss/debugger/gdb_session.h>
 #include <iss/debugger/server.h>
+#include <iss/arch/${coreDef.name.toLowerCase()}.h>
+#include <iss/arch/riscv_hart_m_p.h>
 #include <iss/iss.h>
 #include <iss/interp/vm_base.h>
 #include <util/logging.h>

src/iss/arch/riscv_hart_m_p.h

@@ -477,10 +477,10 @@ template <typename BASE, features_e FEAT> std::pair<uint64_t, bool> riscv_hart_m
     if (fp) {
         std::array<char, 5> buf;
         auto n = fread(buf.data(), 1, 4, fp);
+        fclose(fp);
         if (n != 4) throw std::runtime_error("input file has insufficient size");
         buf[4] = 0;
         if (strcmp(buf.data() + 1, "ELF") == 0) {
-            fclose(fp);
             // Create elfio reader
             ELFIO::elfio reader;
             // Load ELF data
@@ -571,12 +571,12 @@ iss::status riscv_hart_m_p<BASE, FEAT>::read(const address_type type, const acce
             if (unlikely(is_fetch(access) && (addr&(alignment-1)))) {
                 fault_data = addr;
                 if (is_debug(access)) throw trap_access(0, addr);
-                this->trap_state = (1 << 31); // issue trap 0
+                this->trap_state = (1UL << 31); // issue trap 0
                 return iss::Err;
             }
             try {
                 if(!is_debug(access) && (addr&(alignment-1))){
-                    this->trap_state = 1<<31 | 4<<16;
+                    this->trap_state = (1UL << 31) | 4<<16;
                     fault_data=addr;
                     return iss::Err;
                 }
@@ -595,12 +595,12 @@ iss::status riscv_hart_m_p<BASE, FEAT>::read(const address_type type, const acce
                     res = read_mem( phys_addr, length, data);
                 }
                 if (unlikely(res != iss::Ok)){
-                    this->trap_state = (1 << 31) | (5 << 16); // issue trap 5 (load access fault
+                    this->trap_state = (1UL << 31) | (5 << 16); // issue trap 5 (load access fault
                     fault_data=addr;
                 }
                 return res;
             } catch (trap_access &ta) {
-                this->trap_state = (1 << 31) | ta.id;
+                this->trap_state = (1UL << 31) | ta.id;
                 fault_data=ta.addr;
                 return iss::Err;
             }
@@ -626,7 +626,7 @@ iss::status riscv_hart_m_p<BASE, FEAT>::read(const address_type type, const acce
         }
         return iss::Ok;
     } catch (trap_access &ta) {
-        this->trap_state = (1 << 31) | ta.id;
+        this->trap_state = (1UL << 31) | ta.id;
         fault_data=ta.addr;
         return iss::Err;
     }
@@ -664,12 +664,12 @@ iss::status riscv_hart_m_p<BASE, FEAT>::write(const address_type type, const acc
             if (unlikely((access && iss::access_type::FETCH) && (addr & 0x1) == 1)) {
                 fault_data = addr;
                 if (access && iss::access_type::DEBUG) throw trap_access(0, addr);
-                this->trap_state = (1 << 31); // issue trap 0
+                this->trap_state = (1UL << 31); // issue trap 0
                 return iss::Err;
             }
             try {
                 if(length>1 && (addr&(length-1)) && (access&access_type::DEBUG) != access_type::DEBUG){
-                    this->trap_state = 1<<31 | 6<<16;
+                    this->trap_state = (1UL << 31) | 6<<16;
                     fault_data=addr;
                     return iss::Err;
                 }
@@ -688,12 +688,12 @@ iss::status riscv_hart_m_p<BASE, FEAT>::write(const address_type type, const acc
                     res = write_mem( phys_addr, length, data);
                 }
                 if (unlikely(res != iss::Ok)) {
-                    this->trap_state = (1 << 31) | (7 << 16); // issue trap 7 (Store/AMO access fault)
+                    this->trap_state = (1UL << 31) | (7 << 16); // issue trap 7 (Store/AMO access fault)
                     fault_data=addr;
                 }
                 return res;
             } catch (trap_access &ta) {
-                this->trap_state = (1 << 31) | ta.id;
+                this->trap_state = (1UL << 31) | ta.id;
                 fault_data=ta.addr;
                 return iss::Err;
             }
@@ -753,7 +753,7 @@ iss::status riscv_hart_m_p<BASE, FEAT>::write(const address_type type, const acc
         }
         return iss::Ok;
     } catch (trap_access &ta) {
-        this->trap_state = (1 << 31) | ta.id;
+        this->trap_state = (1UL << 31) | ta.id;
         fault_data=ta.addr;
         return iss::Err;
     }

src/iss/arch/riscv_hart_mu_p.h

@@ -526,10 +526,10 @@ template <typename BASE, features_e FEAT> std::pair<uint64_t, bool> riscv_hart_m
     if (fp) {
         std::array<char, 5> buf;
         auto n = fread(buf.data(), 1, 4, fp);
+        fclose(fp);
         if (n != 4) throw std::runtime_error("input file has insufficient size");
         buf[4] = 0;
         if (strcmp(buf.data() + 1, "ELF") == 0) {
-            fclose(fp);
             // Create elfio reader
             ELFIO::elfio reader;
             // Load ELF data
@@ -708,7 +708,7 @@ iss::status riscv_hart_mu_p<BASE, FEAT>::read(const address_type type, const acc
                 if(!pmp_check(access, addr, length) && !is_debug(access)) {
                     fault_data = addr;
                     if (is_debug(access)) throw trap_access(0, addr);
-                    this->trap_state = (1 << 31) | ((access==access_type::FETCH?1:5) << 16); // issue trap 1
+                    this->trap_state = (1UL << 31) | ((access==access_type::FETCH?1:5) << 16); // issue trap 1
                     return iss::Err;
                 }
             }
@@ -716,12 +716,12 @@ iss::status riscv_hart_mu_p<BASE, FEAT>::read(const address_type type, const acc
             if (unlikely(is_fetch(access) && (addr&(alignment-1)))) {
                 fault_data = addr;
                 if (is_debug(access)) throw trap_access(0, addr);
-                this->trap_state = (1 << 31); // issue trap 0
+                this->trap_state = (1UL << 31); // issue trap 0
                 return iss::Err;
             }
             try {
                 if(!is_debug(access)  && (addr&(alignment-1))){
-                    this->trap_state = 1<<31 | 4<<16;
+                    this->trap_state = (1UL << 31) | 4<<16;
                     fault_data=addr;
                     return iss::Err;
                 }
@@ -740,12 +740,12 @@ iss::status riscv_hart_mu_p<BASE, FEAT>::read(const address_type type, const acc
                     res = read_mem( phys_addr, length, data);
                 }
                 if (unlikely(res != iss::Ok)){
-                    this->trap_state = (1 << 31) | (5 << 16); // issue trap 5 (load access fault
+                    this->trap_state = (1UL << 31) | (5 << 16); // issue trap 5 (load access fault
                     fault_data=addr;
                 }
                 return res;
             } catch (trap_access &ta) {
-                this->trap_state = (1 << 31) | ta.id;
+                this->trap_state = (1UL << 31) | ta.id;
                 fault_data=ta.addr;
                 return iss::Err;
             }
@@ -771,7 +771,7 @@ iss::status riscv_hart_mu_p<BASE, FEAT>::read(const address_type type, const acc
         }
         return iss::Ok;
     } catch (trap_access &ta) {
-        this->trap_state = (1 << 31) | ta.id;
+        this->trap_state = (1UL << 31) | ta.id;
         fault_data=ta.addr;
         return iss::Err;
     }
@@ -810,19 +810,19 @@ iss::status riscv_hart_mu_p<BASE, FEAT>::write(const address_type type, const ac
                 if(!pmp_check(access, addr, length) && (access&access_type::DEBUG) != access_type::DEBUG) {
                     fault_data = addr;
                     if (access && iss::access_type::DEBUG) throw trap_access(0, addr);
-                    this->trap_state = (1 << 31) | (7 << 16); // issue trap 1
+                    this->trap_state = (1UL << 31) | (7 << 16); // issue trap 1
                     return iss::Err;
                 }
             }
             if (unlikely((access && iss::access_type::FETCH) && (addr & 0x1) == 1)) {
                 fault_data = addr;
                 if (access && iss::access_type::DEBUG) throw trap_access(0, addr);
-                this->trap_state = (1 << 31); // issue trap 0
+                this->trap_state = (1UL << 31); // issue trap 0
                 return iss::Err;
             }
             try {
                 if(length>1 && (addr&(length-1)) && (access&access_type::DEBUG) != access_type::DEBUG){
-                    this->trap_state = 1<<31 | 6<<16;
+                    this->trap_state = (1UL << 31) | 6<<16;
                     fault_data=addr;
                     return iss::Err;
                 }
@@ -841,12 +841,12 @@ iss::status riscv_hart_mu_p<BASE, FEAT>::write(const address_type type, const ac
                     res = write_mem( phys_addr, length, data);
                 }
                 if (unlikely(res != iss::Ok)) {
-                    this->trap_state = (1 << 31) | (7 << 16); // issue trap 7 (Store/AMO access fault)
+                    this->trap_state = (1UL << 31) | (7 << 16); // issue trap 7 (Store/AMO access fault)
                     fault_data=addr;
                 }
                 return res;
             } catch (trap_access &ta) {
-                this->trap_state = (1 << 31) | ta.id;
+                this->trap_state = (1UL << 31) | ta.id;
                 fault_data=ta.addr;
                 return iss::Err;
             }
@@ -906,7 +906,7 @@ iss::status riscv_hart_mu_p<BASE, FEAT>::write(const address_type type, const ac
         }
         return iss::Ok;
     } catch (trap_access &ta) {
-        this->trap_state = (1 << 31) | ta.id;
+        this->trap_state = (1UL << 31) | ta.id;
         fault_data=ta.addr;
         return iss::Err;
     }

src/iss/debugger/riscv_target_adapter.h

@@ -85,7 +85,7 @@ public:
      corresponding bytes in avail_buf are 0, otherwise
      avail buf is 1 */
     status read_single_register(unsigned int reg_no, std::vector<uint8_t> &buf,
-                                std::vector<uint8_t> &avail_buf) override;
+            std::vector<uint8_t> &avail_buf) override;
 
     /* Write one register. buf is 4-byte aligned and it is in target byte
      order */
@@ -104,7 +104,7 @@ public:
     status process_query(unsigned int &mask, const rp_thread_ref &arg, rp_thread_info &info) override;
 
     status thread_list_query(int first, const rp_thread_ref &arg, std::vector<rp_thread_ref> &result, size_t max_num,
-                             size_t &num, bool &done) override;
+            size_t &num, bool &done) override;
 
     status current_thread_query(rp_thread_ref &thread) override;
 
@@ -120,12 +120,12 @@ public:
 
     status packetsize_query(std::string &out_buf) override;
 
-    status add_break(int type, uint64_t addr, unsigned int length) override;
+    status add_break(break_type type, uint64_t addr, unsigned int length) override;
 
-    status remove_break(int type, uint64_t addr, unsigned int length) override;
+    status remove_break(break_type type, uint64_t addr, unsigned int length) override;
 
     status resume_from_addr(bool step, int sig, uint64_t addr, rp_thread_ref thread,
-                            std::function<void(unsigned)> stop_callback) override;
+            std::function<void(unsigned)> stop_callback) override;
 
     status target_xml_query(std::string &out_buf) override;
 
@@ -159,8 +159,8 @@ template <typename ARCH> status riscv_target_adapter<ARCH>::is_thread_alive(rp_t
  */
 template <typename ARCH>
 status riscv_target_adapter<ARCH>::thread_list_query(int first, const rp_thread_ref &arg,
-                                                     std::vector<rp_thread_ref> &result, size_t max_num, size_t &num,
-                                                     bool &done) {
+        std::vector<rp_thread_ref> &result, size_t max_num, size_t &num,
+        bool &done) {
     if (first == 0) {
         result.clear();
         result.push_back(thread_idx);
@@ -193,20 +193,20 @@ status riscv_target_adapter<ARCH>::read_registers(std::vector<uint8_t> &data, st
         }
     }
     // work around fill with F type registers
-//    if (arch::traits<ARCH>::NUM_REGS < 65) {
-//        auto reg_width = sizeof(typename arch::traits<ARCH>::reg_t);
-//        for (size_t reg_no = 0; reg_no < 33; ++reg_no) {
-//            for (size_t j = 0; j < reg_width; ++j) {
-//                data.push_back(0x0);
-//                avail.push_back(0x00);
-//            }
-//            // if(arch::traits<ARCH>::XLEN < 64)
-//            //     for(unsigned j=0; j<4; ++j){
-//            //         data.push_back(0x0);
-//            //         avail.push_back(0x00);
-//            //     }
-//        }
-//    }
+    //    if (arch::traits<ARCH>::NUM_REGS < 65) {
+    //        auto reg_width = sizeof(typename arch::traits<ARCH>::reg_t);
+    //        for (size_t reg_no = 0; reg_no < 33; ++reg_no) {
+    //            for (size_t j = 0; j < reg_width; ++j) {
+    //                data.push_back(0x0);
+    //                avail.push_back(0x00);
+    //            }
+    //            // if(arch::traits<ARCH>::XLEN < 64)
+    //            //     for(unsigned j=0; j<4; ++j){
+    //            //         data.push_back(0x0);
+    //            //         avail.push_back(0x00);
+    //            //     }
+    //        }
+    //    }
     return Ok;
 }
 
@@ -240,7 +240,7 @@ template <typename ARCH> status riscv_target_adapter<ARCH>::write_registers(cons
 
 template <typename ARCH>
 status riscv_target_adapter<ARCH>::read_single_register(unsigned int reg_no, std::vector<uint8_t> &data,
-                                                        std::vector<uint8_t> &avail) {
+        std::vector<uint8_t> &avail) {
     if (reg_no < 65) {
         // auto reg_size = arch::traits<ARCH>::reg_bit_width(static_cast<typename
         // arch::traits<ARCH>::reg_e>(reg_no))/8;
@@ -331,34 +331,46 @@ template <typename ARCH> status riscv_target_adapter<ARCH>::packetsize_query(std
     return Ok;
 }
 
-template <typename ARCH> status riscv_target_adapter<ARCH>::add_break(int type, uint64_t addr, unsigned int length) {
-    auto saddr = map_addr({iss::access_type::FETCH, iss::address_type::PHYSICAL, 0, addr});
-    auto eaddr = map_addr({iss::access_type::FETCH, iss::address_type::PHYSICAL, 0, addr + length});
-    target_adapter_base::bp_lut.addEntry(++target_adapter_base::bp_count, saddr.val, eaddr.val - saddr.val);
-    LOG(TRACE) << "Adding breakpoint with handle " << target_adapter_base::bp_count << " for addr 0x" << std::hex
-               << saddr.val << std::dec;
-    LOG(TRACE) << "Now having " << target_adapter_base::bp_lut.size() << " breakpoints";
-    return Ok;
-}
-
-template <typename ARCH> status riscv_target_adapter<ARCH>::remove_break(int type, uint64_t addr, unsigned int length) {
-    auto saddr = map_addr({iss::access_type::FETCH, iss::address_type::PHYSICAL, 0, addr});
-    unsigned handle = target_adapter_base::bp_lut.getEntry(saddr.val);
-    if (handle) {
-        LOG(TRACE) << "Removing breakpoint with handle " << handle << " for addr 0x" << std::hex << saddr.val
-                   << std::dec;
-        // TODO: check length of addr range
-        target_adapter_base::bp_lut.removeEntry(handle);
+template <typename ARCH> status riscv_target_adapter<ARCH>::add_break(break_type type, uint64_t addr, unsigned int length) {
+    switch(type) {
+    default:
+        return Err;
+    case HW_EXEC: {
+        auto saddr = map_addr({iss::access_type::FETCH, iss::address_type::PHYSICAL, 0, addr});
+        auto eaddr = map_addr({iss::access_type::FETCH, iss::address_type::PHYSICAL, 0, addr + length});
+        target_adapter_base::bp_lut.addEntry(++target_adapter_base::bp_count, saddr.val, eaddr.val - saddr.val);
+        LOG(TRACE) << "Adding breakpoint with handle " << target_adapter_base::bp_count << " for addr 0x" << std::hex
+                << saddr.val << std::dec;
         LOG(TRACE) << "Now having " << target_adapter_base::bp_lut.size() << " breakpoints";
         return Ok;
     }
-    LOG(TRACE) << "Now having " << target_adapter_base::bp_lut.size() << " breakpoints";
-    return Err;
+    }
+}
+
+template <typename ARCH> status riscv_target_adapter<ARCH>::remove_break(break_type type, uint64_t addr, unsigned int length) {
+    switch(type) {
+    default:
+        return Err;
+    case HW_EXEC: {
+        auto saddr = map_addr({iss::access_type::FETCH, iss::address_type::PHYSICAL, 0, addr});
+        unsigned handle = target_adapter_base::bp_lut.getEntry(saddr.val);
+        if (handle) {
+            LOG(TRACE) << "Removing breakpoint with handle " << handle << " for addr 0x" << std::hex << saddr.val
+                    << std::dec;
+            // TODO: check length of addr range
+            target_adapter_base::bp_lut.removeEntry(handle);
+            LOG(TRACE) << "Now having " << target_adapter_base::bp_lut.size() << " breakpoints";
+            return Ok;
+        }
+        LOG(TRACE) << "Now having " << target_adapter_base::bp_lut.size() << " breakpoints";
+        return Err;
+    }
+    }
 }
 
 template <typename ARCH>
 status riscv_target_adapter<ARCH>::resume_from_addr(bool step, int sig, uint64_t addr, rp_thread_ref thread,
-                                                    std::function<void(unsigned)> stop_callback) {
+        std::function<void(unsigned)> stop_callback) {
     auto *reg_base = core->get_regs_base_ptr();
     auto reg_width = arch::traits<ARCH>::reg_bit_widths[arch::traits<ARCH>::PC] / 8;
     auto offset = traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC];
@@ -369,42 +381,42 @@ status riscv_target_adapter<ARCH>::resume_from_addr(bool step, int sig, uint64_t
 
 template <typename ARCH> status riscv_target_adapter<ARCH>::target_xml_query(std::string &out_buf) {
     const std::string res{"<?xml version=\"1.0\"?><!DOCTYPE target SYSTEM \"gdb-target.dtd\">"
-                          "<target><architecture>riscv:rv32</architecture>"
-                          //"  <feature name=\"org.gnu.gdb.riscv.rv32i\">\n"
-                          //"    <reg name=\"x0\"  bitsize=\"32\" group=\"general\"/>\n"
-                          //"    <reg name=\"x1\"  bitsize=\"32\" group=\"general\"/>\n"
-                          //"    <reg name=\"x2\"  bitsize=\"32\" group=\"general\"/>\n"
-                          //"    <reg name=\"x3\"  bitsize=\"32\" group=\"general\"/>\n"
-                          //"    <reg name=\"x4\"  bitsize=\"32\" group=\"general\"/>\n"
-                          //"    <reg name=\"x5\"  bitsize=\"32\" group=\"general\"/>\n"
-                          //"    <reg name=\"x6\"  bitsize=\"32\" group=\"general\"/>\n"
-                          //"    <reg name=\"x7\"  bitsize=\"32\" group=\"general\"/>\n"
-                          //"    <reg name=\"x8\"  bitsize=\"32\" group=\"general\"/>\n"
-                          //"    <reg name=\"x9\"  bitsize=\"32\" group=\"general\"/>\n"
-                          //"    <reg name=\"x10\" bitsize=\"32\" group=\"general\"/>\n"
-                          //"    <reg name=\"x11\" bitsize=\"32\" group=\"general\"/>\n"
-                          //"    <reg name=\"x12\" bitsize=\"32\" group=\"general\"/>\n"
-                          //"    <reg name=\"x13\" bitsize=\"32\" group=\"general\"/>\n"
-                          //"    <reg name=\"x14\" bitsize=\"32\" group=\"general\"/>\n"
-                          //"    <reg name=\"x15\" bitsize=\"32\" group=\"general\"/>\n"
-                          //"    <reg name=\"x16\" bitsize=\"32\" group=\"general\"/>\n"
-                          //"    <reg name=\"x17\" bitsize=\"32\" group=\"general\"/>\n"
-                          //"    <reg name=\"x18\" bitsize=\"32\" group=\"general\"/>\n"
-                          //"    <reg name=\"x19\" bitsize=\"32\" group=\"general\"/>\n"
-                          //"    <reg name=\"x20\" bitsize=\"32\" group=\"general\"/>\n"
-                          //"    <reg name=\"x21\" bitsize=\"32\" group=\"general\"/>\n"
-                          //"    <reg name=\"x22\" bitsize=\"32\" group=\"general\"/>\n"
-                          //"    <reg name=\"x23\" bitsize=\"32\" group=\"general\"/>\n"
-                          //"    <reg name=\"x24\" bitsize=\"32\" group=\"general\"/>\n"
-                          //"    <reg name=\"x25\" bitsize=\"32\" group=\"general\"/>\n"
-                          //"    <reg name=\"x26\" bitsize=\"32\" group=\"general\"/>\n"
-                          //"    <reg name=\"x27\" bitsize=\"32\" group=\"general\"/>\n"
-                          //"    <reg name=\"x28\" bitsize=\"32\" group=\"general\"/>\n"
-                          //"    <reg name=\"x29\" bitsize=\"32\" group=\"general\"/>\n"
-                          //"    <reg name=\"x30\" bitsize=\"32\" group=\"general\"/>\n"
-                          //"    <reg name=\"x31\" bitsize=\"32\" group=\"general\"/>\n"
-                          //"  </feature>\n"
-                          "</target>"};
+        "<target><architecture>riscv:rv32</architecture>"
+        //"  <feature name=\"org.gnu.gdb.riscv.rv32i\">\n"
+        //"    <reg name=\"x0\"  bitsize=\"32\" group=\"general\"/>\n"
+        //"    <reg name=\"x1\"  bitsize=\"32\" group=\"general\"/>\n"
+        //"    <reg name=\"x2\"  bitsize=\"32\" group=\"general\"/>\n"
+        //"    <reg name=\"x3\"  bitsize=\"32\" group=\"general\"/>\n"
+        //"    <reg name=\"x4\"  bitsize=\"32\" group=\"general\"/>\n"
+        //"    <reg name=\"x5\"  bitsize=\"32\" group=\"general\"/>\n"
+        //"    <reg name=\"x6\"  bitsize=\"32\" group=\"general\"/>\n"
+        //"    <reg name=\"x7\"  bitsize=\"32\" group=\"general\"/>\n"
+        //"    <reg name=\"x8\"  bitsize=\"32\" group=\"general\"/>\n"
+        //"    <reg name=\"x9\"  bitsize=\"32\" group=\"general\"/>\n"
+        //"    <reg name=\"x10\" bitsize=\"32\" group=\"general\"/>\n"
+        //"    <reg name=\"x11\" bitsize=\"32\" group=\"general\"/>\n"
+        //"    <reg name=\"x12\" bitsize=\"32\" group=\"general\"/>\n"
+        //"    <reg name=\"x13\" bitsize=\"32\" group=\"general\"/>\n"
+        //"    <reg name=\"x14\" bitsize=\"32\" group=\"general\"/>\n"
+        //"    <reg name=\"x15\" bitsize=\"32\" group=\"general\"/>\n"
+        //"    <reg name=\"x16\" bitsize=\"32\" group=\"general\"/>\n"
+        //"    <reg name=\"x17\" bitsize=\"32\" group=\"general\"/>\n"
+        //"    <reg name=\"x18\" bitsize=\"32\" group=\"general\"/>\n"
+        //"    <reg name=\"x19\" bitsize=\"32\" group=\"general\"/>\n"
+        //"    <reg name=\"x20\" bitsize=\"32\" group=\"general\"/>\n"
+        //"    <reg name=\"x21\" bitsize=\"32\" group=\"general\"/>\n"
+        //"    <reg name=\"x22\" bitsize=\"32\" group=\"general\"/>\n"
+        //"    <reg name=\"x23\" bitsize=\"32\" group=\"general\"/>\n"
+        //"    <reg name=\"x24\" bitsize=\"32\" group=\"general\"/>\n"
+        //"    <reg name=\"x25\" bitsize=\"32\" group=\"general\"/>\n"
+        //"    <reg name=\"x26\" bitsize=\"32\" group=\"general\"/>\n"
+        //"    <reg name=\"x27\" bitsize=\"32\" group=\"general\"/>\n"
+        //"    <reg name=\"x28\" bitsize=\"32\" group=\"general\"/>\n"
+        //"    <reg name=\"x29\" bitsize=\"32\" group=\"general\"/>\n"
+        //"    <reg name=\"x30\" bitsize=\"32\" group=\"general\"/>\n"
+        //"    <reg name=\"x31\" bitsize=\"32\" group=\"general\"/>\n"
+        //"  </feature>\n"
+        "</target>"};
     out_buf = res;
     return Ok;
 }

src/sysc/core_complex.h

@@ -69,7 +69,7 @@ struct core_trace;
 
 class core_complex : public sc_core::sc_module, public scc::traceable {
 public:
-    tlm::scc::initiator_mixin<tlm::scc::scv::tlm_rec_initiator_socket<32>> initiator{"intor"};
+    tlm::scc::initiator_mixin<tlm::tlm_initiator_socket<32>> initiator{"intor"};
 
     sc_core::sc_in<bool> rst_i{"rst_i"};
 
@@ -84,7 +84,7 @@ public:
 #ifndef CWR_SYSTEMC
 	sc_core::sc_in<sc_core::sc_time> clk_i{"clk_i"};
 
-    sc_core::sc_port<tlm::tlm_peek_if<uint64_t>, 1, sc_core::SC_ZERO_OR_MORE_BOUND> mtime_o;
+    sc_core::sc_port<tlm::tlm_peek_if<uint64_t>, 1, sc_core::SC_ZERO_OR_MORE_BOUND> mtime_o{"mtime_o"};
 
     cci::cci_param<std::string> elf_file{"elf_file", ""};