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base: DBT-RISE:459794b863c8707071f72667a33a10d7dd1f7c76
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DBT-RISE:main DBT-RISE:develop DBT-RISE:featture/interp_instr_cache DBT-RISE:feature/privilege_refactor DBT-RISE:feature/htif DBT-RISE:feature/eve_checkin DBT-RISE:feature/iss_factory DBT-RISE:feature/core_factory DBT-RISE:Trace_enhancement DBT-RISE:feature/reduced_output DBT-RISE:msvc_compat DBT-RISE:hotfix/latest_scc DBT-RISE:feature/interpreter
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compare: DBT-RISE:49d09a05d77adb7602ea1ed7200e649edc7c7f83
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DBT-RISE:develop DBT-RISE:featture/interp_instr_cache DBT-RISE:feature/privilege_refactor DBT-RISE:feature/htif DBT-RISE:feature/eve_checkin DBT-RISE:main DBT-RISE:feature/iss_factory DBT-RISE:feature/core_factory DBT-RISE:Trace_enhancement DBT-RISE:feature/reduced_output DBT-RISE:msvc_compat DBT-RISE:hotfix/latest_scc DBT-RISE:feature/interpreter

1 Commits
459794b863 ... 49d09a05d7

Author SHA1 Message Date
Eyck Jentzsch
49d09a05d7 fix access rights to debug CSR register (#268) 2021-11-07 16:45:10 +01:00
2 changed files with 63 additions and 24 deletions
Expand all files Collapse all files

44
incl/iss/arch/riscv_hart_m_p.h
View File

@@ -287,7 +287,6 @@ protected:
};
std::vector<clic_int_reg_t> clic_int_reg;
private:
iss::status read_csr_reg(unsigned addr, reg_t &val);
iss::status write_csr_reg(unsigned addr, reg_t val);
iss::status read_null(unsigned addr, reg_t &val);
@@ -307,18 +306,23 @@ private:
iss::status write_ip(unsigned addr, reg_t val);
iss::status read_hartid(unsigned addr, reg_t &val);
iss::status write_epc(unsigned addr, reg_t val);
iss::status write_dcsr(unsigned addr, reg_t val);
iss::status write_intstatus(unsigned addr, reg_t val);
iss::status write_intthresh(unsigned addr, reg_t val);
iss::status write_dcsr_dcsr(unsigned addr, reg_t val);
iss::status read_dcsr_reg(unsigned addr, reg_t &val);
iss::status write_dcsr_reg(unsigned addr, reg_t val);
reg_t mhartid_reg{0x0};
std::function<iss::status(phys_addr_t, unsigned, uint8_t *const)>mem_read_cb;
std::function<iss::status(phys_addr_t, unsigned, const uint8_t *const)> mem_write_cb;
protected:
void check_interrupt();
bool pmp_check(const access_type type, const uint64_t addr, const unsigned len);
uint64_t clic_base_addr{0};
unsigned clic_num_irq{0};
unsigned clic_num_trigger{0};
unsigned mcause_max_irq{16};
bool debug_mode_active{false};
};
template <typename BASE, features_e FEAT>
@@ -389,14 +393,14 @@ riscv_hart_m_p<BASE, FEAT>::riscv_hart_m_p()
csr_wr_cb[marchid] = &this_class::write_null;
csr_wr_cb[mimpid] = &this_class::write_null;
if(FEAT & FEAT_DEBUG){
csr_wr_cb[dscratch0] = &this_class::write_csr_reg;
csr_rd_cb[dscratch0] = &this_class::read_csr_reg;
csr_wr_cb[dscratch1] = &this_class::write_csr_reg;
csr_rd_cb[dscratch1] = &this_class::read_csr_reg;
csr_wr_cb[dpc] = &this_class::write_csr_reg;
csr_rd_cb[dpc] = &this_class::read_csr_reg;
csr_wr_cb[dcsr] = &this_class::write_dcsr;
csr_rd_cb[dcsr] = &this_class::read_csr_reg;
csr_wr_cb[dscratch0] = &this_class::write_dcsr_reg;
csr_rd_cb[dscratch0] = &this_class::read_dcsr_reg;
csr_wr_cb[dscratch1] = &this_class::write_dcsr_reg;
csr_rd_cb[dscratch1] = &this_class::read_dcsr_reg;
csr_wr_cb[dpc] = &this_class::write_dcsr_reg;
csr_rd_cb[dpc] = &this_class::read_dcsr_reg;
csr_wr_cb[dcsr] = &this_class::write_dcsr_dcsr;
csr_rd_cb[dcsr] = &this_class::read_dcsr_reg;
}
}
@@ -810,7 +814,9 @@ template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>
return iss::Ok;
}
template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::write_dcsr(unsigned addr, reg_t val) {
template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::write_dcsr_dcsr(unsigned addr, reg_t val) {
if(!debug_mode_active)
throw illegal_instruction_fault(this->fault_data);
// +-------------- ebreakm
// | +---------- stepi
// | | +++----- cause
@@ -819,6 +825,20 @@ template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>
return iss::Ok;
}
template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::read_dcsr_reg(unsigned addr, reg_t &val) {
if(!debug_mode_active)
throw illegal_instruction_fault(this->fault_data);
val = csr[addr];
return iss::Ok;
}
template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::write_dcsr_reg(unsigned addr, reg_t val) {
if(!debug_mode_active)
throw illegal_instruction_fault(this->fault_data);
csr[addr] = val;
return iss::Ok;
}
template <typename BASE, features_e FEAT>
iss::status riscv_hart_m_p<BASE, FEAT>::read_mem(phys_addr_t paddr, unsigned length, uint8_t *const data) {
if(mem_read_cb) return mem_read_cb(paddr, length, data);

43
incl/iss/arch/riscv_hart_mu_p.h
View File

@@ -302,7 +302,6 @@ protected:
};
std::vector<clic_int_reg_t> clic_int_reg;
private:
iss::status read_csr_reg(unsigned addr, reg_t &val);
iss::status write_csr_reg(unsigned addr, reg_t val);
iss::status read_null(unsigned addr, reg_t &val);
@@ -324,21 +323,23 @@ private:
iss::status write_edeleg(unsigned addr, reg_t val);
iss::status read_hartid(unsigned addr, reg_t &val);
iss::status write_epc(unsigned addr, reg_t val);
iss::status write_dcsr(unsigned addr, reg_t val);
iss::status write_intstatus(unsigned addr, reg_t val);
iss::status write_intthresh(unsigned addr, reg_t val);
iss::status write_dcsr_dcsr(unsigned addr, reg_t val);
iss::status read_dcsr_reg(unsigned addr, reg_t &val);
iss::status write_dcsr_reg(unsigned addr, reg_t val);
reg_t mhartid_reg{0x0};
std::function<iss::status(phys_addr_t, unsigned, uint8_t *const)>mem_read_cb;
std::function<iss::status(phys_addr_t, unsigned, const uint8_t *const)> mem_write_cb;
protected:
void check_interrupt();
bool pmp_check(const access_type type, const uint64_t addr, const unsigned len);
uint64_t clic_base_addr{0};
unsigned clic_num_irq{0};
unsigned clic_num_trigger{0};
unsigned mcause_max_irq{16};
bool debug_mode_active{false};
};
template <typename BASE, features_e FEAT>
@@ -464,14 +465,14 @@ riscv_hart_mu_p<BASE, FEAT>::riscv_hart_mu_p()
mcause_max_irq=clic_num_irq+16;
}
if(FEAT & FEAT_DEBUG){
csr_wr_cb[dscratch0] = &this_class::write_csr_reg;
csr_rd_cb[dscratch0] = &this_class::read_csr_reg;
csr_wr_cb[dscratch1] = &this_class::write_csr_reg;
csr_rd_cb[dscratch1] = &this_class::read_csr_reg;
csr_wr_cb[dpc] = &this_class::write_csr_reg;
csr_rd_cb[dpc] = &this_class::read_csr_reg;
csr_wr_cb[dcsr] = &this_class::write_dcsr;
csr_rd_cb[dcsr] = &this_class::read_csr_reg;
csr_wr_cb[dscratch0] = &this_class::write_dcsr_reg;
csr_rd_cb[dscratch0] = &this_class::read_dcsr_reg;
csr_wr_cb[dscratch1] = &this_class::write_dcsr_reg;
csr_rd_cb[dscratch1] = &this_class::read_dcsr_reg;
csr_wr_cb[dpc] = &this_class::write_dcsr_reg;
csr_rd_cb[dpc] = &this_class::read_dcsr_reg;
csr_wr_cb[dcsr] = &this_class::write_dcsr_dcsr;
csr_rd_cb[dcsr] = &this_class::read_dcsr_reg;
}
}
@@ -977,7 +978,9 @@ template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT
return iss::Ok;
}
template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT>::write_dcsr(unsigned addr, reg_t val) {
template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT>::write_dcsr_dcsr(unsigned addr, reg_t val) {
if(!debug_mode_active)
throw illegal_instruction_fault(this->fault_data);
// +-------------- ebreakm
// | +---------- stepi
// | | +++----- cause
@@ -985,6 +988,22 @@ template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT
csr[addr] = val & 0b1000100111000100U;
return iss::Ok;
}
template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT>::read_dcsr_reg(unsigned addr, reg_t &val) {
if(!debug_mode_active)
throw illegal_instruction_fault(this->fault_data);
val = csr[addr];
return iss::Ok;
}
template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT>::write_dcsr_reg(unsigned addr, reg_t val) {
if(!debug_mode_active)
throw illegal_instruction_fault(this->fault_data);
csr[addr] = val;
return iss::Ok;
}
template<typename BASE, features_e FEAT>
iss::status riscv_hart_mu_p<BASE, FEAT>::write_intthresh(unsigned addr, reg_t val) {
csr[addr]= val &0xff;