adds formatting fixes

contrib/instr/TGC5C_instr.yaml

@@ -1,5 +1,5 @@
 
-RV32I: 
+RVI: 
   LUI:
     index: 0
     encoding: 0b00000000000000000000000000110111
@@ -27,84 +27,84 @@ RV32I:
     mask: 0b00000000000000000111000001111111
     size:   32
     branch:   true
-    delay:   [1,2]
+    delay:   [1,1]
   BEQ:
     index: 4
     encoding: 0b00000000000000000000000001100011
     mask: 0b00000000000000000111000001111111
     size:   32
     branch:   true
-    delay:   [1,2]
+    delay:   [1,1]
   BNE:
     index: 5
     encoding: 0b00000000000000000001000001100011
     mask: 0b00000000000000000111000001111111
     size:   32
     branch:   true
-    delay:   [1,2]
+    delay:   [1,1]
   BLT:
     index: 6
     encoding: 0b00000000000000000100000001100011
     mask: 0b00000000000000000111000001111111
     size:   32
     branch:   true
-    delay:   [1,2]
+    delay:   [1,1]
   BGE:
     index: 7
     encoding: 0b00000000000000000101000001100011
     mask: 0b00000000000000000111000001111111
     size:   32
     branch:   true
-    delay:   [1,2]
+    delay:   [1,1]
   BLTU:
     index: 8
     encoding: 0b00000000000000000110000001100011
     mask: 0b00000000000000000111000001111111
     size:   32
     branch:   true
-    delay:   [1,2]
+    delay:   [1,1]
   BGEU:
     index: 9
     encoding: 0b00000000000000000111000001100011
     mask: 0b00000000000000000111000001111111
     size:   32
     branch:   true
-    delay:   [1,2]
+    delay:   [1,1]
   LB:
     index: 10
     encoding: 0b00000000000000000000000000000011
     mask: 0b00000000000000000111000001111111
     size:   32
     branch:   false
-    delay:   2
+    delay:   1
   LH:
     index: 11
     encoding: 0b00000000000000000001000000000011
     mask: 0b00000000000000000111000001111111
     size:   32
     branch:   false
-    delay:   2
+    delay:   1
   LW:
     index: 12
     encoding: 0b00000000000000000010000000000011
     mask: 0b00000000000000000111000001111111
     size:   32
     branch:   false
-    delay:   2
+    delay:   1
   LBU:
     index: 13
     encoding: 0b00000000000000000100000000000011
     mask: 0b00000000000000000111000001111111
     size:   32
     branch:   false
-    delay:   2
+    delay:   1
   LHU:
     index: 14
     encoding: 0b00000000000000000101000000000011
     mask: 0b00000000000000000111000001111111
     size:   32
     branch:   false
-    delay:   2
+    delay:   1
   SB:
     index: 15
     encoding: 0b00000000000000000000000000100011
@@ -356,56 +356,56 @@ RV32M:
     mask: 0b11111110000000000111000001111111
     size:   32
     branch:   false
-    delay:   2
+    delay:   1
   MULH:
     index: 50
     encoding: 0b00000010000000000001000000110011
     mask: 0b11111110000000000111000001111111
     size:   32
     branch:   false
-    delay:   2
+    delay:   1
   MULHSU:
     index: 51
     encoding: 0b00000010000000000010000000110011
     mask: 0b11111110000000000111000001111111
     size:   32
     branch:   false
-    delay:   2
+    delay:   1
   MULHU:
     index: 52
     encoding: 0b00000010000000000011000000110011
     mask: 0b11111110000000000111000001111111
     size:   32
     branch:   false
-    delay:   2
+    delay:   1
   DIV:
     index: 53
     encoding: 0b00000010000000000100000000110011
     mask: 0b11111110000000000111000001111111
     size:   32
     branch:   false
-    delay:   17
+    delay:   1
   DIVU:
     index: 54
     encoding: 0b00000010000000000101000000110011
     mask: 0b11111110000000000111000001111111
     size:   32
     branch:   false
-    delay:   17
+    delay:   1
   REM:
     index: 55
     encoding: 0b00000010000000000110000000110011
     mask: 0b11111110000000000111000001111111
     size:   32
     branch:   false
-    delay:   17
+    delay:   1
   REMU:
     index: 56
     encoding: 0b00000010000000000111000000110011
     mask: 0b11111110000000000111000001111111
     size:   32
     branch:   false
-    delay:   17
+    delay:   1
 Zca: 
   C__ADDI4SPN:
     index: 57
@@ -420,7 +420,7 @@ Zca:
     mask: 0b1110000000000011
     size:   16
     branch:   false
-    delay:   2
+    delay:   1
   C__SW:
     index: 59
     encoding: 0b1100000000000000
@@ -542,14 +542,14 @@ Zca:
     mask: 0b1110000000000011
     size:   16
     branch:   true
-    delay:   [1,2]
+    delay:   [1,1]
   C__BNEZ:
     index: 76
     encoding: 0b1110000000000001
     mask: 0b1110000000000011
     size:   16
     branch:   true
-    delay:   [1,2]
+    delay:   [1,1]
   C__SLLI:
     index: 77
     encoding: 0b0000000000000010
@@ -564,7 +564,7 @@ Zca:
     mask: 0b1110000000000011
     size:   16
     branch:   false
-    delay:   2
+    delay:   1
   C__MV:
     index: 79
     encoding: 0b1000000000000010

gen_input/templates/CORENAME.cpp.gtl

@@ -37,6 +37,7 @@ def getRegisterSizes(){
     return regs
 }
 %>
+// clang-format off
 #include "${coreDef.name.toLowerCase()}.h"
 #include "util/ities.h"
 #include <util/logging.h>
@@ -73,4 +74,4 @@ uint8_t *${coreDef.name.toLowerCase()}::get_regs_base_ptr() {
 ${coreDef.name.toLowerCase()}::phys_addr_t ${coreDef.name.toLowerCase()}::virt2phys(const iss::addr_t &addr) {
     return phys_addr_t(addr.access, addr.space, addr.val&traits<${coreDef.name.toLowerCase()}>::addr_mask);
 }
-
+// clang-format on

gen_input/templates/CORENAME.h.gtl

@@ -60,7 +60,7 @@ def getCString(def val){
 %>
 #ifndef _${coreDef.name.toUpperCase()}_H_
 #define _${coreDef.name.toUpperCase()}_H_
-
+// clang-format off
 #include <array>
 #include <iss/arch/traits.h>
 #include <iss/arch_if.h>
@@ -174,3 +174,4 @@ if(fcsr != null) {%>
 }
 }            
 #endif /* _${coreDef.name.toUpperCase()}_H_ */
+// clang-format on

gen_input/templates/CORENAME_sysc.cpp.gtl

@@ -29,7 +29,7 @@
  * POSSIBILITY OF SUCH DAMAGE.
  *
  *******************************************************************************/
-
+// clang-format off
 #include <sysc/iss_factory.h>
 #include <iss/arch/${coreDef.name.toLowerCase()}.h>
 #include <iss/arch/riscv_hart_m_p.h>
@@ -128,3 +128,4 @@ volatile std::array<bool, ${array_count}> ${coreDef.name.toLowerCase()}_init = {
 }
 #endif
 }
+// clang-format on

gen_input/templates/asmjit/CORENAME.cpp.gtl

@@ -29,7 +29,7 @@
  * POSSIBILITY OF SUCH DAMAGE.
  *
  *******************************************************************************/
-
+// clang-format off
 #include <iss/arch/${coreDef.name.toLowerCase()}.h>
 #include <iss/debugger/gdb_session.h>
 #include <iss/debugger/server.h>
@@ -278,3 +278,4 @@ volatile std::array<bool, 2> dummy = {
 };
 }
 }
+// clang-format on

gen_input/templates/interp/CORENAME.cpp.gtl

@@ -34,6 +34,7 @@ def nativeTypeSize(int size){
     if(size<=8) return 8; else if(size<=16) return 16; else if(size<=32) return 32; else return 64;
 }
 %>
+// clang-format off
 #include <iss/arch/${coreDef.name.toLowerCase()}.h>
 #include <iss/debugger/gdb_session.h>
 #include <iss/debugger/server.h>
@@ -377,3 +378,4 @@ volatile std::array<bool, 2> dummy = {
 };
 }
 }
+// clang-format on

gen_input/templates/llvm/CORENAME.cpp.gtl

@@ -29,7 +29,7 @@
  * POSSIBILITY OF SUCH DAMAGE.
  *
  *******************************************************************************/
-
+// clang-format off
 #include <iss/arch/${coreDef.name.toLowerCase()}.h>
 #include <iss/debugger/gdb_session.h>
 #include <iss/debugger/server.h>
@@ -380,3 +380,4 @@ volatile std::array<bool, 2> dummy = {
 };
 }
 }
+// clang-format on

gen_input/templates/tcc/CORENAME.cpp.gtl

@@ -29,7 +29,7 @@
  * POSSIBILITY OF SUCH DAMAGE.
  *
  *******************************************************************************/
-
+// clang-format off
 #include <iss/arch/${coreDef.name.toLowerCase()}.h>
 #include <iss/debugger/gdb_session.h>
 #include <iss/debugger/server.h>
@@ -344,3 +344,4 @@ volatile std::array<bool, 2> dummy = {
 };
 }
 }
+// clang-format on

src/iss/arch/tgc5c.cpp

@@ -30,12 +30,13 @@
  *
  *******************************************************************************/
 
+// clang-format off
 #include "tgc5c.h"
 #include "util/ities.h"
+#include <util/logging.h>
 #include <cstdio>
 #include <cstring>
 #include <fstream>
-#include <util/logging.h>
 
 using namespace iss::arch;
 
@@ -59,8 +60,11 @@ void tgc5c::reset(uint64_t address) {
     reg.icount=0;
 }
 
-uint8_t* tgc5c::get_regs_base_ptr() { return reinterpret_cast<uint8_t*>(&reg); }
+uint8_t *tgc5c::get_regs_base_ptr() {
+	return reinterpret_cast<uint8_t*>(&reg);
+}
 
 tgc5c::phys_addr_t tgc5c::virt2phys(const iss::addr_t &addr) {
     return phys_addr_t(addr.access, addr.space, addr.val&traits<tgc5c>::addr_mask);
 }
+// clang-format on

src/iss/arch/tgc5c.h

@@ -32,7 +32,7 @@
 
 #ifndef _TGC5C_H_
 #define _TGC5C_H_
-
+// clang-format off
 #include <array>
 #include <iss/arch/traits.h>
 #include <iss/arch_if.h>
@@ -47,76 +47,18 @@ template <> struct traits<tgc5c> {
 
     constexpr static char const* const core_type = "TGC5C";
     
-    static constexpr std::array<const char*, 36> reg_names{{"x0",  "x1",  "x2",  "x3",  "x4",  "x5",  "x6",      "x7",   "x8",
-                                                            "x9",  "x10", "x11", "x12", "x13", "x14", "x15",     "x16",  "x17",
-                                                            "x18", "x19", "x20", "x21", "x22", "x23", "x24",     "x25",  "x26",
-                                                            "x27", "x28", "x29", "x30", "x31", "pc",  "next_pc", "priv", "dpc"}};
+    static constexpr std::array<const char*, 36> reg_names{
+        {"x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28", "x29", "x30", "x31", "pc", "next_pc", "priv", "dpc"}};
  
     static constexpr std::array<const char*, 36> reg_aliases{
-        {"zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", "s0",  "s1",  "a0", "a1", "a2", "a3", "a4", "a5",      "a6",   "a7",
-         "s2",   "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6", "pc", "next_pc", "priv", "dpc"}};
+        {"zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", "s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5", "a6", "a7", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6", "pc", "next_pc", "priv", "dpc"}};
 
-    enum constants {
-        MISA_VAL = 1073746180ULL,
-        MARCHID_VAL = 2147483651ULL,
-        XLEN = 32ULL,
-        INSTR_ALIGNMENT = 2ULL,
-        RFS = 32ULL,
-        fence = 0ULL,
-        fencei = 1ULL,
-        fencevmal = 2ULL,
-        fencevmau = 3ULL,
-        CSR_SIZE = 4096ULL,
-        MUL_LEN = 64ULL
-    };
+    enum constants {MISA_VAL=1073746180ULL, MARCHID_VAL=2147483651ULL, XLEN=32ULL, INSTR_ALIGNMENT=2ULL, RFS=32ULL, fence=0ULL, fencei=1ULL, fencevmal=2ULL, fencevmau=3ULL, CSR_SIZE=4096ULL, MUL_LEN=64ULL};
 
     constexpr static unsigned FP_REGS_SIZE = 0;
 
     enum reg_e {
-        X0,
-        X1,
-        X2,
-        X3,
-        X4,
-        X5,
-        X6,
-        X7,
-        X8,
-        X9,
-        X10,
-        X11,
-        X12,
-        X13,
-        X14,
-        X15,
-        X16,
-        X17,
-        X18,
-        X19,
-        X20,
-        X21,
-        X22,
-        X23,
-        X24,
-        X25,
-        X26,
-        X27,
-        X28,
-        X29,
-        X30,
-        X31,
-        PC,
-        NEXT_PC,
-        PRIV,
-        DPC,
-        NUM_REGS,
-        TRAP_STATE = NUM_REGS,
-        PENDING_TRAP,
-        ICOUNT,
-        CYCLE,
-        INSTRET,
-        INSTRUCTION,
-        LAST_BRANCH
+        X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X12, X13, X14, X15, X16, X17, X18, X19, X20, X21, X22, X23, X24, X25, X26, X27, X28, X29, X30, X31, PC, NEXT_PC, PRIV, DPC, NUM_REGS, TRAP_STATE=NUM_REGS, PENDING_TRAP, ICOUNT, CYCLE, INSTRET, INSTRUCTION, LAST_BRANCH
     };
 
     using reg_t = uint32_t;
@@ -129,13 +71,11 @@ template <> struct traits<tgc5c> {
 
     using phys_addr_t = iss::typed_addr_t<iss::address_type::PHYSICAL>;
 
-    static constexpr std::array<const uint32_t, 43> reg_bit_widths{{32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32,
-                                                                    32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32,
-                                                                    32, 32, 32, 32, 8,  32, 32, 32, 64, 64, 64, 32, 32}};
+    static constexpr std::array<const uint32_t, 43> reg_bit_widths{
+        {32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,8,32,32,32,64,64,64,32,32}};
 
     static constexpr std::array<const uint32_t, 43> reg_byte_offsets{
-        {0,  4,  8,  12,  16,  20,  24,  28,  32,  36,  40,  44,  48,  52,  56,  60,  64,  68,  72,  76,  80, 84,
-         88, 92, 96, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 137, 141, 145, 149, 157, 165, 173, 177}};
+        {0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,137,141,145,149,157,165,173,177}};
 
     static const uint64_t addr_mask = (reg_t(1) << (XLEN - 1)) | ((reg_t(1) << (XLEN - 1)) - 1);
 
@@ -261,6 +201,7 @@ struct tgc5c : public arch_if {
 
     inline uint32_t get_last_branch() { return reg.last_branch; }
 
+
 #pragma pack(push, 1)
     struct TGC5C_regs { 
         uint32_t X0 = 0; 
@@ -313,8 +254,10 @@ struct tgc5c : public arch_if {
 
     uint32_t get_fcsr(){return 0;}
     void set_fcsr(uint32_t val){}
+
 };
 
-} // namespace arch
-} // namespace iss
+}
+}            
 #endif /* _TGC5C_H_ */
+// clang-format on