Confronta commit
1 Commit
458c773e19
...
e48597b2b7
| Autore | SHA1 | Data | |
|---|---|---|---|
| e48597b2b7 |
@ -1,5 +1,5 @@
|
||||
|
||||
RV32I:
|
||||
RVI:
|
||||
LUI:
|
||||
index: 0
|
||||
encoding: 0b00000000000000000000000000110111
|
||||
@ -27,84 +27,84 @@ RV32I:
|
||||
mask: 0b00000000000000000111000001111111
|
||||
size: 32
|
||||
branch: true
|
||||
delay: [1,2]
|
||||
delay: [1,1]
|
||||
BEQ:
|
||||
index: 4
|
||||
encoding: 0b00000000000000000000000001100011
|
||||
mask: 0b00000000000000000111000001111111
|
||||
size: 32
|
||||
branch: true
|
||||
delay: [1,2]
|
||||
delay: [1,1]
|
||||
BNE:
|
||||
index: 5
|
||||
encoding: 0b00000000000000000001000001100011
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||||
mask: 0b00000000000000000111000001111111
|
||||
size: 32
|
||||
branch: true
|
||||
delay: [1,2]
|
||||
delay: [1,1]
|
||||
BLT:
|
||||
index: 6
|
||||
encoding: 0b00000000000000000100000001100011
|
||||
mask: 0b00000000000000000111000001111111
|
||||
size: 32
|
||||
branch: true
|
||||
delay: [1,2]
|
||||
delay: [1,1]
|
||||
BGE:
|
||||
index: 7
|
||||
encoding: 0b00000000000000000101000001100011
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||||
mask: 0b00000000000000000111000001111111
|
||||
size: 32
|
||||
branch: true
|
||||
delay: [1,2]
|
||||
delay: [1,1]
|
||||
BLTU:
|
||||
index: 8
|
||||
encoding: 0b00000000000000000110000001100011
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||||
mask: 0b00000000000000000111000001111111
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||||
size: 32
|
||||
branch: true
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||||
delay: [1,2]
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||||
delay: [1,1]
|
||||
BGEU:
|
||||
index: 9
|
||||
encoding: 0b00000000000000000111000001100011
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||||
mask: 0b00000000000000000111000001111111
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||||
size: 32
|
||||
branch: true
|
||||
delay: [1,2]
|
||||
delay: [1,1]
|
||||
LB:
|
||||
index: 10
|
||||
encoding: 0b00000000000000000000000000000011
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||||
mask: 0b00000000000000000111000001111111
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||||
size: 32
|
||||
branch: false
|
||||
delay: 2
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||||
delay: 1
|
||||
LH:
|
||||
index: 11
|
||||
encoding: 0b00000000000000000001000000000011
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||||
mask: 0b00000000000000000111000001111111
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||||
size: 32
|
||||
branch: false
|
||||
delay: 2
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||||
delay: 1
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||||
LW:
|
||||
index: 12
|
||||
encoding: 0b00000000000000000010000000000011
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||||
mask: 0b00000000000000000111000001111111
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||||
size: 32
|
||||
branch: false
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||||
delay: 2
|
||||
delay: 1
|
||||
LBU:
|
||||
index: 13
|
||||
encoding: 0b00000000000000000100000000000011
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||||
mask: 0b00000000000000000111000001111111
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||||
size: 32
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||||
branch: false
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||||
delay: 2
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||||
delay: 1
|
||||
LHU:
|
||||
index: 14
|
||||
encoding: 0b00000000000000000101000000000011
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||||
mask: 0b00000000000000000111000001111111
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||||
size: 32
|
||||
branch: false
|
||||
delay: 2
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||||
delay: 1
|
||||
SB:
|
||||
index: 15
|
||||
encoding: 0b00000000000000000000000000100011
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||||
@ -356,56 +356,56 @@ RV32M:
|
||||
mask: 0b11111110000000000111000001111111
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||||
size: 32
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||||
branch: false
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||||
delay: 2
|
||||
delay: 1
|
||||
MULH:
|
||||
index: 50
|
||||
encoding: 0b00000010000000000001000000110011
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||||
mask: 0b11111110000000000111000001111111
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||||
size: 32
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||||
branch: false
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||||
delay: 2
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||||
delay: 1
|
||||
MULHSU:
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||||
index: 51
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||||
encoding: 0b00000010000000000010000000110011
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||||
mask: 0b11111110000000000111000001111111
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||||
size: 32
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||||
branch: false
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||||
delay: 2
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||||
delay: 1
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||||
MULHU:
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||||
index: 52
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||||
encoding: 0b00000010000000000011000000110011
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||||
mask: 0b11111110000000000111000001111111
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||||
size: 32
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||||
branch: false
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||||
delay: 2
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||||
delay: 1
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||||
DIV:
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||||
index: 53
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||||
encoding: 0b00000010000000000100000000110011
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||||
mask: 0b11111110000000000111000001111111
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||||
size: 32
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||||
branch: false
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||||
delay: 17
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||||
delay: 1
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||||
DIVU:
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||||
index: 54
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||||
encoding: 0b00000010000000000101000000110011
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||||
mask: 0b11111110000000000111000001111111
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||||
size: 32
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||||
branch: false
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||||
delay: 17
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||||
delay: 1
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||||
REM:
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||||
index: 55
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||||
encoding: 0b00000010000000000110000000110011
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||||
mask: 0b11111110000000000111000001111111
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||||
size: 32
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||||
branch: false
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||||
delay: 17
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||||
delay: 1
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||||
REMU:
|
||||
index: 56
|
||||
encoding: 0b00000010000000000111000000110011
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||||
mask: 0b11111110000000000111000001111111
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||||
size: 32
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||||
branch: false
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||||
delay: 17
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||||
delay: 1
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||||
Zca:
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||||
C__ADDI4SPN:
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||||
index: 57
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||||
@ -420,7 +420,7 @@ Zca:
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||||
mask: 0b1110000000000011
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||||
size: 16
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||||
branch: false
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||||
delay: 2
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||||
delay: 1
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||||
C__SW:
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||||
index: 59
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||||
encoding: 0b1100000000000000
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||||
@ -542,14 +542,14 @@ Zca:
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||||
mask: 0b1110000000000011
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||||
size: 16
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||||
branch: true
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||||
delay: [1,2]
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||||
delay: [1,1]
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||||
C__BNEZ:
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||||
index: 76
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||||
encoding: 0b1110000000000001
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||||
mask: 0b1110000000000011
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||||
size: 16
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||||
branch: true
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||||
delay: [1,2]
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||||
delay: [1,1]
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||||
C__SLLI:
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||||
index: 77
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||||
encoding: 0b0000000000000010
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||||
@ -564,7 +564,7 @@ Zca:
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||||
mask: 0b1110000000000011
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||||
size: 16
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||||
branch: false
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||||
delay: 2
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||||
delay: 1
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||||
C__MV:
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||||
index: 79
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||||
encoding: 0b1000000000000010
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||||
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||||
@ -37,6 +37,7 @@ def getRegisterSizes(){
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return regs
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}
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||||
%>
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||||
// clang-format off
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||||
#include "${coreDef.name.toLowerCase()}.h"
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#include "util/ities.h"
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#include <util/logging.h>
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||||
@ -73,4 +74,4 @@ uint8_t *${coreDef.name.toLowerCase()}::get_regs_base_ptr() {
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${coreDef.name.toLowerCase()}::phys_addr_t ${coreDef.name.toLowerCase()}::virt2phys(const iss::addr_t &addr) {
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||||
return phys_addr_t(addr.access, addr.space, addr.val&traits<${coreDef.name.toLowerCase()}>::addr_mask);
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||||
}
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||||
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||||
// clang-format on
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||||
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||||
@ -60,7 +60,7 @@ def getCString(def val){
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%>
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||||
#ifndef _${coreDef.name.toUpperCase()}_H_
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#define _${coreDef.name.toUpperCase()}_H_
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||||
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||||
// clang-format off
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||||
#include <array>
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||||
#include <iss/arch/traits.h>
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#include <iss/arch_if.h>
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||||
@ -174,3 +174,4 @@ if(fcsr != null) {%>
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||||
}
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||||
}
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||||
#endif /* _${coreDef.name.toUpperCase()}_H_ */
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||||
// clang-format on
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||||
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||||
@ -29,7 +29,7 @@
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||||
* POSSIBILITY OF SUCH DAMAGE.
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||||
*
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||||
*******************************************************************************/
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||||
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||||
// clang-format off
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||||
#include <sysc/iss_factory.h>
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#include <iss/arch/${coreDef.name.toLowerCase()}.h>
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#include <iss/arch/riscv_hart_m_p.h>
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@ -128,3 +128,4 @@ volatile std::array<bool, ${array_count}> ${coreDef.name.toLowerCase()}_init = {
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}
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#endif
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||||
}
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||||
// clang-format on
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||||
@ -29,7 +29,7 @@
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||||
* POSSIBILITY OF SUCH DAMAGE.
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||||
*
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||||
*******************************************************************************/
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||||
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||||
// clang-format off
|
||||
#include <iss/arch/${coreDef.name.toLowerCase()}.h>
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#include <iss/debugger/gdb_session.h>
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#include <iss/debugger/server.h>
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||||
@ -278,3 +278,4 @@ volatile std::array<bool, 2> dummy = {
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||||
};
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||||
}
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||||
}
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||||
// clang-format on
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||||
@ -34,6 +34,7 @@ def nativeTypeSize(int size){
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||||
if(size<=8) return 8; else if(size<=16) return 16; else if(size<=32) return 32; else return 64;
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||||
}
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||||
%>
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||||
// clang-format off
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||||
#include <iss/arch/${coreDef.name.toLowerCase()}.h>
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||||
#include <iss/debugger/gdb_session.h>
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||||
#include <iss/debugger/server.h>
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||||
@ -377,3 +378,4 @@ volatile std::array<bool, 2> dummy = {
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||||
};
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||||
}
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||||
}
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||||
// clang-format on
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||||
@ -29,7 +29,7 @@
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||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
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||||
*******************************************************************************/
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||||
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||||
// clang-format off
|
||||
#include <iss/arch/${coreDef.name.toLowerCase()}.h>
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||||
#include <iss/debugger/gdb_session.h>
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||||
#include <iss/debugger/server.h>
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||||
@ -380,3 +380,4 @@ volatile std::array<bool, 2> dummy = {
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||||
};
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||||
}
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||||
}
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||||
// clang-format on
|
||||
@ -29,7 +29,7 @@
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*******************************************************************************/
|
||||
|
||||
// clang-format off
|
||||
#include <iss/arch/${coreDef.name.toLowerCase()}.h>
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||||
#include <iss/debugger/gdb_session.h>
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||||
#include <iss/debugger/server.h>
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||||
@ -344,3 +344,4 @@ volatile std::array<bool, 2> dummy = {
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||||
};
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||||
}
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||||
}
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||||
// clang-format on
|
||||
@ -30,37 +30,41 @@
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||||
*
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||||
*******************************************************************************/
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||||
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||||
// clang-format off
|
||||
#include "tgc5c.h"
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||||
#include "util/ities.h"
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||||
#include <util/logging.h>
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||||
#include <cstdio>
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||||
#include <cstring>
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||||
#include <fstream>
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||||
#include <util/logging.h>
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||||
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||||
using namespace iss::arch;
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||||
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||||
constexpr std::array<const char*, 36> iss::arch::traits<iss::arch::tgc5c>::reg_names;
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||||
constexpr std::array<const char*, 36> iss::arch::traits<iss::arch::tgc5c>::reg_aliases;
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||||
constexpr std::array<const char*, 36> iss::arch::traits<iss::arch::tgc5c>::reg_names;
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||||
constexpr std::array<const char*, 36> iss::arch::traits<iss::arch::tgc5c>::reg_aliases;
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||||
constexpr std::array<const uint32_t, 43> iss::arch::traits<iss::arch::tgc5c>::reg_bit_widths;
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||||
constexpr std::array<const uint32_t, 43> iss::arch::traits<iss::arch::tgc5c>::reg_byte_offsets;
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||||
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||||
tgc5c::tgc5c() = default;
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tgc5c::tgc5c() = default;
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||||
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tgc5c::~tgc5c() = default;
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||||
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||||
void tgc5c::reset(uint64_t address) {
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auto base_ptr = reinterpret_cast<traits<tgc5c>::reg_t*>(get_regs_base_ptr());
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||||
for(size_t i = 0; i < traits<tgc5c>::NUM_REGS; ++i)
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*(base_ptr + i) = 0;
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reg.PC = address;
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reg.NEXT_PC = reg.PC;
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reg.PRIV = 0x3;
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reg.trap_state = 0;
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reg.icount = 0;
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for(size_t i=0; i<traits<tgc5c>::NUM_REGS; ++i)
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*(base_ptr+i)=0;
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reg.PC=address;
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reg.NEXT_PC=reg.PC;
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reg.PRIV=0x3;
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reg.trap_state=0;
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reg.icount=0;
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||||
}
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||||
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||||
uint8_t* tgc5c::get_regs_base_ptr() { return reinterpret_cast<uint8_t*>(®); }
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||||
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||||
tgc5c::phys_addr_t tgc5c::virt2phys(const iss::addr_t& addr) {
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||||
return phys_addr_t(addr.access, addr.space, addr.val & traits<tgc5c>::addr_mask);
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||||
uint8_t *tgc5c::get_regs_base_ptr() {
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return reinterpret_cast<uint8_t*>(®);
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||||
}
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||||
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||||
tgc5c::phys_addr_t tgc5c::virt2phys(const iss::addr_t &addr) {
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||||
return phys_addr_t(addr.access, addr.space, addr.val&traits<tgc5c>::addr_mask);
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||||
}
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||||
// clang-format on
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||||
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||||
@ -32,7 +32,7 @@
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||||
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||||
#ifndef _TGC5C_H_
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#define _TGC5C_H_
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// clang-format off
|
||||
#include <array>
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||||
#include <iss/arch/traits.h>
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#include <iss/arch_if.h>
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@ -47,95 +47,35 @@ template <> struct traits<tgc5c> {
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||||
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constexpr static char const* const core_type = "TGC5C";
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||||
static constexpr std::array<const char*, 36> reg_names{{"x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8",
|
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"x9", "x10", "x11", "x12", "x13", "x14", "x15", "x16", "x17",
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"x18", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26",
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"x27", "x28", "x29", "x30", "x31", "pc", "next_pc", "priv", "dpc"}};
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static constexpr std::array<const char*, 36> reg_names{
|
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{"x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28", "x29", "x30", "x31", "pc", "next_pc", "priv", "dpc"}};
|
||||
|
||||
static constexpr std::array<const char*, 36> reg_aliases{
|
||||
{"zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", "s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5", "a6", "a7",
|
||||
"s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6", "pc", "next_pc", "priv", "dpc"}};
|
||||
{"zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", "s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5", "a6", "a7", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6", "pc", "next_pc", "priv", "dpc"}};
|
||||
|
||||
enum constants {
|
||||
MISA_VAL = 1073746180ULL,
|
||||
MARCHID_VAL = 2147483651ULL,
|
||||
XLEN = 32ULL,
|
||||
INSTR_ALIGNMENT = 2ULL,
|
||||
RFS = 32ULL,
|
||||
fence = 0ULL,
|
||||
fencei = 1ULL,
|
||||
fencevmal = 2ULL,
|
||||
fencevmau = 3ULL,
|
||||
CSR_SIZE = 4096ULL,
|
||||
MUL_LEN = 64ULL
|
||||
};
|
||||
enum constants {MISA_VAL=1073746180ULL, MARCHID_VAL=2147483651ULL, XLEN=32ULL, INSTR_ALIGNMENT=2ULL, RFS=32ULL, fence=0ULL, fencei=1ULL, fencevmal=2ULL, fencevmau=3ULL, CSR_SIZE=4096ULL, MUL_LEN=64ULL};
|
||||
|
||||
constexpr static unsigned FP_REGS_SIZE = 0;
|
||||
|
||||
enum reg_e {
|
||||
X0,
|
||||
X1,
|
||||
X2,
|
||||
X3,
|
||||
X4,
|
||||
X5,
|
||||
X6,
|
||||
X7,
|
||||
X8,
|
||||
X9,
|
||||
X10,
|
||||
X11,
|
||||
X12,
|
||||
X13,
|
||||
X14,
|
||||
X15,
|
||||
X16,
|
||||
X17,
|
||||
X18,
|
||||
X19,
|
||||
X20,
|
||||
X21,
|
||||
X22,
|
||||
X23,
|
||||
X24,
|
||||
X25,
|
||||
X26,
|
||||
X27,
|
||||
X28,
|
||||
X29,
|
||||
X30,
|
||||
X31,
|
||||
PC,
|
||||
NEXT_PC,
|
||||
PRIV,
|
||||
DPC,
|
||||
NUM_REGS,
|
||||
TRAP_STATE = NUM_REGS,
|
||||
PENDING_TRAP,
|
||||
ICOUNT,
|
||||
CYCLE,
|
||||
INSTRET,
|
||||
INSTRUCTION,
|
||||
LAST_BRANCH
|
||||
X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X12, X13, X14, X15, X16, X17, X18, X19, X20, X21, X22, X23, X24, X25, X26, X27, X28, X29, X30, X31, PC, NEXT_PC, PRIV, DPC, NUM_REGS, TRAP_STATE=NUM_REGS, PENDING_TRAP, ICOUNT, CYCLE, INSTRET, INSTRUCTION, LAST_BRANCH
|
||||
};
|
||||
|
||||
using reg_t = uint32_t;
|
||||
|
||||
using addr_t = uint32_t;
|
||||
|
||||
using code_word_t = uint32_t; // TODO: check removal
|
||||
using code_word_t = uint32_t; //TODO: check removal
|
||||
|
||||
using virt_addr_t = iss::typed_addr_t<iss::address_type::VIRTUAL>;
|
||||
|
||||
using phys_addr_t = iss::typed_addr_t<iss::address_type::PHYSICAL>;
|
||||
|
||||
static constexpr std::array<const uint32_t, 43> reg_bit_widths{{32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32,
|
||||
32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32,
|
||||
32, 32, 32, 32, 8, 32, 32, 32, 64, 64, 64, 32, 32}};
|
||||
static constexpr std::array<const uint32_t, 43> reg_bit_widths{
|
||||
{32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,8,32,32,32,64,64,64,32,32}};
|
||||
|
||||
static constexpr std::array<const uint32_t, 43> reg_byte_offsets{
|
||||
{0, 4, 8, 12, 16, 20, 24, 28, 32, 36, 40, 44, 48, 52, 56, 60, 64, 68, 72, 76, 80, 84,
|
||||
88, 92, 96, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 137, 141, 145, 149, 157, 165, 173, 177}};
|
||||
{0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,137,141,145,149,157,165,173,177}};
|
||||
|
||||
static const uint64_t addr_mask = (reg_t(1) << (XLEN - 1)) | ((reg_t(1) << (XLEN - 1)) - 1);
|
||||
|
||||
@ -235,17 +175,17 @@ template <> struct traits<tgc5c> {
|
||||
};
|
||||
};
|
||||
|
||||
struct tgc5c : public arch_if {
|
||||
struct tgc5c: public arch_if {
|
||||
|
||||
using virt_addr_t = typename traits<tgc5c>::virt_addr_t;
|
||||
using phys_addr_t = typename traits<tgc5c>::phys_addr_t;
|
||||
using reg_t = typename traits<tgc5c>::reg_t;
|
||||
using reg_t = typename traits<tgc5c>::reg_t;
|
||||
using addr_t = typename traits<tgc5c>::addr_t;
|
||||
|
||||
tgc5c();
|
||||
~tgc5c();
|
||||
|
||||
void reset(uint64_t address = 0) override;
|
||||
void reset(uint64_t address=0) override;
|
||||
|
||||
uint8_t* get_regs_base_ptr() override;
|
||||
|
||||
@ -261,6 +201,7 @@ struct tgc5c : public arch_if {
|
||||
|
||||
inline uint32_t get_last_branch() { return reg.last_branch; }
|
||||
|
||||
|
||||
#pragma pack(push, 1)
|
||||
struct TGC5C_regs {
|
||||
uint32_t X0 = 0;
|
||||
@ -309,12 +250,14 @@ struct tgc5c : public arch_if {
|
||||
#pragma pack(pop)
|
||||
std::array<address_type, 4> addr_mode;
|
||||
|
||||
uint64_t interrupt_sim = 0;
|
||||
uint64_t interrupt_sim=0;
|
||||
|
||||
uint32_t get_fcsr(){return 0;}
|
||||
void set_fcsr(uint32_t val){}
|
||||
|
||||
uint32_t get_fcsr() { return 0; }
|
||||
void set_fcsr(uint32_t val) {}
|
||||
};
|
||||
|
||||
} // namespace arch
|
||||
} // namespace iss
|
||||
}
|
||||
}
|
||||
#endif /* _TGC5C_H_ */
|
||||
// clang-format on
|
||||
|
||||
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