DBT-RISE/DBT-RISE-TGC
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base: DBT-RISE:438e598a4aaf287298596e3ceb6609ee36818fee
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DBT-RISE:main DBT-RISE:develop DBT-RISE:featture/interp_instr_cache DBT-RISE:feature/privilege_refactor DBT-RISE:feature/htif DBT-RISE:feature/eve_checkin DBT-RISE:feature/iss_factory DBT-RISE:feature/core_factory DBT-RISE:Trace_enhancement DBT-RISE:feature/reduced_output DBT-RISE:msvc_compat DBT-RISE:hotfix/latest_scc DBT-RISE:feature/interpreter
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compare: DBT-RISE:17ee7b138d0a5ef8e182d71c5a1dd2dd273034ea
Branches Tags
DBT-RISE:develop DBT-RISE:featture/interp_instr_cache DBT-RISE:feature/privilege_refactor DBT-RISE:feature/htif DBT-RISE:feature/eve_checkin DBT-RISE:main DBT-RISE:feature/iss_factory DBT-RISE:feature/core_factory DBT-RISE:Trace_enhancement DBT-RISE:feature/reduced_output DBT-RISE:msvc_compat DBT-RISE:hotfix/latest_scc DBT-RISE:feature/interpreter

2 Commits
438e598a4a ... 17ee7b138d

Author SHA1 Message Date
Eyck Jentzsch
17ee7b138d update generated TGC-C VM 2021-09-29 00:44:17 +02:00
Eyck Jentzsch
aa84a27a5b fix JALR alignment in description 2021-09-29 00:43:42 +02:00
2 changed files with 2 additions and 2 deletions
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2
gen_input/CoreDSL-Instruction-Set-Description

Submodule gen_input/CoreDSL-Instruction-Set-Description updated: 89dabd00e3...9e3119a806

2
src/vm/interp/vm_tgc_c.cpp
View File

@ -517,7 +517,7 @@ private:
// execute instruction // execute instruction
try { try {
{ {
int32_t new_pc = *(X+rs1) + (int16_t)sext<12>(imm); int32_t new_pc = (*(X+rs1) + (int16_t)sext<12>(imm)) & ~ 1;
if(new_pc % traits::INSTR_ALIGNMENT) { if(new_pc % traits::INSTR_ALIGNMENT) {
raise(0, 0); raise(0, 0);
} }