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No commits in common. "37db31fb4b4cd9b1b633ce0834a7cd2e4d71a106" and "a6c48ceaacedafd858ea287bd6ea6fefbb590714" have entirely different histories.
37db31fb4b
...
a6c48ceaac
@ -1,4 +1,4 @@
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cmake_minimum_required(VERSION 3.18)
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cmake_minimum_required(VERSION 3.12)
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list(APPEND CMAKE_MODULE_PATH ${CMAKE_CURRENT_SOURCE_DIR}/cmake)
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list(APPEND CMAKE_MODULE_PATH ${CMAKE_CURRENT_SOURCE_DIR}/cmake)
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# ##############################################################################
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# ##############################################################################
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@ -373,7 +373,7 @@ volatile std::array<bool, 2> dummy = {
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auto vm = new llvm::${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*cpu, false);
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auto vm = new llvm::${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*cpu, false);
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if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
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if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
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if(init_data){
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if(init_data){
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auto* cb = reinterpret_cast<std::function<void(arch_if*, arch::traits<arch::${coreDef.name.toLowerCase()}>::reg_t*, arch::traits<arch::${coreDef.name.toLowerCase()}>::reg_t*)>*>(init_data);
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auto* cb = reinterpret_cast<std::function<void(arch_if*, arch::traits<arch::${coreDef.name.toLowerCase()}>::reg_t, arch::traits<arch::${coreDef.name.toLowerCase()}>::reg_t)>*>(init_data);
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cpu->set_semihosting_callback(*cb);
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cpu->set_semihosting_callback(*cb);
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}
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}
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return {cpu_ptr{cpu}, vm_ptr{vm}};
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return {cpu_ptr{cpu}, vm_ptr{vm}};
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@ -383,7 +383,7 @@ volatile std::array<bool, 2> dummy = {
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auto vm = new llvm::${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*cpu, false);
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auto vm = new llvm::${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*cpu, false);
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if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
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if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
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if(init_data){
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if(init_data){
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auto* cb = reinterpret_cast<std::function<void(arch_if*, arch::traits<arch::${coreDef.name.toLowerCase()}>::reg_t*, arch::traits<arch::${coreDef.name.toLowerCase()}>::reg_t*)>*>(init_data);
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auto* cb = reinterpret_cast<std::function<void(arch_if*, arch::traits<arch::${coreDef.name.toLowerCase()}>::reg_t, arch::traits<arch::${coreDef.name.toLowerCase()}>::reg_t)>*>(init_data);
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cpu->set_semihosting_callback(*cb);
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cpu->set_semihosting_callback(*cb);
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}
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}
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return {cpu_ptr{cpu}, vm_ptr{vm}};
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return {cpu_ptr{cpu}, vm_ptr{vm}};
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@ -1125,6 +1125,9 @@ iss::status riscv_hart_m_p<BASE, FEAT>::write_mem(phys_addr_t paddr, unsigned le
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}
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}
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this->reg.trap_state = std::numeric_limits<uint32_t>::max();
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this->reg.trap_state = std::numeric_limits<uint32_t>::max();
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this->interrupt_sim = hostvar;
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this->interrupt_sim = hostvar;
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#ifndef WITH_TCC
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// throw(iss::simulation_stopped(hostvar));
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#endif
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break;
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break;
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case 0x0101: {
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case 0x0101: {
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char c = static_cast<char>(hostvar & 0xff);
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char c = static_cast<char>(hostvar & 0xff);
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@ -4722,7 +4722,7 @@ volatile std::array<bool, 2> dummy = {
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auto vm = new llvm::tgc5c::vm_impl<arch::tgc5c>(*cpu, false);
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auto vm = new llvm::tgc5c::vm_impl<arch::tgc5c>(*cpu, false);
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if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
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if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
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if(init_data){
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if(init_data){
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auto* cb = reinterpret_cast<std::function<void(arch_if*, arch::traits<arch::tgc5c>::reg_t*, arch::traits<arch::tgc5c>::reg_t*)>*>(init_data);
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auto* cb = reinterpret_cast<std::function<void(arch_if*, arch::traits<arch::tgc5c>::reg_t, arch::traits<arch::tgc5c>::reg_t)>*>(init_data);
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cpu->set_semihosting_callback(*cb);
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cpu->set_semihosting_callback(*cb);
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}
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}
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return {cpu_ptr{cpu}, vm_ptr{vm}};
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return {cpu_ptr{cpu}, vm_ptr{vm}};
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@ -4732,7 +4732,7 @@ volatile std::array<bool, 2> dummy = {
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auto vm = new llvm::tgc5c::vm_impl<arch::tgc5c>(*cpu, false);
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auto vm = new llvm::tgc5c::vm_impl<arch::tgc5c>(*cpu, false);
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if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
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if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
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if(init_data){
|
if(init_data){
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auto* cb = reinterpret_cast<std::function<void(arch_if*, arch::traits<arch::tgc5c>::reg_t*, arch::traits<arch::tgc5c>::reg_t*)>*>(init_data);
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auto* cb = reinterpret_cast<std::function<void(arch_if*, arch::traits<arch::tgc5c>::reg_t, arch::traits<arch::tgc5c>::reg_t)>*>(init_data);
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cpu->set_semihosting_callback(*cb);
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cpu->set_semihosting_callback(*cb);
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}
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}
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return {cpu_ptr{cpu}, vm_ptr{vm}};
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return {cpu_ptr{cpu}, vm_ptr{vm}};
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70
src_test/iss/arch/tgc5a.cpp
Normal file
70
src_test/iss/arch/tgc5a.cpp
Normal file
@ -0,0 +1,70 @@
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|
/*******************************************************************************
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* Copyright (C) 2017 - 2020 MINRES Technologies GmbH
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* All rights reserved.
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||||||
|
*
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|
* Redistribution and use in source and binary forms, with or without
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|
* modification, are permitted provided that the following conditions are met:
|
||||||
|
*
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
*
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||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
*
|
||||||
|
* 3. Neither the name of the copyright holder nor the names of its contributors
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||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||||
|
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
|
||||||
|
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||||
|
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||||
|
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||||
|
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||||
|
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||||
|
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
* POSSIBILITY OF SUCH DAMAGE.
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||||||
|
*
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||||||
|
*******************************************************************************/
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// clang-format off
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#include "tgc5a.h"
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#include "util/ities.h"
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#include <util/logging.h>
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#include <cstdio>
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#include <cstring>
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#include <fstream>
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using namespace iss::arch;
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constexpr std::array<const char*, 20> iss::arch::traits<iss::arch::tgc5a>::reg_names;
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constexpr std::array<const char*, 20> iss::arch::traits<iss::arch::tgc5a>::reg_aliases;
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constexpr std::array<const uint32_t, 27> iss::arch::traits<iss::arch::tgc5a>::reg_bit_widths;
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constexpr std::array<const uint32_t, 27> iss::arch::traits<iss::arch::tgc5a>::reg_byte_offsets;
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tgc5a::tgc5a() = default;
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tgc5a::~tgc5a() = default;
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void tgc5a::reset(uint64_t address) {
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auto base_ptr = reinterpret_cast<traits<tgc5a>::reg_t*>(get_regs_base_ptr());
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for(size_t i=0; i<traits<tgc5a>::NUM_REGS; ++i)
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*(base_ptr+i)=0;
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reg.PC=address;
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reg.NEXT_PC=reg.PC;
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reg.PRIV=0x3;
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reg.trap_state=0;
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reg.icount=0;
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}
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uint8_t *tgc5a::get_regs_base_ptr() {
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return reinterpret_cast<uint8_t*>(®);
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}
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tgc5a::phys_addr_t tgc5a::virt2phys(const iss::addr_t &addr) {
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return phys_addr_t(addr.access, addr.space, addr.val&traits<tgc5a>::addr_mask);
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}
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// clang-format on
|
209
src_test/iss/arch/tgc5a.h
Normal file
209
src_test/iss/arch/tgc5a.h
Normal file
@ -0,0 +1,209 @@
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|||||||
|
/*******************************************************************************
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||||||
|
* Copyright (C) 2017 - 2021 MINRES Technologies GmbH
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||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions are met:
|
||||||
|
*
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
*
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
*
|
||||||
|
* 3. Neither the name of the copyright holder nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||||
|
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
|
||||||
|
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||||
|
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||||
|
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||||
|
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||||
|
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||||
|
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
* POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*
|
||||||
|
*******************************************************************************/
|
||||||
|
|
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|
#ifndef _TGC5A_H_
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#define _TGC5A_H_
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// clang-format off
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#include <array>
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#include <iss/arch/traits.h>
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#include <iss/arch_if.h>
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#include <iss/vm_if.h>
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|
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|
namespace iss {
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|
namespace arch {
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|
|
||||||
|
struct tgc5a;
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|
|
||||||
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template <> struct traits<tgc5a> {
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|
|
||||||
|
constexpr static char const* const core_type = "TGC5A";
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|
|
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|
static constexpr std::array<const char*, 20> reg_names{
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|
{"x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", "pc", "next_pc", "priv", "dpc"}};
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||||||
|
|
||||||
|
static constexpr std::array<const char*, 20> reg_aliases{
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|
{"zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", "s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5", "pc", "next_pc", "priv", "dpc"}};
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|
|
||||||
|
enum constants {MISA_VAL=1073741840ULL, MARCHID_VAL=2147483649ULL, CLIC_NUM_IRQ=0ULL, XLEN=32ULL, INSTR_ALIGNMENT=4ULL, RFS=16ULL, fence=0ULL, fencei=1ULL, fencevmal=2ULL, fencevmau=3ULL, CSR_SIZE=4096ULL};
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|
|
||||||
|
constexpr static unsigned FP_REGS_SIZE = 0;
|
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|
|
||||||
|
enum reg_e {
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|
X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X12, X13, X14, X15, PC, NEXT_PC, PRIV, DPC, NUM_REGS, TRAP_STATE=NUM_REGS, PENDING_TRAP, ICOUNT, CYCLE, INSTRET, INSTRUCTION, LAST_BRANCH
|
||||||
|
};
|
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|
|
||||||
|
using reg_t = uint32_t;
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|
|
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|
using addr_t = uint32_t;
|
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|
|
||||||
|
using code_word_t = uint32_t; //TODO: check removal
|
||||||
|
|
||||||
|
using virt_addr_t = iss::typed_addr_t<iss::address_type::VIRTUAL>;
|
||||||
|
|
||||||
|
using phys_addr_t = iss::typed_addr_t<iss::address_type::PHYSICAL>;
|
||||||
|
|
||||||
|
static constexpr std::array<const uint32_t, 27> reg_bit_widths{
|
||||||
|
{32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,8,32,32,32,64,64,64,32,32}};
|
||||||
|
|
||||||
|
static constexpr std::array<const uint32_t, 27> reg_byte_offsets{
|
||||||
|
{0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,73,77,81,85,93,101,109,113}};
|
||||||
|
|
||||||
|
static const uint64_t addr_mask = (reg_t(1) << (XLEN - 1)) | ((reg_t(1) << (XLEN - 1)) - 1);
|
||||||
|
|
||||||
|
enum sreg_flag_e { FLAGS };
|
||||||
|
|
||||||
|
enum mem_type_e { MEM, FENCE, RES, CSR };
|
||||||
|
|
||||||
|
enum class opcode_e {
|
||||||
|
LUI = 0,
|
||||||
|
AUIPC = 1,
|
||||||
|
JAL = 2,
|
||||||
|
JALR = 3,
|
||||||
|
BEQ = 4,
|
||||||
|
BNE = 5,
|
||||||
|
BLT = 6,
|
||||||
|
BGE = 7,
|
||||||
|
BLTU = 8,
|
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|
BGEU = 9,
|
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|
LB = 10,
|
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|
LH = 11,
|
||||||
|
LW = 12,
|
||||||
|
LBU = 13,
|
||||||
|
LHU = 14,
|
||||||
|
SB = 15,
|
||||||
|
SH = 16,
|
||||||
|
SW = 17,
|
||||||
|
ADDI = 18,
|
||||||
|
SLTI = 19,
|
||||||
|
SLTIU = 20,
|
||||||
|
XORI = 21,
|
||||||
|
ORI = 22,
|
||||||
|
ANDI = 23,
|
||||||
|
SLLI = 24,
|
||||||
|
SRLI = 25,
|
||||||
|
SRAI = 26,
|
||||||
|
ADD = 27,
|
||||||
|
SUB = 28,
|
||||||
|
SLL = 29,
|
||||||
|
SLT = 30,
|
||||||
|
SLTU = 31,
|
||||||
|
XOR = 32,
|
||||||
|
SRL = 33,
|
||||||
|
SRA = 34,
|
||||||
|
OR = 35,
|
||||||
|
AND = 36,
|
||||||
|
FENCE = 37,
|
||||||
|
ECALL = 38,
|
||||||
|
EBREAK = 39,
|
||||||
|
MRET = 40,
|
||||||
|
WFI = 41,
|
||||||
|
CSRRW = 42,
|
||||||
|
CSRRS = 43,
|
||||||
|
CSRRC = 44,
|
||||||
|
CSRRWI = 45,
|
||||||
|
CSRRSI = 46,
|
||||||
|
CSRRCI = 47,
|
||||||
|
FENCE_I = 48,
|
||||||
|
MAX_OPCODE
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
struct tgc5a: public arch_if {
|
||||||
|
|
||||||
|
using virt_addr_t = typename traits<tgc5a>::virt_addr_t;
|
||||||
|
using phys_addr_t = typename traits<tgc5a>::phys_addr_t;
|
||||||
|
using reg_t = typename traits<tgc5a>::reg_t;
|
||||||
|
using addr_t = typename traits<tgc5a>::addr_t;
|
||||||
|
|
||||||
|
tgc5a();
|
||||||
|
~tgc5a();
|
||||||
|
|
||||||
|
void reset(uint64_t address=0) override;
|
||||||
|
|
||||||
|
uint8_t* get_regs_base_ptr() override;
|
||||||
|
|
||||||
|
inline uint64_t get_icount() { return reg.icount; }
|
||||||
|
|
||||||
|
inline bool should_stop() { return interrupt_sim; }
|
||||||
|
|
||||||
|
inline uint64_t stop_code() { return interrupt_sim; }
|
||||||
|
|
||||||
|
virtual phys_addr_t virt2phys(const iss::addr_t& addr);
|
||||||
|
|
||||||
|
virtual iss::sync_type needed_sync() const { return iss::NO_SYNC; }
|
||||||
|
|
||||||
|
inline uint32_t get_last_branch() { return reg.last_branch; }
|
||||||
|
|
||||||
|
|
||||||
|
#pragma pack(push, 1)
|
||||||
|
struct TGC5A_regs {
|
||||||
|
uint32_t X0 = 0;
|
||||||
|
uint32_t X1 = 0;
|
||||||
|
uint32_t X2 = 0;
|
||||||
|
uint32_t X3 = 0;
|
||||||
|
uint32_t X4 = 0;
|
||||||
|
uint32_t X5 = 0;
|
||||||
|
uint32_t X6 = 0;
|
||||||
|
uint32_t X7 = 0;
|
||||||
|
uint32_t X8 = 0;
|
||||||
|
uint32_t X9 = 0;
|
||||||
|
uint32_t X10 = 0;
|
||||||
|
uint32_t X11 = 0;
|
||||||
|
uint32_t X12 = 0;
|
||||||
|
uint32_t X13 = 0;
|
||||||
|
uint32_t X14 = 0;
|
||||||
|
uint32_t X15 = 0;
|
||||||
|
uint32_t PC = 0;
|
||||||
|
uint32_t NEXT_PC = 0;
|
||||||
|
uint8_t PRIV = 0;
|
||||||
|
uint32_t DPC = 0;
|
||||||
|
uint32_t trap_state = 0, pending_trap = 0;
|
||||||
|
uint64_t icount = 0;
|
||||||
|
uint64_t cycle = 0;
|
||||||
|
uint64_t instret = 0;
|
||||||
|
uint32_t instruction = 0;
|
||||||
|
uint32_t last_branch = 0;
|
||||||
|
} reg;
|
||||||
|
#pragma pack(pop)
|
||||||
|
std::array<address_type, 4> addr_mode;
|
||||||
|
|
||||||
|
uint64_t interrupt_sim=0;
|
||||||
|
|
||||||
|
uint32_t get_fcsr(){return 0;}
|
||||||
|
void set_fcsr(uint32_t val){}
|
||||||
|
|
||||||
|
};
|
||||||
|
|
||||||
|
}
|
||||||
|
}
|
||||||
|
#endif /* _TGC5A_H_ */
|
||||||
|
// clang-format on
|
70
src_test/iss/arch/tgc5b.cpp
Normal file
70
src_test/iss/arch/tgc5b.cpp
Normal file
@ -0,0 +1,70 @@
|
|||||||
|
/*******************************************************************************
|
||||||
|
* Copyright (C) 2017 - 2020 MINRES Technologies GmbH
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions are met:
|
||||||
|
*
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
*
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
*
|
||||||
|
* 3. Neither the name of the copyright holder nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||||
|
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
|
||||||
|
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||||
|
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||||
|
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||||
|
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||||
|
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||||
|
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
* POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*
|
||||||
|
*******************************************************************************/
|
||||||
|
|
||||||
|
// clang-format off
|
||||||
|
#include "tgc5b.h"
|
||||||
|
#include "util/ities.h"
|
||||||
|
#include <util/logging.h>
|
||||||
|
#include <cstdio>
|
||||||
|
#include <cstring>
|
||||||
|
#include <fstream>
|
||||||
|
|
||||||
|
using namespace iss::arch;
|
||||||
|
|
||||||
|
constexpr std::array<const char*, 36> iss::arch::traits<iss::arch::tgc5b>::reg_names;
|
||||||
|
constexpr std::array<const char*, 36> iss::arch::traits<iss::arch::tgc5b>::reg_aliases;
|
||||||
|
constexpr std::array<const uint32_t, 43> iss::arch::traits<iss::arch::tgc5b>::reg_bit_widths;
|
||||||
|
constexpr std::array<const uint32_t, 43> iss::arch::traits<iss::arch::tgc5b>::reg_byte_offsets;
|
||||||
|
|
||||||
|
tgc5b::tgc5b() = default;
|
||||||
|
|
||||||
|
tgc5b::~tgc5b() = default;
|
||||||
|
|
||||||
|
void tgc5b::reset(uint64_t address) {
|
||||||
|
auto base_ptr = reinterpret_cast<traits<tgc5b>::reg_t*>(get_regs_base_ptr());
|
||||||
|
for(size_t i=0; i<traits<tgc5b>::NUM_REGS; ++i)
|
||||||
|
*(base_ptr+i)=0;
|
||||||
|
reg.PC=address;
|
||||||
|
reg.NEXT_PC=reg.PC;
|
||||||
|
reg.PRIV=0x3;
|
||||||
|
reg.trap_state=0;
|
||||||
|
reg.icount=0;
|
||||||
|
}
|
||||||
|
|
||||||
|
uint8_t *tgc5b::get_regs_base_ptr() {
|
||||||
|
return reinterpret_cast<uint8_t*>(®);
|
||||||
|
}
|
||||||
|
|
||||||
|
tgc5b::phys_addr_t tgc5b::virt2phys(const iss::addr_t &addr) {
|
||||||
|
return phys_addr_t(addr.access, addr.space, addr.val&traits<tgc5b>::addr_mask);
|
||||||
|
}
|
||||||
|
// clang-format on
|
225
src_test/iss/arch/tgc5b.h
Normal file
225
src_test/iss/arch/tgc5b.h
Normal file
@ -0,0 +1,225 @@
|
|||||||
|
/*******************************************************************************
|
||||||
|
* Copyright (C) 2017 - 2021 MINRES Technologies GmbH
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions are met:
|
||||||
|
*
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
*
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
*
|
||||||
|
* 3. Neither the name of the copyright holder nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||||
|
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
|
||||||
|
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||||
|
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||||
|
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||||
|
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||||
|
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||||
|
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
* POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*
|
||||||
|
*******************************************************************************/
|
||||||
|
|
||||||
|
#ifndef _TGC5B_H_
|
||||||
|
#define _TGC5B_H_
|
||||||
|
// clang-format off
|
||||||
|
#include <array>
|
||||||
|
#include <iss/arch/traits.h>
|
||||||
|
#include <iss/arch_if.h>
|
||||||
|
#include <iss/vm_if.h>
|
||||||
|
|
||||||
|
namespace iss {
|
||||||
|
namespace arch {
|
||||||
|
|
||||||
|
struct tgc5b;
|
||||||
|
|
||||||
|
template <> struct traits<tgc5b> {
|
||||||
|
|
||||||
|
constexpr static char const* const core_type = "TGC5B";
|
||||||
|
|
||||||
|
static constexpr std::array<const char*, 36> reg_names{
|
||||||
|
{"x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28", "x29", "x30", "x31", "pc", "next_pc", "priv", "dpc"}};
|
||||||
|
|
||||||
|
static constexpr std::array<const char*, 36> reg_aliases{
|
||||||
|
{"zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", "s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5", "a6", "a7", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6", "pc", "next_pc", "priv", "dpc"}};
|
||||||
|
|
||||||
|
enum constants {MISA_VAL=1073742080ULL, MARCHID_VAL=2147483650ULL, CLIC_NUM_IRQ=0ULL, XLEN=32ULL, INSTR_ALIGNMENT=4ULL, RFS=32ULL, fence=0ULL, fencei=1ULL, fencevmal=2ULL, fencevmau=3ULL, CSR_SIZE=4096ULL};
|
||||||
|
|
||||||
|
constexpr static unsigned FP_REGS_SIZE = 0;
|
||||||
|
|
||||||
|
enum reg_e {
|
||||||
|
X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X12, X13, X14, X15, X16, X17, X18, X19, X20, X21, X22, X23, X24, X25, X26, X27, X28, X29, X30, X31, PC, NEXT_PC, PRIV, DPC, NUM_REGS, TRAP_STATE=NUM_REGS, PENDING_TRAP, ICOUNT, CYCLE, INSTRET, INSTRUCTION, LAST_BRANCH
|
||||||
|
};
|
||||||
|
|
||||||
|
using reg_t = uint32_t;
|
||||||
|
|
||||||
|
using addr_t = uint32_t;
|
||||||
|
|
||||||
|
using code_word_t = uint32_t; //TODO: check removal
|
||||||
|
|
||||||
|
using virt_addr_t = iss::typed_addr_t<iss::address_type::VIRTUAL>;
|
||||||
|
|
||||||
|
using phys_addr_t = iss::typed_addr_t<iss::address_type::PHYSICAL>;
|
||||||
|
|
||||||
|
static constexpr std::array<const uint32_t, 43> reg_bit_widths{
|
||||||
|
{32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,8,32,32,32,64,64,64,32,32}};
|
||||||
|
|
||||||
|
static constexpr std::array<const uint32_t, 43> reg_byte_offsets{
|
||||||
|
{0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,137,141,145,149,157,165,173,177}};
|
||||||
|
|
||||||
|
static const uint64_t addr_mask = (reg_t(1) << (XLEN - 1)) | ((reg_t(1) << (XLEN - 1)) - 1);
|
||||||
|
|
||||||
|
enum sreg_flag_e { FLAGS };
|
||||||
|
|
||||||
|
enum mem_type_e { MEM, FENCE, RES, CSR };
|
||||||
|
|
||||||
|
enum class opcode_e {
|
||||||
|
LUI = 0,
|
||||||
|
AUIPC = 1,
|
||||||
|
JAL = 2,
|
||||||
|
JALR = 3,
|
||||||
|
BEQ = 4,
|
||||||
|
BNE = 5,
|
||||||
|
BLT = 6,
|
||||||
|
BGE = 7,
|
||||||
|
BLTU = 8,
|
||||||
|
BGEU = 9,
|
||||||
|
LB = 10,
|
||||||
|
LH = 11,
|
||||||
|
LW = 12,
|
||||||
|
LBU = 13,
|
||||||
|
LHU = 14,
|
||||||
|
SB = 15,
|
||||||
|
SH = 16,
|
||||||
|
SW = 17,
|
||||||
|
ADDI = 18,
|
||||||
|
SLTI = 19,
|
||||||
|
SLTIU = 20,
|
||||||
|
XORI = 21,
|
||||||
|
ORI = 22,
|
||||||
|
ANDI = 23,
|
||||||
|
SLLI = 24,
|
||||||
|
SRLI = 25,
|
||||||
|
SRAI = 26,
|
||||||
|
ADD = 27,
|
||||||
|
SUB = 28,
|
||||||
|
SLL = 29,
|
||||||
|
SLT = 30,
|
||||||
|
SLTU = 31,
|
||||||
|
XOR = 32,
|
||||||
|
SRL = 33,
|
||||||
|
SRA = 34,
|
||||||
|
OR = 35,
|
||||||
|
AND = 36,
|
||||||
|
FENCE = 37,
|
||||||
|
ECALL = 38,
|
||||||
|
EBREAK = 39,
|
||||||
|
MRET = 40,
|
||||||
|
WFI = 41,
|
||||||
|
CSRRW = 42,
|
||||||
|
CSRRS = 43,
|
||||||
|
CSRRC = 44,
|
||||||
|
CSRRWI = 45,
|
||||||
|
CSRRSI = 46,
|
||||||
|
CSRRCI = 47,
|
||||||
|
FENCE_I = 48,
|
||||||
|
MAX_OPCODE
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
struct tgc5b: public arch_if {
|
||||||
|
|
||||||
|
using virt_addr_t = typename traits<tgc5b>::virt_addr_t;
|
||||||
|
using phys_addr_t = typename traits<tgc5b>::phys_addr_t;
|
||||||
|
using reg_t = typename traits<tgc5b>::reg_t;
|
||||||
|
using addr_t = typename traits<tgc5b>::addr_t;
|
||||||
|
|
||||||
|
tgc5b();
|
||||||
|
~tgc5b();
|
||||||
|
|
||||||
|
void reset(uint64_t address=0) override;
|
||||||
|
|
||||||
|
uint8_t* get_regs_base_ptr() override;
|
||||||
|
|
||||||
|
inline uint64_t get_icount() { return reg.icount; }
|
||||||
|
|
||||||
|
inline bool should_stop() { return interrupt_sim; }
|
||||||
|
|
||||||
|
inline uint64_t stop_code() { return interrupt_sim; }
|
||||||
|
|
||||||
|
virtual phys_addr_t virt2phys(const iss::addr_t& addr);
|
||||||
|
|
||||||
|
virtual iss::sync_type needed_sync() const { return iss::NO_SYNC; }
|
||||||
|
|
||||||
|
inline uint32_t get_last_branch() { return reg.last_branch; }
|
||||||
|
|
||||||
|
|
||||||
|
#pragma pack(push, 1)
|
||||||
|
struct TGC5B_regs {
|
||||||
|
uint32_t X0 = 0;
|
||||||
|
uint32_t X1 = 0;
|
||||||
|
uint32_t X2 = 0;
|
||||||
|
uint32_t X3 = 0;
|
||||||
|
uint32_t X4 = 0;
|
||||||
|
uint32_t X5 = 0;
|
||||||
|
uint32_t X6 = 0;
|
||||||
|
uint32_t X7 = 0;
|
||||||
|
uint32_t X8 = 0;
|
||||||
|
uint32_t X9 = 0;
|
||||||
|
uint32_t X10 = 0;
|
||||||
|
uint32_t X11 = 0;
|
||||||
|
uint32_t X12 = 0;
|
||||||
|
uint32_t X13 = 0;
|
||||||
|
uint32_t X14 = 0;
|
||||||
|
uint32_t X15 = 0;
|
||||||
|
uint32_t X16 = 0;
|
||||||
|
uint32_t X17 = 0;
|
||||||
|
uint32_t X18 = 0;
|
||||||
|
uint32_t X19 = 0;
|
||||||
|
uint32_t X20 = 0;
|
||||||
|
uint32_t X21 = 0;
|
||||||
|
uint32_t X22 = 0;
|
||||||
|
uint32_t X23 = 0;
|
||||||
|
uint32_t X24 = 0;
|
||||||
|
uint32_t X25 = 0;
|
||||||
|
uint32_t X26 = 0;
|
||||||
|
uint32_t X27 = 0;
|
||||||
|
uint32_t X28 = 0;
|
||||||
|
uint32_t X29 = 0;
|
||||||
|
uint32_t X30 = 0;
|
||||||
|
uint32_t X31 = 0;
|
||||||
|
uint32_t PC = 0;
|
||||||
|
uint32_t NEXT_PC = 0;
|
||||||
|
uint8_t PRIV = 0;
|
||||||
|
uint32_t DPC = 0;
|
||||||
|
uint32_t trap_state = 0, pending_trap = 0;
|
||||||
|
uint64_t icount = 0;
|
||||||
|
uint64_t cycle = 0;
|
||||||
|
uint64_t instret = 0;
|
||||||
|
uint32_t instruction = 0;
|
||||||
|
uint32_t last_branch = 0;
|
||||||
|
} reg;
|
||||||
|
#pragma pack(pop)
|
||||||
|
std::array<address_type, 4> addr_mode;
|
||||||
|
|
||||||
|
uint64_t interrupt_sim=0;
|
||||||
|
|
||||||
|
uint32_t get_fcsr(){return 0;}
|
||||||
|
void set_fcsr(uint32_t val){}
|
||||||
|
|
||||||
|
};
|
||||||
|
|
||||||
|
}
|
||||||
|
}
|
||||||
|
#endif /* _TGC5B_H_ */
|
||||||
|
// clang-format on
|
1776
src_test/vm/interp/vm_tgc5a.cpp
Normal file
1776
src_test/vm/interp/vm_tgc5a.cpp
Normal file
File diff suppressed because it is too large
Load Diff
1776
src_test/vm/interp/vm_tgc5b.cpp
Normal file
1776
src_test/vm/interp/vm_tgc5b.cpp
Normal file
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue
Block a user