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base: DBT-RISE:34bb8e62aeed221741d186e019778f97e42e6d12
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DBT-RISE:main DBT-RISE:develop DBT-RISE:featture/interp_instr_cache DBT-RISE:feature/privilege_refactor DBT-RISE:feature/htif DBT-RISE:feature/eve_checkin DBT-RISE:feature/iss_factory DBT-RISE:feature/core_factory DBT-RISE:Trace_enhancement DBT-RISE:feature/reduced_output DBT-RISE:msvc_compat DBT-RISE:hotfix/latest_scc DBT-RISE:feature/interpreter
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compare: DBT-RISE:3261055871c646a4b47594db242a8634f1148511
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DBT-RISE:develop DBT-RISE:featture/interp_instr_cache DBT-RISE:feature/privilege_refactor DBT-RISE:feature/htif DBT-RISE:feature/eve_checkin DBT-RISE:main DBT-RISE:feature/iss_factory DBT-RISE:feature/core_factory DBT-RISE:Trace_enhancement DBT-RISE:feature/reduced_output DBT-RISE:msvc_compat DBT-RISE:hotfix/latest_scc DBT-RISE:feature/interpreter

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34bb8e62ae ... 3261055871

Author SHA1 Message Date
Eyck Jentzsch
3261055871 update description to latest CoreDSL2 2021-02-15 11:35:56 +00:00
2 changed files with 3 additions and 3 deletions
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2
gen_input/CoreDSL-Instruction-Set-Description

Submodule gen_input/CoreDSL-Instruction-Set-Description updated: 998444fba8...919a3c8611

4
gen_input/TGFS.core_desc
View File

@ -3,7 +3,7 @@ import "CoreDSL-Instruction-Set-Description/RVM.core_desc"
import "CoreDSL-Instruction-Set-Description/RVC.core_desc"
Core TGF_B provides RV32I {
constants {
architectural_state {
unsigned XLEN=32;
unsigned PCLEN=32;
// definitions for the architecture wrapper
@ -15,7 +15,7 @@ Core TGF_B provides RV32I {
}
Core TGF_C provides RV32I, RV32M, RV32IC {
constants {
architectural_state {
unsigned XLEN=32;
unsigned PCLEN=32;
// definitions for the architecture wrapper