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DBT-RISE-TGC
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base: DBT-RISE:2b094c31620e5108a35e45d81582d56e8f2c9153
Branches Tags
DBT-RISE:main
DBT-RISE:develop
DBT-RISE:feature/iss_factory
DBT-RISE:feature/core_factory
DBT-RISE:Trace_enhancement
DBT-RISE:feature/reduced_output
DBT-RISE:msvc_compat
DBT-RISE:hotfix/latest_scc
DBT-RISE:feature/interpreter
...
compare: DBT-RISE:7b31b8ca8ef48a7614eb21008d764e3003c82795
Branches Tags
DBT-RISE:develop
DBT-RISE:main
DBT-RISE:feature/iss_factory
DBT-RISE:feature/core_factory
DBT-RISE:Trace_enhancement
DBT-RISE:feature/reduced_output
DBT-RISE:msvc_compat
DBT-RISE:hotfix/latest_scc
DBT-RISE:feature/interpreter

7 Commits
2b094c3162 ... 7b31b8ca8e

Author SHA1 Message Date
Eyck-Alexander Jentzsch 7b31b8ca8e adds updated generated files 2023-07-09 16:58:47 +02:00
Eyck-Alexander Jentzsch 91a23a4a18 Merge branch 'develop' of https://git.minres.com/DBT-RISE/DBT-RISE-TGC into develop 2023-07-09 16:55:06 +02:00
Eyck-Alexander Jentzsch 21d3250e1a changes templates 2023-07-09 16:53:59 +02:00
Eyck-Alexander Jentzsch 87b4082633 Merge branch 'tmp' into develop 2023-07-03 14:22:50 +02:00
Eyck-Alexander Jentzsch 15cd36dcd4 adds fix for compressed instructions and reads 2023-06-05 17:57:38 +02:00
Eyck-Alexander Jentzsch 2281ec4144 corrects errors and adds new backend and 2023-06-05 15:18:27 +02:00
Eyck-Alexander Jentzsch 11c481cec2 adds verbosity to error 2023-06-05 15:17:16 +02:00
9 changed files with 355 additions and 360 deletions
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7
gen_input/templates/CORENAME.h.gtl
View File

@ -30,8 +30,6 @@
*
*******************************************************************************/
<%
import com.minres.coredsl.util.BigIntegerWithRadix
def nativeTypeSize(int size){
if(size<=8) return 8; else if(size<=16) return 16; else if(size<=32) return 32; else return 64;
}
@ -57,10 +55,7 @@ def byteSize(int size){
return 128;
}
def getCString(def val){
if(val instanceof BigIntegerWithRadix)
return ((BigIntegerWithRadix)val).toCString()
else
return val.toString()
return val.toString()
}
%>
#ifndef _${coreDef.name.toUpperCase()}_H_

2
gen_input/templates/interp/CORENAME.cpp.gtl
View File

@ -30,8 +30,6 @@
*
*******************************************************************************/
<%
import com.minres.coredsl.util.BigIntegerWithRadix
def nativeTypeSize(int size){
if(size<=8) return 8; else if(size<=16) return 16; else if(size<=32) return 32; else return 64;
}

2
gen_input/templates/tcc/CORENAME.cpp.gtl
View File

@ -207,7 +207,7 @@ private:
${it}<%}%>
}
auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]);
pc=pc+4;
pc=pc+ ${instr.length/8};
gen_set_pc(tu, pc, traits::NEXT_PC);
tu.open_scope();<%instr.behavior.eachLine{%>
${it}<%}%>

4
src/iss/arch/riscv_hart_m_p.h
View File

@ -619,9 +619,9 @@ template <typename BASE, features_e FEAT> std::pair<uint64_t, bool> riscv_hart_m
}
return std::make_pair(entry, true);
}
throw std::runtime_error("memory load file is not a valid elf file");
throw std::runtime_error(fmt::format("memory load file {} is not a valid elf file",name));
}
throw std::runtime_error("memory load file not found");
throw std::runtime_error(fmt::format("memory load file not found, check if {} is a valid file", name));
}
template<typename BASE, features_e FEAT>

4
src/iss/arch/riscv_hart_msu_vp.h
View File

@ -588,9 +588,9 @@ template <typename BASE> std::pair<uint64_t, bool> riscv_hart_msu_vp<BASE>::load
}
return std::make_pair(entry, true);
}
throw std::runtime_error("memory load file is not a valid elf file");
throw std::runtime_error(fmt::format("memory load file {} is not a valid elf file",name));
}
throw std::runtime_error("memory load file not found");
throw std::runtime_error(fmt::format("memory load file not found, check if {} is a valid file", name));
}
template <typename BASE>

4
src/iss/arch/riscv_hart_mu_p.h
View File

@ -690,9 +690,9 @@ template <typename BASE, features_e FEAT> std::pair<uint64_t, bool> riscv_hart_m
}
return std::make_pair(entry, true);
}
throw std::runtime_error("memory load file is not a valid elf file");
throw std::runtime_error(fmt::format("memory load file {} is not a valid elf file",name));
}
throw std::runtime_error("memory load file not found");
throw std::runtime_error(fmt::format("memory load file not found, check if {} is a valid file", name));
}
template<typename BASE, features_e FEAT>

2
src/iss/arch/tgc_c.h
View File

@ -53,7 +53,7 @@ template <> struct traits<tgc_c> {
static constexpr std::array<const char*, 36> reg_aliases{
{"ZERO", "RA", "SP", "GP", "TP", "T0", "T1", "T2", "S0", "S1", "A0", "A1", "A2", "A3", "A4", "A5", "A6", "A7", "S2", "S3", "S4", "S5", "S6", "S7", "S8", "S9", "S10", "S11", "T3", "T4", "T5", "T6", "PC", "NEXT_PC", "PRIV", "DPC"}};
enum constants {MISA_VAL=0b01000000000000000001000100000100, MARCHID_VAL=0x80000003, XLEN=32, INSTR_ALIGNMENT=2, RFS=32, fence=0, fencei=1, fencevmal=2, fencevmau=3, CSR_SIZE=4096, MUL_LEN=64};
enum constants {MISA_VAL=1073746180, MARCHID_VAL=2147483651, XLEN=32, INSTR_ALIGNMENT=2, RFS=32, fence=0, fencei=1, fencevmal=2, fencevmau=3, CSR_SIZE=4096, MUL_LEN=64};
constexpr static unsigned FP_REGS_SIZE = 0;

131
src/vm/interp/vm_tgc_c.cpp
View File

@ -389,7 +389,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
}
else {
if(rd != 0) {
*(X+rd) = *PC + (int32_t)imm;
*(X+rd) = (uint32_t)(*PC + (int32_t)imm);
}
}
}
@ -419,9 +419,9 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
}
else {
if(rd != 0) {
*(X+rd) = *PC + 4;
*(X+rd) = (uint32_t)(*PC + 4);
}
*NEXT_PC = *PC + (int32_t)sext<21>(imm);
*NEXT_PC = (uint32_t)(*PC + (int32_t)sext<21>(imm));
this->core.reg.last_branch = 1;
}
}
@ -448,13 +448,13 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
raise(0, 2);
}
else {
uint32_t new_pc = (*(X+rs1) + (int16_t)sext<12>(imm)) & ~ 0x1;
uint32_t new_pc = (uint32_t)((*(X+rs1) + (int16_t)sext<12>(imm)) & ~ 0x1);
if(new_pc % traits::INSTR_ALIGNMENT) {
raise(0, 0);
}
else {
if(rd != 0) {
*(X+rd) = *PC + 4;
*(X+rd) = (uint32_t)(*PC + 4);
}
*NEXT_PC = new_pc & ~ 0x1;
this->core.reg.last_branch = 1;
@ -488,7 +488,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
raise(0, 0);
}
else {
*NEXT_PC = *PC + (int16_t)sext<13>(imm);
*NEXT_PC = (uint32_t)(*PC + (int16_t)sext<13>(imm));
this->core.reg.last_branch = 1;
}
}
@ -521,7 +521,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
raise(0, 0);
}
else {
*NEXT_PC = *PC + (int16_t)sext<13>(imm);
*NEXT_PC = (uint32_t)(*PC + (int16_t)sext<13>(imm));
this->core.reg.last_branch = 1;
}
}
@ -554,7 +554,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
raise(0, 0);
}
else {
*NEXT_PC = *PC + (int16_t)sext<13>(imm);
*NEXT_PC = (uint32_t)(*PC + (int16_t)sext<13>(imm));
this->core.reg.last_branch = 1;
}
}
@ -587,7 +587,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
raise(0, 0);
}
else {
*NEXT_PC = *PC + (int16_t)sext<13>(imm);
*NEXT_PC = (uint32_t)(*PC + (int16_t)sext<13>(imm));
this->core.reg.last_branch = 1;
}
}
@ -620,7 +620,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
raise(0, 0);
}
else {
*NEXT_PC = *PC + (int16_t)sext<13>(imm);
*NEXT_PC = (uint32_t)(*PC + (int16_t)sext<13>(imm));
this->core.reg.last_branch = 1;
}
}
@ -653,7 +653,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
raise(0, 0);
}
else {
*NEXT_PC = *PC + (int16_t)sext<13>(imm);
*NEXT_PC = (uint32_t)(*PC + (int16_t)sext<13>(imm));
this->core.reg.last_branch = 1;
}
}
@ -681,7 +681,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
raise(0, 2);
}
else {
uint32_t load_address = *(X+rs1) + (int16_t)sext<12>(imm);
uint32_t load_address = (uint32_t)(*(X+rs1) + (int16_t)sext<12>(imm));
int8_t read_res = super::template read_mem<int8_t>(traits::MEM, load_address);
if(this->core.reg.trap_state>=0x80000000UL) goto TRAP_LB;
int8_t res = (int8_t)read_res;
@ -712,7 +712,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
raise(0, 2);
}
else {
uint32_t load_address = *(X+rs1) + (int16_t)sext<12>(imm);
uint32_t load_address = (uint32_t)(*(X+rs1) + (int16_t)sext<12>(imm));
int16_t read_res = super::template read_mem<int16_t>(traits::MEM, load_address);
if(this->core.reg.trap_state>=0x80000000UL) goto TRAP_LH;
int16_t res = (int16_t)read_res;
@ -743,7 +743,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
raise(0, 2);
}
else {
uint32_t load_address = *(X+rs1) + (int16_t)sext<12>(imm);
uint32_t load_address = (uint32_t)(*(X+rs1) + (int16_t)sext<12>(imm));
int32_t read_res = super::template read_mem<int32_t>(traits::MEM, load_address);
if(this->core.reg.trap_state>=0x80000000UL) goto TRAP_LW;
int32_t res = (int32_t)read_res;
@ -774,10 +774,10 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
raise(0, 2);
}
else {
uint32_t load_address = *(X+rs1) + (int16_t)sext<12>(imm);
uint32_t load_address = (uint32_t)(*(X+rs1) + (int16_t)sext<12>(imm));
uint8_t read_res = super::template read_mem<uint8_t>(traits::MEM, load_address);
if(this->core.reg.trap_state>=0x80000000UL) goto TRAP_LBU;
uint8_t res = (uint8_t)read_res;
uint8_t res = read_res;
if(rd != 0) {
*(X+rd) = (uint32_t)res;
}
@ -805,10 +805,10 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
raise(0, 2);
}
else {
uint32_t load_address = *(X+rs1) + (int16_t)sext<12>(imm);
uint32_t load_address = (uint32_t)(*(X+rs1) + (int16_t)sext<12>(imm));
uint16_t read_res = super::template read_mem<uint16_t>(traits::MEM, load_address);
if(this->core.reg.trap_state>=0x80000000UL) goto TRAP_LHU;
uint16_t res = (uint16_t)read_res;
uint16_t res = read_res;
if(rd != 0) {
*(X+rd) = (uint32_t)res;
}
@ -836,8 +836,8 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
raise(0, 2);
}
else {
uint32_t store_address = *(X+rs1) + (int16_t)sext<12>(imm);
super::template write_mem<uint8_t>(traits::MEM, store_address, (int8_t)*(X+rs2));
uint32_t store_address = (uint32_t)(*(X+rs1) + (int16_t)sext<12>(imm));
super::template write_mem<uint8_t>(traits::MEM, store_address, (uint8_t)*(X+rs2));
if(this->core.reg.trap_state>=0x80000000UL) goto TRAP_SB;
}
}
@ -863,8 +863,8 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
raise(0, 2);
}
else {
uint32_t store_address = *(X+rs1) + (int16_t)sext<12>(imm);
super::template write_mem<uint16_t>(traits::MEM, store_address, (int16_t)*(X+rs2));
uint32_t store_address = (uint32_t)(*(X+rs1) + (int16_t)sext<12>(imm));
super::template write_mem<uint16_t>(traits::MEM, store_address, (uint16_t)*(X+rs2));
if(this->core.reg.trap_state>=0x80000000UL) goto TRAP_SH;
}
}
@ -890,8 +890,8 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
raise(0, 2);
}
else {
uint32_t store_address = *(X+rs1) + (int16_t)sext<12>(imm);
super::template write_mem<uint32_t>(traits::MEM, store_address, (int32_t)*(X+rs2));
uint32_t store_address = (uint32_t)(*(X+rs1) + (int16_t)sext<12>(imm));
super::template write_mem<uint32_t>(traits::MEM, store_address, (uint32_t)*(X+rs2));
if(this->core.reg.trap_state>=0x80000000UL) goto TRAP_SW;
}
}
@ -918,7 +918,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
}
else {
if(rd != 0) {
*(X+rd) = *(X+rs1) + (int16_t)sext<12>(imm);
*(X+rd) = (uint32_t)(*(X+rs1) + (int16_t)sext<12>(imm));
}
}
}
@ -1134,7 +1134,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
}
else {
if(rd != 0) {
*(X+rd) = (int32_t)*(X+rs1) >> shamt;
*(X+rd) = (uint32_t)((int32_t)*(X+rs1) >> shamt);
}
}
}
@ -1161,7 +1161,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
}
else {
if(rd != 0) {
*(X+rd) = *(X+rs1) + *(X+rs2);
*(X+rd) = (uint32_t)(*(X+rs1) + *(X+rs2));
}
}
}
@ -1188,7 +1188,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
}
else {
if(rd != 0) {
*(X+rd) = *(X+rs1) - *(X+rs2);
*(X+rd) = (uint32_t)(*(X+rs1) - *(X+rs2));
}
}
}
@ -1350,7 +1350,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
}
else {
if(rd != 0) {
*(X+rd) = (int32_t)*(X+rs1) >> (*(X+rs2) & (traits::XLEN - 1));
*(X+rd) = (uint32_t)((int32_t)*(X+rs1) >> (*(X+rs2) & (traits::XLEN - 1)));
}
}
}
@ -1427,7 +1427,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
*NEXT_PC = *PC + 4;
// execute instruction
{
super::template write_mem<uint8_t>(traits::FENCE, traits::fence, pred << 4 | succ);
super::template write_mem<uint32_t>(traits::FENCE, traits::fence, (uint8_t)pred << 4 | succ);
if(this->core.reg.trap_state>=0x80000000UL) goto TRAP_FENCE;
}
TRAP_FENCE:break;
@ -1706,7 +1706,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
*NEXT_PC = *PC + 4;
// execute instruction
{
super::template write_mem<uint16_t>(traits::FENCE, traits::fencei, imm);
super::template write_mem<uint32_t>(traits::FENCE, traits::fencei, imm);
if(this->core.reg.trap_state>=0x80000000UL) goto TRAP_FENCE_I;
}
TRAP_FENCE_I:break;
@ -1731,7 +1731,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
raise(0, 2);
}
else {
int64_t res = (int64_t)(int32_t)*(X+rs1) * (int64_t)(int32_t)*(X+rs2);
int64_t res = (int32_t)*(X+rs1) * (int32_t)*(X+rs2);
if(rd != 0) {
*(X+rd) = (uint32_t)res;
}
@ -1759,7 +1759,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
raise(0, 2);
}
else {
int64_t res = (int64_t)(int32_t)*(X+rs1) * (int64_t)(int32_t)*(X+rs2);
int64_t res = (int32_t)*(X+rs1) * (int32_t)*(X+rs2);
if(rd != 0) {
*(X+rd) = (uint32_t)(res >> traits::XLEN);
}
@ -1787,7 +1787,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
raise(0, 2);
}
else {
int64_t res = (int64_t)(int32_t)*(X+rs1) * (uint64_t)*(X+rs2);
int64_t res = (int32_t)*(X+rs1) * *(X+rs2);
if(rd != 0) {
*(X+rd) = (uint32_t)(res >> traits::XLEN);
}
@ -1815,7 +1815,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
raise(0, 2);
}
else {
uint64_t res = (uint64_t)*(X+rs1) * (uint64_t)*(X+rs2);
uint64_t res = *(X+rs1) * *(X+rs2);
if(rd != 0) {
*(X+rd) = (uint32_t)(res >> traits::XLEN);
}
@ -1852,11 +1852,11 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
*(X+rd) = MMIN;
}
else {
*(X+rd) = dividend / divisor;
*(X+rd) = (uint32_t)(dividend / divisor);
}
}
else {
*(X+rd) = (int32_t)- 1;
*(X+rd) = (uint32_t)- 1;
}
}
}
@ -1885,12 +1885,12 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
else {
if(*(X+rs2) != 0) {
if(rd != 0) {
*(X+rd) = *(X+rs1) / *(X+rs2);
*(X+rd) = (uint32_t)(*(X+rs1) / *(X+rs2));
}
}
else {
if(rd != 0) {
*(X+rd) = (int32_t)- 1;
*(X+rd) = (uint32_t)- 1;
}
}
}
@ -1926,7 +1926,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
}
else {
if(rd != 0) {
*(X+rd) = (int32_t)*(X+rs1) % (int32_t)*(X+rs2);
*(X+rd) = (uint32_t)((int32_t)*(X+rs1) % (int32_t)*(X+rs2));
}
}
}
@ -1980,7 +1980,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
/* generate console output when executing the command */
auto mnemonic = fmt::format(
"{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "caddi4spn"),
fmt::arg("rd", name(rd)), fmt::arg("imm", imm));
fmt::arg("rd", name(8+rd)), fmt::arg("imm", imm));
this->core.disass_output(pc.val, mnemonic);
}
// used registers
@ -1989,7 +1989,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(imm) {
*(X+rd + 8) = *(X+2) + imm;
*(X+rd + 8) = (uint32_t)(*(X+2) + imm);
}
else {
raise(0, 2);
@ -2013,10 +2013,10 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
*NEXT_PC = *PC + 2;
// execute instruction
{
uint32_t load_address = *(X+rs1 + 8) + uimm;
uint32_t load_address = (uint32_t)(*(X+rs1 + 8) + uimm);
int32_t read_res = super::template read_mem<int32_t>(traits::MEM, load_address);
if(this->core.reg.trap_state>=0x80000000UL) goto TRAP_CLW;
*(X+rd + 8) = (int32_t)read_res;
*(X+rd + 8) = (uint32_t)(int32_t)read_res;
}
TRAP_CLW:break;
}// @suppress("No break at end of case")
@ -2036,8 +2036,8 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
*NEXT_PC = *PC + 2;
// execute instruction
{
uint32_t load_address = *(X+rs1 + 8) + uimm;
super::template write_mem<uint32_t>(traits::MEM, load_address, (int32_t)*(X+rs2 + 8));
uint32_t load_address = (uint32_t)(*(X+rs1 + 8) + uimm);
super::template write_mem<uint32_t>(traits::MEM, load_address, (uint32_t)*(X+rs2 + 8));
if(this->core.reg.trap_state>=0x80000000UL) goto TRAP_CSW;
}
TRAP_CSW:break;
@ -2062,7 +2062,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
}
else {
if(rs1 != 0) {
*(X+rs1) = *(X+rs1) + (int8_t)sext<6>(imm);
*(X+rs1) = (uint32_t)(*(X+rs1) + (int8_t)sext<6>(imm));
}
}
}
@ -2095,8 +2095,8 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
*NEXT_PC = *PC + 2;
// execute instruction
{
*(X+1) = *PC + 2;
*NEXT_PC = *PC + (int16_t)sext<12>(imm);
*(X+1) = (uint32_t)(*PC + 2);
*NEXT_PC = (uint32_t)(*PC + (int16_t)sext<12>(imm));
this->core.reg.last_branch = 1;
}
TRAP_CJAL:break;
@ -2121,7 +2121,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
}
else {
if(rd != 0) {
*(X+rd) = (int8_t)sext<6>(imm);
*(X+rd) = (uint32_t)((int8_t)sext<6>(imm));
}
}
}
@ -2146,7 +2146,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
raise(0, 2);
}
if(rd != 0) {
*(X+rd) = (int32_t)sext<18>(imm);
*(X+rd) = (uint32_t)((int32_t)sext<18>(imm));
}
}
TRAP_CLUI:break;
@ -2166,7 +2166,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(nzimm) {
*(X+2) = *(X+2) + (int16_t)sext<10>(nzimm);
*(X+2) = (uint32_t)(*(X+2) + (int16_t)sext<10>(nzimm));
}
else {
raise(0, 2);
@ -2223,11 +2223,11 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(shamt) {
*(X+rs1 + 8) = ((int32_t)*(X+rs1 + 8)) >> shamt;
*(X+rs1 + 8) = (uint32_t)(((int32_t)*(X+rs1 + 8)) >> shamt);
}
else {
if(traits::XLEN == 128) {
*(X+rs1 + 8) = ((int32_t)*(X+rs1 + 8)) >> 64;
*(X+rs1 + 8) = (uint32_t)(((int32_t)*(X+rs1 + 8)) >> 64);
}
}
}
@ -2248,7 +2248,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
*NEXT_PC = *PC + 2;
// execute instruction
{
*(X+rs1 + 8) = *(X+rs1 + 8) & (int8_t)sext<6>(imm);
*(X+rs1 + 8) = (uint32_t)(*(X+rs1 + 8) & (int8_t)sext<6>(imm));
}
TRAP_CANDI:break;
}// @suppress("No break at end of case")
@ -2267,7 +2267,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
*NEXT_PC = *PC + 2;
// execute instruction
{
*(X+rd + 8) = *(X+rd + 8) - *(X+rs2 + 8);
*(X+rd + 8) = (uint32_t)(*(X+rd + 8) - *(X+rs2 + 8));
}
TRAP_CSUB:break;
}// @suppress("No break at end of case")
@ -2341,7 +2341,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
*NEXT_PC = *PC + 2;
// execute instruction
{
*NEXT_PC = *PC + (int16_t)sext<12>(imm);
*NEXT_PC = (uint32_t)(*PC + (int16_t)sext<12>(imm));
this->core.reg.last_branch = 1;
}
TRAP_CJ:break;
@ -2362,7 +2362,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(*(X+rs1 + 8) == 0) {
*NEXT_PC = *PC + (int16_t)sext<9>(imm);
*NEXT_PC = (uint32_t)(*PC + (int16_t)sext<9>(imm));
this->core.reg.last_branch = 1;
}
}
@ -2384,7 +2384,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(*(X+rs1 + 8) != 0) {
*NEXT_PC = *PC + (int16_t)sext<9>(imm);
*NEXT_PC = (uint32_t)(*PC + (int16_t)sext<9>(imm));
this->core.reg.last_branch = 1;
}
}
@ -2435,10 +2435,11 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
raise(0, 2);
}
else {
int32_t read_res = super::template read_mem<int32_t>(traits::MEM, *(X+2) + uimm);
uint32_t offs = (uint32_t)(*(X+2) + uimm);
int32_t read_res = super::template read_mem<int32_t>(traits::MEM, offs);
if(this->core.reg.trap_state>=0x80000000UL) goto TRAP_CLWSP;
int32_t res = read_res;
*(X+rd) = (int32_t)res;
int32_t res = (int32_t)read_res;
*(X+rd) = (uint32_t)res;
}
}
TRAP_CLWSP:break;
@ -2526,7 +2527,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
}
else {
if(rd != 0) {
*(X+rd) = *(X+rd) + *(X+rs2);
*(X+rd) = (uint32_t)(*(X+rd) + *(X+rs2));
}
}
}
@ -2551,7 +2552,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
}
else {
uint32_t new_pc = *(X+rs1);
*(X+1) = *PC + 2;
*(X+1) = (uint32_t)(*PC + 2);
*NEXT_PC = new_pc & ~ 0x1;
this->core.reg.last_branch = 1;
}
@ -2590,7 +2591,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
raise(0, 2);
}
else {
uint32_t offs = *(X+2) + uimm;
uint32_t offs = (uint32_t)(*(X+2) + uimm);
super::template write_mem<uint32_t>(traits::MEM, offs, (uint32_t)*(X+rs2));
if(this->core.reg.trap_state>=0x80000000UL) goto TRAP_CSWSP;
}

559
src/vm/tcc/vm_tgc_c.cpp
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