DBT-RISE/DBT-RISE-TGC
9
0
Fork 0
Code Issues 1 Pull Requests 1 Projects Releases Wiki Activity

Compare commits

base: DBT-RISE:1c90fe765d47508c160f16c2119ccc5d6c272d51
Branches Tags
DBT-RISE:main DBT-RISE:develop DBT-RISE:featture/interp_instr_cache DBT-RISE:feature/privilege_refactor DBT-RISE:feature/htif DBT-RISE:feature/eve_checkin DBT-RISE:feature/iss_factory DBT-RISE:feature/core_factory DBT-RISE:Trace_enhancement DBT-RISE:feature/reduced_output DBT-RISE:msvc_compat DBT-RISE:hotfix/latest_scc DBT-RISE:feature/interpreter
...
compare: DBT-RISE:5d481eb79db9a82753bc869d790908f010ac8a68
Branches Tags
DBT-RISE:develop DBT-RISE:featture/interp_instr_cache DBT-RISE:feature/privilege_refactor DBT-RISE:feature/htif DBT-RISE:feature/eve_checkin DBT-RISE:main DBT-RISE:feature/iss_factory DBT-RISE:feature/core_factory DBT-RISE:Trace_enhancement DBT-RISE:feature/reduced_output DBT-RISE:msvc_compat DBT-RISE:hotfix/latest_scc DBT-RISE:feature/interpreter

1 Commits
1c90fe765d ... 5d481eb79d

Author SHA1 Message Date
Eyck Jentzsch
5d481eb79d fix generation of non-exception code 2022-05-30 22:04:16 +02:00
1 changed files with 15 additions and 19 deletions
Expand all files Collapse all files

34
gen_input/templates/interp/CORENAME.cpp.gtl
View File

@@ -301,25 +301,21 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, static_cast<unsigned>(inst_id)); if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, static_cast<unsigned>(inst_id));
switch(inst_id){<%instructions.eachWithIndex{instr, idx -> %> switch(inst_id){<%instructions.eachWithIndex{instr, idx -> %>
case arch::traits<ARCH>::opcode_e::${instr.name}: { case arch::traits<ARCH>::opcode_e::${instr.name}: {
<%instr.fields.eachLine{%>${it} <%instr.fields.eachLine{%>${it}
<%}%>if(this->disass_enabled){ <%}%>if(this->disass_enabled){
/* generate console output when executing the command */ /* generate console output when executing the command */<%instr.disass.eachLine{%>
<%instr.disass.eachLine{%>${it} ${it}<%}%>
<%}%> }
} // used registers<%instr.usedVariables.each{ k,v->
// used registers<%instr.usedVariables.each{ k,v-> if(v.isArray) {%>
if(v.isArray) {%> auto* ${k} = reinterpret_cast<uint${nativeTypeSize(v.type.size)}_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::${k}0]);<% }else{ %>
auto* ${k} = reinterpret_cast<uint${nativeTypeSize(v.type.size)}_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::${k}0]);<% }else{ %> auto* ${k} = reinterpret_cast<uint${nativeTypeSize(v.type.size)}_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::${k}]);
auto* ${k} = reinterpret_cast<uint${nativeTypeSize(v.type.size)}_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::${k}]); <%}}%>// calculate next pc value
<%}}%>// calculate next pc value *NEXT_PC = *PC + ${instr.length/8};
*NEXT_PC = *PC + ${instr.length/8}; // execute instruction<%instr.behavior.eachLine{%>
// execute instruction ${it}<%}%>
try { TRAP_${instr.name}:break;
<%instr.behavior.eachLine{%>${it} }// @suppress("No break at end of case")<%}%>
<%}%>
} catch(...){}
TRAP_${instr.name}:break;
}// @suppress("No break at end of case")<%}%>
default: { default: {
*NEXT_PC = *PC + ((instr & 3) == 3 ? 4 : 2); *NEXT_PC = *PC + ((instr & 3) == 3 ? 4 : 2);
raise(0, 2); raise(0, 2);