DBT-RISE/DBT-RISE-TGC
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base: DBT-RISE:12ccfc055a3e885da61a74dcf16cc047c8e272a7
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DBT-RISE:main DBT-RISE:develop DBT-RISE:featture/interp_instr_cache DBT-RISE:feature/privilege_refactor DBT-RISE:feature/htif DBT-RISE:feature/eve_checkin DBT-RISE:feature/iss_factory DBT-RISE:feature/core_factory DBT-RISE:Trace_enhancement DBT-RISE:feature/reduced_output DBT-RISE:msvc_compat DBT-RISE:hotfix/latest_scc DBT-RISE:feature/interpreter
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compare: DBT-RISE:a53ee42e13e59cb23336990edd034756a6df7cfb
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DBT-RISE:develop DBT-RISE:featture/interp_instr_cache DBT-RISE:feature/privilege_refactor DBT-RISE:feature/htif DBT-RISE:feature/eve_checkin DBT-RISE:main DBT-RISE:feature/iss_factory DBT-RISE:feature/core_factory DBT-RISE:Trace_enhancement DBT-RISE:feature/reduced_output DBT-RISE:msvc_compat DBT-RISE:hotfix/latest_scc DBT-RISE:feature/interpreter

1 Commits
12ccfc055a ... a53ee42e13

Author SHA1 Message Date
Eyck Jentzsch
a53ee42e13 updates TGC_C according to CoreDSL description update 2022-07-12 22:34:22 +02:00
1 changed files with 4 additions and 5 deletions
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9
src/vm/interp/vm_tgc_c.cpp
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@@ -2187,12 +2187,11 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
*NEXT_PC = *PC + 2;
// execute instruction
{
uint32_t offs = *(X+2) + uimm;
int32_t read_res = super::template read_mem<int32_t>(traits::MEM, offs);
if(this->core.trap_state) goto TRAP_CLWSP;
int32_t res = read_res;
if(rd % traits::RFS) {
*(X+rd % traits::RFS) = res;
int32_t read_res = super::template read_mem<int32_t>(traits::MEM, *(X+2) + uimm);
if(this->core.trap_state) goto TRAP_CLWSP;
int32_t res = read_res;
*(X+rd % traits::RFS) = (int32_t)res;
}
else {
raise(0, 2);