updates TGC_C according to CoreDSL description update

src/vm/interp/vm_tgc_c.cpp

@@ -2187,12 +2187,11 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                 *NEXT_PC = *PC + 2;
                 // execute instruction
                 {
-                    uint32_t offs = *(X+2) + uimm;
+                    if(rd % traits::RFS) {
-                    int32_t read_res = super::template read_mem<int32_t>(traits::MEM, offs);
+                        int32_t read_res = super::template read_mem<int32_t>(traits::MEM, *(X+2) + uimm);
                         if(this->core.trap_state) goto TRAP_CLWSP;
                         int32_t res = read_res;
-                    if(rd % traits::RFS) {
+                        *(X+rd % traits::RFS) = (int32_t)res;
-                        *(X+rd % traits::RFS) = res;
                     }
                     else {
                         raise(0, 2);