adds support for different branch types in tracing

gen_input/templates/interp/CORENAME.cpp.gtl

@@ -137,44 +137,6 @@ protected:
     using coro_t = boost::coroutines2::coroutine<void>::pull_type;
     std::vector<coro_t> spawn_blocks;
 
-    template<typename T>
-    T& pc_assign(T& val){super::ex_info.branch_taken=true; return val;}
-    inline uint8_t readSpace1(typename super::mem_type_e space, uint64_t addr){
-        auto ret = super::template read_mem<uint8_t>(space, addr);
-        if(this->core.trap_state) throw 0;
-        return ret;
-    }
-    inline uint16_t readSpace2(typename super::mem_type_e space, uint64_t addr){
-        auto ret = super::template read_mem<uint16_t>(space, addr);
-        if(this->core.trap_state) throw 0;
-        return ret;
-    }
-    inline uint32_t readSpace4(typename super::mem_type_e space, uint64_t addr){
-        auto ret = super::template read_mem<uint32_t>(space, addr);
-        if(this->core.trap_state) throw 0;
-        return ret;
-    }
-    inline uint64_t readSpace8(typename super::mem_type_e space, uint64_t addr){
-        auto ret = super::template read_mem<uint64_t>(space, addr);
-        if(this->core.trap_state) throw 0;
-        return ret;
-    }
-    inline void writeSpace1(typename super::mem_type_e space, uint64_t addr, uint8_t data){
-        super::write_mem(space, addr, data);
-        if(this->core.trap_state) throw 0;
-    }
-    inline void writeSpace2(typename super::mem_type_e space, uint64_t addr, uint16_t data){
-        super::write_mem(space, addr, data);
-        if(this->core.trap_state) throw 0;
-    }
-    inline void writeSpace4(typename super::mem_type_e space, uint64_t addr, uint32_t data){
-        super::write_mem(space, addr, data);
-        if(this->core.trap_state) throw 0;
-    }
-    inline void writeSpace8(typename super::mem_type_e space, uint64_t addr, uint64_t data){
-        super::write_mem(space, addr, data);
-        if(this->core.trap_state) throw 0;
-    }
     template<unsigned W, typename U, typename S = typename std::make_signed<U>::type>
     inline S sext(U from) {
         auto mask = (1ULL<<W) - 1;
@@ -183,12 +145,15 @@ protected:
     }
     
     inline void process_spawn_blocks() {
+        if(spawn_blocks.size()==0) return;
+        std::swap(super::ex_info.branch_taken, super::ex_info.hw_branch_taken);
         for(auto it = std::begin(spawn_blocks); it!=std::end(spawn_blocks);)
              if(*it){
                  (*it)();
                  ++it;
              } else
                  spawn_blocks.erase(it);
+        std::swap(super::ex_info.branch_taken, super::ex_info.hw_branch_taken);
     }
 <%functions.each{ it.eachLine { %>
     ${it}<%}%>

src/iss/debugger/riscv_target_adapter.h

@@ -120,9 +120,9 @@ public:
 
     status packetsize_query(std::string &out_buf) override;
 
-    status add_break(int type, uint64_t addr, unsigned int length) override;
+    status add_break(break_type type, uint64_t addr, unsigned int length) override;
 
-    status remove_break(int type, uint64_t addr, unsigned int length) override;
+    status remove_break(break_type type, uint64_t addr, unsigned int length) override;
 
     status resume_from_addr(bool step, int sig, uint64_t addr, rp_thread_ref thread,
             std::function<void(unsigned)> stop_callback) override;
@@ -193,20 +193,20 @@ status riscv_target_adapter<ARCH>::read_registers(std::vector<uint8_t> &data, st
         }
     }
     // work around fill with F type registers
-//    if (arch::traits<ARCH>::NUM_REGS < 65) {
-//        auto reg_width = sizeof(typename arch::traits<ARCH>::reg_t);
-//        for (size_t reg_no = 0; reg_no < 33; ++reg_no) {
-//            for (size_t j = 0; j < reg_width; ++j) {
-//                data.push_back(0x0);
-//                avail.push_back(0x00);
-//            }
-//            // if(arch::traits<ARCH>::XLEN < 64)
-//            //     for(unsigned j=0; j<4; ++j){
-//            //         data.push_back(0x0);
-//            //         avail.push_back(0x00);
-//            //     }
-//        }
-//    }
+    //    if (arch::traits<ARCH>::NUM_REGS < 65) {
+    //        auto reg_width = sizeof(typename arch::traits<ARCH>::reg_t);
+    //        for (size_t reg_no = 0; reg_no < 33; ++reg_no) {
+    //            for (size_t j = 0; j < reg_width; ++j) {
+    //                data.push_back(0x0);
+    //                avail.push_back(0x00);
+    //            }
+    //            // if(arch::traits<ARCH>::XLEN < 64)
+    //            //     for(unsigned j=0; j<4; ++j){
+    //            //         data.push_back(0x0);
+    //            //         avail.push_back(0x00);
+    //            //     }
+    //        }
+    //    }
     return Ok;
 }
 
@@ -331,7 +331,12 @@ template <typename ARCH> status riscv_target_adapter<ARCH>::packetsize_query(std
     return Ok;
 }
 
-template <typename ARCH> status riscv_target_adapter<ARCH>::add_break(int type, uint64_t addr, unsigned int length) {
+template <typename ARCH> status riscv_target_adapter<ARCH>::add_break(break_type type, uint64_t addr, unsigned int length) {
+    switch(type) {
+    default:
+        return Err;
+    case SW_EXEC:
+    case HW_EXEC: {
         auto saddr = map_addr({iss::access_type::FETCH, iss::address_type::PHYSICAL, 0, addr});
         auto eaddr = map_addr({iss::access_type::FETCH, iss::address_type::PHYSICAL, 0, addr + length});
         target_adapter_base::bp_lut.addEntry(++target_adapter_base::bp_count, saddr.val, eaddr.val - saddr.val);
@@ -339,9 +344,16 @@ template <typename ARCH> status riscv_target_adapter<ARCH>::add_break(int type,
                 << saddr.val << std::dec;
         LOG(TRACE) << "Now having " << target_adapter_base::bp_lut.size() << " breakpoints";
         return Ok;
+    }
+    }
 }
 
-template <typename ARCH> status riscv_target_adapter<ARCH>::remove_break(int type, uint64_t addr, unsigned int length) {
+template <typename ARCH> status riscv_target_adapter<ARCH>::remove_break(break_type type, uint64_t addr, unsigned int length) {
+    switch(type) {
+    default:
+        return Err;
+    case SW_EXEC:
+    case HW_EXEC: {
         auto saddr = map_addr({iss::access_type::FETCH, iss::address_type::PHYSICAL, 0, addr});
         unsigned handle = target_adapter_base::bp_lut.getEntry(saddr.val);
         if (handle) {
@@ -354,6 +366,8 @@ template <typename ARCH> status riscv_target_adapter<ARCH>::remove_break(int typ
         }
         LOG(TRACE) << "Now having " << target_adapter_base::bp_lut.size() << " breakpoints";
         return Err;
+    }
+    }
 }
 
 template <typename ARCH>

src/sysc/core_complex.h

@@ -69,7 +69,7 @@ struct core_trace;
 
 class core_complex : public sc_core::sc_module, public scc::traceable {
 public:
-    tlm::scc::initiator_mixin<tlm::scc::scv::tlm_rec_initiator_socket<32>> initiator{"intor"};
+    tlm::scc::initiator_mixin<tlm::tlm_initiator_socket<32>> initiator{"intor"};
 
     sc_core::sc_in<bool> rst_i{"rst_i"};
 
@@ -84,7 +84,7 @@ public:
 #ifndef CWR_SYSTEMC
 	sc_core::sc_in<sc_core::sc_time> clk_i{"clk_i"};
 
-    sc_core::sc_port<tlm::tlm_peek_if<uint64_t>, 1, sc_core::SC_ZERO_OR_MORE_BOUND> mtime_o;
+    sc_core::sc_port<tlm::tlm_peek_if<uint64_t>, 1, sc_core::SC_ZERO_OR_MORE_BOUND> mtime_o{"mtime_o"};
 
     cci::cci_param<std::string> elf_file{"elf_file", ""};
 

src/vm/interp/vm_tgc_c.cpp

@@ -131,44 +131,6 @@ protected:
     using coro_t = boost::coroutines2::coroutine<void>::pull_type;
     std::vector<coro_t> spawn_blocks;
 
-    template<typename T>
-    T& pc_assign(T& val){super::ex_info.branch_taken=true; return val;}
-    inline uint8_t readSpace1(typename super::mem_type_e space, uint64_t addr){
-        auto ret = super::template read_mem<uint8_t>(space, addr);
-        if(this->core.trap_state) throw 0;
-        return ret;
-    }
-    inline uint16_t readSpace2(typename super::mem_type_e space, uint64_t addr){
-        auto ret = super::template read_mem<uint16_t>(space, addr);
-        if(this->core.trap_state) throw 0;
-        return ret;
-    }
-    inline uint32_t readSpace4(typename super::mem_type_e space, uint64_t addr){
-        auto ret = super::template read_mem<uint32_t>(space, addr);
-        if(this->core.trap_state) throw 0;
-        return ret;
-    }
-    inline uint64_t readSpace8(typename super::mem_type_e space, uint64_t addr){
-        auto ret = super::template read_mem<uint64_t>(space, addr);
-        if(this->core.trap_state) throw 0;
-        return ret;
-    }
-    inline void writeSpace1(typename super::mem_type_e space, uint64_t addr, uint8_t data){
-        super::write_mem(space, addr, data);
-        if(this->core.trap_state) throw 0;
-    }
-    inline void writeSpace2(typename super::mem_type_e space, uint64_t addr, uint16_t data){
-        super::write_mem(space, addr, data);
-        if(this->core.trap_state) throw 0;
-    }
-    inline void writeSpace4(typename super::mem_type_e space, uint64_t addr, uint32_t data){
-        super::write_mem(space, addr, data);
-        if(this->core.trap_state) throw 0;
-    }
-    inline void writeSpace8(typename super::mem_type_e space, uint64_t addr, uint64_t data){
-        super::write_mem(space, addr, data);
-        if(this->core.trap_state) throw 0;
-    }
     template<unsigned W, typename U, typename S = typename std::make_signed<U>::type>
     inline S sext(U from) {
         auto mask = (1ULL<<W) - 1;
@@ -177,12 +139,15 @@ protected:
     }
     
     inline void process_spawn_blocks() {
+        if(spawn_blocks.size()==0) return;
+        std::swap(super::ex_info.branch_taken, super::ex_info.hw_branch_taken);
         for(auto it = std::begin(spawn_blocks); it!=std::end(spawn_blocks);)
              if(*it){
                  (*it)();
                  ++it;
              } else
                  spawn_blocks.erase(it);
+        std::swap(super::ex_info.branch_taken, super::ex_info.hw_branch_taken);
     }
 
 private: