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base: DBT-RISE:0833198d3434951c9648fc9304ec06371527d915
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DBT-RISE:main DBT-RISE:develop DBT-RISE:featture/interp_instr_cache DBT-RISE:feature/privilege_refactor DBT-RISE:feature/htif DBT-RISE:feature/eve_checkin DBT-RISE:feature/iss_factory DBT-RISE:feature/core_factory DBT-RISE:Trace_enhancement DBT-RISE:feature/reduced_output DBT-RISE:msvc_compat DBT-RISE:hotfix/latest_scc DBT-RISE:feature/interpreter
...
compare: DBT-RISE:00e02bf5656af608632bc31eeec04470d27e3a52
Branches Tags
DBT-RISE:develop DBT-RISE:featture/interp_instr_cache DBT-RISE:feature/privilege_refactor DBT-RISE:feature/htif DBT-RISE:feature/eve_checkin DBT-RISE:main DBT-RISE:feature/iss_factory DBT-RISE:feature/core_factory DBT-RISE:Trace_enhancement DBT-RISE:feature/reduced_output DBT-RISE:msvc_compat DBT-RISE:hotfix/latest_scc DBT-RISE:feature/interpreter

4 Commits
0833198d34 ... 00e02bf565

Author SHA1 Message Date
Eyck Jentzsch
00e02bf565 adds support for different branch types in tracing 2022-08-08 06:30:37 +02:00
Eyck Jentzsch
1ad66a71d8 extends supported break point types 2022-08-06 09:53:24 +02:00
Eyck Jentzsch
e60fa3d5e6 adaptes to changes in dbt-rise-core 2022-08-06 09:49:32 +02:00
Eyck Jentzsch
8407f6287f replaces core_complex socket 2022-07-24 20:52:28 +02:00
4 changed files with 101 additions and 157 deletions
Expand all files Collapse all files

41
gen_input/templates/interp/CORENAME.cpp.gtl
View File

@ -137,44 +137,6 @@ protected:
using coro_t = boost::coroutines2::coroutine<void>::pull_type; using coro_t = boost::coroutines2::coroutine<void>::pull_type;
std::vector<coro_t> spawn_blocks; std::vector<coro_t> spawn_blocks;
template<typename T>
T& pc_assign(T& val){super::ex_info.branch_taken=true; return val;}
inline uint8_t readSpace1(typename super::mem_type_e space, uint64_t addr){
auto ret = super::template read_mem<uint8_t>(space, addr);
if(this->core.trap_state) throw 0;
return ret;
}
inline uint16_t readSpace2(typename super::mem_type_e space, uint64_t addr){
auto ret = super::template read_mem<uint16_t>(space, addr);
if(this->core.trap_state) throw 0;
return ret;
}
inline uint32_t readSpace4(typename super::mem_type_e space, uint64_t addr){
auto ret = super::template read_mem<uint32_t>(space, addr);
if(this->core.trap_state) throw 0;
return ret;
}
inline uint64_t readSpace8(typename super::mem_type_e space, uint64_t addr){
auto ret = super::template read_mem<uint64_t>(space, addr);
if(this->core.trap_state) throw 0;
return ret;
}
inline void writeSpace1(typename super::mem_type_e space, uint64_t addr, uint8_t data){
super::write_mem(space, addr, data);
if(this->core.trap_state) throw 0;
}
inline void writeSpace2(typename super::mem_type_e space, uint64_t addr, uint16_t data){
super::write_mem(space, addr, data);
if(this->core.trap_state) throw 0;
}
inline void writeSpace4(typename super::mem_type_e space, uint64_t addr, uint32_t data){
super::write_mem(space, addr, data);
if(this->core.trap_state) throw 0;
}
inline void writeSpace8(typename super::mem_type_e space, uint64_t addr, uint64_t data){
super::write_mem(space, addr, data);
if(this->core.trap_state) throw 0;
}
template<unsigned W, typename U, typename S = typename std::make_signed<U>::type> template<unsigned W, typename U, typename S = typename std::make_signed<U>::type>
inline S sext(U from) { inline S sext(U from) {
auto mask = (1ULL<<W) - 1; auto mask = (1ULL<<W) - 1;
@ -183,12 +145,15 @@ protected:
} }
inline void process_spawn_blocks() { inline void process_spawn_blocks() {
if(spawn_blocks.size()==0) return;
std::swap(super::ex_info.branch_taken, super::ex_info.hw_branch_taken);
for(auto it = std::begin(spawn_blocks); it!=std::end(spawn_blocks);) for(auto it = std::begin(spawn_blocks); it!=std::end(spawn_blocks);)
if(*it){ if(*it){
(*it)(); (*it)();
++it; ++it;
} else } else
spawn_blocks.erase(it); spawn_blocks.erase(it);
std::swap(super::ex_info.branch_taken, super::ex_info.hw_branch_taken);
} }
<%functions.each{ it.eachLine { %> <%functions.each{ it.eachLine { %>
${it}<%}%> ${it}<%}%>

172
src/iss/debugger/riscv_target_adapter.h
View File

@ -85,7 +85,7 @@ public:
corresponding bytes in avail_buf are 0, otherwise corresponding bytes in avail_buf are 0, otherwise
avail buf is 1 */ avail buf is 1 */
status read_single_register(unsigned int reg_no, std::vector<uint8_t> &buf, status read_single_register(unsigned int reg_no, std::vector<uint8_t> &buf,
std::vector<uint8_t> &avail_buf) override; std::vector<uint8_t> &avail_buf) override;
/* Write one register. buf is 4-byte aligned and it is in target byte /* Write one register. buf is 4-byte aligned and it is in target byte
order */ order */
@ -104,7 +104,7 @@ public:
status process_query(unsigned int &mask, const rp_thread_ref &arg, rp_thread_info &info) override; status process_query(unsigned int &mask, const rp_thread_ref &arg, rp_thread_info &info) override;
status thread_list_query(int first, const rp_thread_ref &arg, std::vector<rp_thread_ref> &result, size_t max_num, status thread_list_query(int first, const rp_thread_ref &arg, std::vector<rp_thread_ref> &result, size_t max_num,
size_t &num, bool &done) override; size_t &num, bool &done) override;
status current_thread_query(rp_thread_ref &thread) override; status current_thread_query(rp_thread_ref &thread) override;
@ -120,12 +120,12 @@ public:
status packetsize_query(std::string &out_buf) override; status packetsize_query(std::string &out_buf) override;
status add_break(int type, uint64_t addr, unsigned int length) override; status add_break(break_type type, uint64_t addr, unsigned int length) override;
status remove_break(int type, uint64_t addr, unsigned int length) override; status remove_break(break_type type, uint64_t addr, unsigned int length) override;
status resume_from_addr(bool step, int sig, uint64_t addr, rp_thread_ref thread, status resume_from_addr(bool step, int sig, uint64_t addr, rp_thread_ref thread,
std::function<void(unsigned)> stop_callback) override; std::function<void(unsigned)> stop_callback) override;
status target_xml_query(std::string &out_buf) override; status target_xml_query(std::string &out_buf) override;
@ -159,8 +159,8 @@ template <typename ARCH> status riscv_target_adapter<ARCH>::is_thread_alive(rp_t
*/ */
template <typename ARCH> template <typename ARCH>
status riscv_target_adapter<ARCH>::thread_list_query(int first, const rp_thread_ref &arg, status riscv_target_adapter<ARCH>::thread_list_query(int first, const rp_thread_ref &arg,
std::vector<rp_thread_ref> &result, size_t max_num, size_t &num, std::vector<rp_thread_ref> &result, size_t max_num, size_t &num,
bool &done) { bool &done) {
if (first == 0) { if (first == 0) {
result.clear(); result.clear();
result.push_back(thread_idx); result.push_back(thread_idx);
@ -193,20 +193,20 @@ status riscv_target_adapter<ARCH>::read_registers(std::vector<uint8_t> &data, st
} }
} }
// work around fill with F type registers // work around fill with F type registers
// if (arch::traits<ARCH>::NUM_REGS < 65) { // if (arch::traits<ARCH>::NUM_REGS < 65) {
// auto reg_width = sizeof(typename arch::traits<ARCH>::reg_t); // auto reg_width = sizeof(typename arch::traits<ARCH>::reg_t);
// for (size_t reg_no = 0; reg_no < 33; ++reg_no) { // for (size_t reg_no = 0; reg_no < 33; ++reg_no) {
// for (size_t j = 0; j < reg_width; ++j) { // for (size_t j = 0; j < reg_width; ++j) {
// data.push_back(0x0); // data.push_back(0x0);
// avail.push_back(0x00); // avail.push_back(0x00);
// } // }
// // if(arch::traits<ARCH>::XLEN < 64) // // if(arch::traits<ARCH>::XLEN < 64)
// // for(unsigned j=0; j<4; ++j){ // // for(unsigned j=0; j<4; ++j){
// // data.push_back(0x0); // // data.push_back(0x0);
// // avail.push_back(0x00); // // avail.push_back(0x00);
// // } // // }
// } // }
// } // }
return Ok; return Ok;
} }
@ -240,7 +240,7 @@ template <typename ARCH> status riscv_target_adapter<ARCH>::write_registers(cons
template <typename ARCH> template <typename ARCH>
status riscv_target_adapter<ARCH>::read_single_register(unsigned int reg_no, std::vector<uint8_t> &data, status riscv_target_adapter<ARCH>::read_single_register(unsigned int reg_no, std::vector<uint8_t> &data,
std::vector<uint8_t> &avail) { std::vector<uint8_t> &avail) {
if (reg_no < 65) { if (reg_no < 65) {
// auto reg_size = arch::traits<ARCH>::reg_bit_width(static_cast<typename // auto reg_size = arch::traits<ARCH>::reg_bit_width(static_cast<typename
// arch::traits<ARCH>::reg_e>(reg_no))/8; // arch::traits<ARCH>::reg_e>(reg_no))/8;
@ -331,34 +331,48 @@ template <typename ARCH> status riscv_target_adapter<ARCH>::packetsize_query(std
return Ok; return Ok;
} }
template <typename ARCH> status riscv_target_adapter<ARCH>::add_break(int type, uint64_t addr, unsigned int length) { template <typename ARCH> status riscv_target_adapter<ARCH>::add_break(break_type type, uint64_t addr, unsigned int length) {
auto saddr = map_addr({iss::access_type::FETCH, iss::address_type::PHYSICAL, 0, addr}); switch(type) {
auto eaddr = map_addr({iss::access_type::FETCH, iss::address_type::PHYSICAL, 0, addr + length}); default:
target_adapter_base::bp_lut.addEntry(++target_adapter_base::bp_count, saddr.val, eaddr.val - saddr.val); return Err;
LOG(TRACE) << "Adding breakpoint with handle " << target_adapter_base::bp_count << " for addr 0x" << std::hex case SW_EXEC:
<< saddr.val << std::dec; case HW_EXEC: {
LOG(TRACE) << "Now having " << target_adapter_base::bp_lut.size() << " breakpoints"; auto saddr = map_addr({iss::access_type::FETCH, iss::address_type::PHYSICAL, 0, addr});
return Ok; auto eaddr = map_addr({iss::access_type::FETCH, iss::address_type::PHYSICAL, 0, addr + length});
} target_adapter_base::bp_lut.addEntry(++target_adapter_base::bp_count, saddr.val, eaddr.val - saddr.val);
LOG(TRACE) << "Adding breakpoint with handle " << target_adapter_base::bp_count << " for addr 0x" << std::hex
template <typename ARCH> status riscv_target_adapter<ARCH>::remove_break(int type, uint64_t addr, unsigned int length) { << saddr.val << std::dec;
auto saddr = map_addr({iss::access_type::FETCH, iss::address_type::PHYSICAL, 0, addr});
unsigned handle = target_adapter_base::bp_lut.getEntry(saddr.val);
if (handle) {
LOG(TRACE) << "Removing breakpoint with handle " << handle << " for addr 0x" << std::hex << saddr.val
<< std::dec;
// TODO: check length of addr range
target_adapter_base::bp_lut.removeEntry(handle);
LOG(TRACE) << "Now having " << target_adapter_base::bp_lut.size() << " breakpoints"; LOG(TRACE) << "Now having " << target_adapter_base::bp_lut.size() << " breakpoints";
return Ok; return Ok;
} }
LOG(TRACE) << "Now having " << target_adapter_base::bp_lut.size() << " breakpoints"; }
return Err; }
template <typename ARCH> status riscv_target_adapter<ARCH>::remove_break(break_type type, uint64_t addr, unsigned int length) {
switch(type) {
default:
return Err;
case SW_EXEC:
case HW_EXEC: {
auto saddr = map_addr({iss::access_type::FETCH, iss::address_type::PHYSICAL, 0, addr});
unsigned handle = target_adapter_base::bp_lut.getEntry(saddr.val);
if (handle) {
LOG(TRACE) << "Removing breakpoint with handle " << handle << " for addr 0x" << std::hex << saddr.val
<< std::dec;
// TODO: check length of addr range
target_adapter_base::bp_lut.removeEntry(handle);
LOG(TRACE) << "Now having " << target_adapter_base::bp_lut.size() << " breakpoints";
return Ok;
}
LOG(TRACE) << "Now having " << target_adapter_base::bp_lut.size() << " breakpoints";
return Err;
}
}
} }
template <typename ARCH> template <typename ARCH>
status riscv_target_adapter<ARCH>::resume_from_addr(bool step, int sig, uint64_t addr, rp_thread_ref thread, status riscv_target_adapter<ARCH>::resume_from_addr(bool step, int sig, uint64_t addr, rp_thread_ref thread,
std::function<void(unsigned)> stop_callback) { std::function<void(unsigned)> stop_callback) {
auto *reg_base = core->get_regs_base_ptr(); auto *reg_base = core->get_regs_base_ptr();
auto reg_width = arch::traits<ARCH>::reg_bit_widths[arch::traits<ARCH>::PC] / 8; auto reg_width = arch::traits<ARCH>::reg_bit_widths[arch::traits<ARCH>::PC] / 8;
auto offset = traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]; auto offset = traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC];
@ -369,42 +383,42 @@ status riscv_target_adapter<ARCH>::resume_from_addr(bool step, int sig, uint64_t
template <typename ARCH> status riscv_target_adapter<ARCH>::target_xml_query(std::string &out_buf) { template <typename ARCH> status riscv_target_adapter<ARCH>::target_xml_query(std::string &out_buf) {
const std::string res{"<?xml version=\"1.0\"?><!DOCTYPE target SYSTEM \"gdb-target.dtd\">" const std::string res{"<?xml version=\"1.0\"?><!DOCTYPE target SYSTEM \"gdb-target.dtd\">"
"<target><architecture>riscv:rv32</architecture>" "<target><architecture>riscv:rv32</architecture>"
//" <feature name=\"org.gnu.gdb.riscv.rv32i\">\n" //" <feature name=\"org.gnu.gdb.riscv.rv32i\">\n"
//" <reg name=\"x0\" bitsize=\"32\" group=\"general\"/>\n" //" <reg name=\"x0\" bitsize=\"32\" group=\"general\"/>\n"
//" <reg name=\"x1\" bitsize=\"32\" group=\"general\"/>\n" //" <reg name=\"x1\" bitsize=\"32\" group=\"general\"/>\n"
//" <reg name=\"x2\" bitsize=\"32\" group=\"general\"/>\n" //" <reg name=\"x2\" bitsize=\"32\" group=\"general\"/>\n"
//" <reg name=\"x3\" bitsize=\"32\" group=\"general\"/>\n" //" <reg name=\"x3\" bitsize=\"32\" group=\"general\"/>\n"
//" <reg name=\"x4\" bitsize=\"32\" group=\"general\"/>\n" //" <reg name=\"x4\" bitsize=\"32\" group=\"general\"/>\n"
//" <reg name=\"x5\" bitsize=\"32\" group=\"general\"/>\n" //" <reg name=\"x5\" bitsize=\"32\" group=\"general\"/>\n"
//" <reg name=\"x6\" bitsize=\"32\" group=\"general\"/>\n" //" <reg name=\"x6\" bitsize=\"32\" group=\"general\"/>\n"
//" <reg name=\"x7\" bitsize=\"32\" group=\"general\"/>\n" //" <reg name=\"x7\" bitsize=\"32\" group=\"general\"/>\n"
//" <reg name=\"x8\" bitsize=\"32\" group=\"general\"/>\n" //" <reg name=\"x8\" bitsize=\"32\" group=\"general\"/>\n"
//" <reg name=\"x9\" bitsize=\"32\" group=\"general\"/>\n" //" <reg name=\"x9\" bitsize=\"32\" group=\"general\"/>\n"
//" <reg name=\"x10\" bitsize=\"32\" group=\"general\"/>\n" //" <reg name=\"x10\" bitsize=\"32\" group=\"general\"/>\n"
//" <reg name=\"x11\" bitsize=\"32\" group=\"general\"/>\n" //" <reg name=\"x11\" bitsize=\"32\" group=\"general\"/>\n"
//" <reg name=\"x12\" bitsize=\"32\" group=\"general\"/>\n" //" <reg name=\"x12\" bitsize=\"32\" group=\"general\"/>\n"
//" <reg name=\"x13\" bitsize=\"32\" group=\"general\"/>\n" //" <reg name=\"x13\" bitsize=\"32\" group=\"general\"/>\n"
//" <reg name=\"x14\" bitsize=\"32\" group=\"general\"/>\n" //" <reg name=\"x14\" bitsize=\"32\" group=\"general\"/>\n"
//" <reg name=\"x15\" bitsize=\"32\" group=\"general\"/>\n" //" <reg name=\"x15\" bitsize=\"32\" group=\"general\"/>\n"
//" <reg name=\"x16\" bitsize=\"32\" group=\"general\"/>\n" //" <reg name=\"x16\" bitsize=\"32\" group=\"general\"/>\n"
//" <reg name=\"x17\" bitsize=\"32\" group=\"general\"/>\n" //" <reg name=\"x17\" bitsize=\"32\" group=\"general\"/>\n"
//" <reg name=\"x18\" bitsize=\"32\" group=\"general\"/>\n" //" <reg name=\"x18\" bitsize=\"32\" group=\"general\"/>\n"
//" <reg name=\"x19\" bitsize=\"32\" group=\"general\"/>\n" //" <reg name=\"x19\" bitsize=\"32\" group=\"general\"/>\n"
//" <reg name=\"x20\" bitsize=\"32\" group=\"general\"/>\n" //" <reg name=\"x20\" bitsize=\"32\" group=\"general\"/>\n"
//" <reg name=\"x21\" bitsize=\"32\" group=\"general\"/>\n" //" <reg name=\"x21\" bitsize=\"32\" group=\"general\"/>\n"
//" <reg name=\"x22\" bitsize=\"32\" group=\"general\"/>\n" //" <reg name=\"x22\" bitsize=\"32\" group=\"general\"/>\n"
//" <reg name=\"x23\" bitsize=\"32\" group=\"general\"/>\n" //" <reg name=\"x23\" bitsize=\"32\" group=\"general\"/>\n"
//" <reg name=\"x24\" bitsize=\"32\" group=\"general\"/>\n" //" <reg name=\"x24\" bitsize=\"32\" group=\"general\"/>\n"
//" <reg name=\"x25\" bitsize=\"32\" group=\"general\"/>\n" //" <reg name=\"x25\" bitsize=\"32\" group=\"general\"/>\n"
//" <reg name=\"x26\" bitsize=\"32\" group=\"general\"/>\n" //" <reg name=\"x26\" bitsize=\"32\" group=\"general\"/>\n"
//" <reg name=\"x27\" bitsize=\"32\" group=\"general\"/>\n" //" <reg name=\"x27\" bitsize=\"32\" group=\"general\"/>\n"
//" <reg name=\"x28\" bitsize=\"32\" group=\"general\"/>\n" //" <reg name=\"x28\" bitsize=\"32\" group=\"general\"/>\n"
//" <reg name=\"x29\" bitsize=\"32\" group=\"general\"/>\n" //" <reg name=\"x29\" bitsize=\"32\" group=\"general\"/>\n"
//" <reg name=\"x30\" bitsize=\"32\" group=\"general\"/>\n" //" <reg name=\"x30\" bitsize=\"32\" group=\"general\"/>\n"
//" <reg name=\"x31\" bitsize=\"32\" group=\"general\"/>\n" //" <reg name=\"x31\" bitsize=\"32\" group=\"general\"/>\n"
//" </feature>\n" //" </feature>\n"
"</target>"}; "</target>"};
out_buf = res; out_buf = res;
return Ok; return Ok;
} }

4
src/sysc/core_complex.h
View File

@ -69,7 +69,7 @@ struct core_trace;
class core_complex : public sc_core::sc_module, public scc::traceable { class core_complex : public sc_core::sc_module, public scc::traceable {
public: public:
tlm::scc::initiator_mixin<tlm::scc::scv::tlm_rec_initiator_socket<32>> initiator{"intor"}; tlm::scc::initiator_mixin<tlm::tlm_initiator_socket<32>> initiator{"intor"};
sc_core::sc_in<bool> rst_i{"rst_i"}; sc_core::sc_in<bool> rst_i{"rst_i"};
@ -84,7 +84,7 @@ public:
#ifndef CWR_SYSTEMC #ifndef CWR_SYSTEMC
sc_core::sc_in<sc_core::sc_time> clk_i{"clk_i"}; sc_core::sc_in<sc_core::sc_time> clk_i{"clk_i"};
sc_core::sc_port<tlm::tlm_peek_if<uint64_t>, 1, sc_core::SC_ZERO_OR_MORE_BOUND> mtime_o; sc_core::sc_port<tlm::tlm_peek_if<uint64_t>, 1, sc_core::SC_ZERO_OR_MORE_BOUND> mtime_o{"mtime_o"};
cci::cci_param<std::string> elf_file{"elf_file", ""}; cci::cci_param<std::string> elf_file{"elf_file", ""};

41
src/vm/interp/vm_tgc_c.cpp
View File

@ -131,44 +131,6 @@ protected:
using coro_t = boost::coroutines2::coroutine<void>::pull_type; using coro_t = boost::coroutines2::coroutine<void>::pull_type;
std::vector<coro_t> spawn_blocks; std::vector<coro_t> spawn_blocks;
template<typename T>
T& pc_assign(T& val){super::ex_info.branch_taken=true; return val;}
inline uint8_t readSpace1(typename super::mem_type_e space, uint64_t addr){
auto ret = super::template read_mem<uint8_t>(space, addr);
if(this->core.trap_state) throw 0;
return ret;
}
inline uint16_t readSpace2(typename super::mem_type_e space, uint64_t addr){
auto ret = super::template read_mem<uint16_t>(space, addr);
if(this->core.trap_state) throw 0;
return ret;
}
inline uint32_t readSpace4(typename super::mem_type_e space, uint64_t addr){
auto ret = super::template read_mem<uint32_t>(space, addr);
if(this->core.trap_state) throw 0;
return ret;
}
inline uint64_t readSpace8(typename super::mem_type_e space, uint64_t addr){
auto ret = super::template read_mem<uint64_t>(space, addr);
if(this->core.trap_state) throw 0;
return ret;
}
inline void writeSpace1(typename super::mem_type_e space, uint64_t addr, uint8_t data){
super::write_mem(space, addr, data);
if(this->core.trap_state) throw 0;
}
inline void writeSpace2(typename super::mem_type_e space, uint64_t addr, uint16_t data){
super::write_mem(space, addr, data);
if(this->core.trap_state) throw 0;
}
inline void writeSpace4(typename super::mem_type_e space, uint64_t addr, uint32_t data){
super::write_mem(space, addr, data);
if(this->core.trap_state) throw 0;
}
inline void writeSpace8(typename super::mem_type_e space, uint64_t addr, uint64_t data){
super::write_mem(space, addr, data);
if(this->core.trap_state) throw 0;
}
template<unsigned W, typename U, typename S = typename std::make_signed<U>::type> template<unsigned W, typename U, typename S = typename std::make_signed<U>::type>
inline S sext(U from) { inline S sext(U from) {
auto mask = (1ULL<<W) - 1; auto mask = (1ULL<<W) - 1;
@ -177,12 +139,15 @@ protected:
} }
inline void process_spawn_blocks() { inline void process_spawn_blocks() {
if(spawn_blocks.size()==0) return;
std::swap(super::ex_info.branch_taken, super::ex_info.hw_branch_taken);
for(auto it = std::begin(spawn_blocks); it!=std::end(spawn_blocks);) for(auto it = std::begin(spawn_blocks); it!=std::end(spawn_blocks);)
if(*it){ if(*it){
(*it)(); (*it)();
++it; ++it;
} else } else
spawn_blocks.erase(it); spawn_blocks.erase(it);
std::swap(super::ex_info.branch_taken, super::ex_info.hw_branch_taken);
} }
private: private: