Changed SystemC model to model a platform in a system. Added dedicated
UART Terminal connected via tlm_signals
This commit is contained in:
30
riscv.sc/incl/sysc/General/system.h
Normal file
30
riscv.sc/incl/sysc/General/system.h
Normal file
@ -0,0 +1,30 @@
|
||||
/*
|
||||
* system.h
|
||||
*
|
||||
* Created on: 11.07.2018
|
||||
* Author: eyck
|
||||
*/
|
||||
|
||||
#ifndef __SYSC_GENERAL_SYSTEM_H_
|
||||
#define __SYSC_GENERAL_SYSTEM_H_
|
||||
|
||||
#include "sysc/SiFive/platform.h"
|
||||
#include "sysc/General/terminal.h"
|
||||
#include <systemc>
|
||||
|
||||
namespace sysc {
|
||||
|
||||
class system: sc_core::sc_module {
|
||||
public:
|
||||
system(sc_core::sc_module_name nm);
|
||||
virtual ~system();
|
||||
|
||||
sc_core::sc_vector<tlm::tlm_signal<sc_dt::sc_logic>> s_gpio;
|
||||
|
||||
private:
|
||||
sysc::platform i_platform;
|
||||
sysc::terminal i_terminal;
|
||||
};
|
||||
|
||||
}
|
||||
#endif /* __SYSC_GENERAL_SYSTEM_H_ */
|
42
riscv.sc/incl/sysc/General/terminal.h
Normal file
42
riscv.sc/incl/sysc/General/terminal.h
Normal file
@ -0,0 +1,42 @@
|
||||
/*
|
||||
* terminal.h
|
||||
*
|
||||
* Created on: 07.07.2018
|
||||
* Author: eyck
|
||||
*/
|
||||
|
||||
#ifndef RISCV_SC_INCL_SYSC_GENERAL_TERMINAL_H_
|
||||
#define RISCV_SC_INCL_SYSC_GENERAL_TERMINAL_H_
|
||||
|
||||
#include "scc/signal_target_mixin.h"
|
||||
#include "scc/signal_initiator_mixin.h"
|
||||
#include "tlm/tlm_signal.h"
|
||||
#include "cci_configuration"
|
||||
#include <sysc/kernel/sc_module.h>
|
||||
#include <memory>
|
||||
|
||||
namespace sysc {
|
||||
class WsHandler;
|
||||
|
||||
class terminal: public sc_core::sc_module {
|
||||
public:
|
||||
scc::tlm_signal_logic_out tx_o;
|
||||
scc::tlm_signal_logic_in rx_i;
|
||||
|
||||
terminal();
|
||||
|
||||
terminal(const sc_core::sc_module_name& nm);
|
||||
|
||||
virtual ~terminal();
|
||||
|
||||
cci::cci_param<bool> write_to_ws;
|
||||
|
||||
protected:
|
||||
std::vector<uint8_t> queue;
|
||||
void receive(tlm::tlm_signal_gp<sc_dt::sc_logic>& gp, sc_core::sc_time& delay);
|
||||
std::shared_ptr<sysc::WsHandler> handler;
|
||||
sc_core::sc_time last_tx_start=sc_core::SC_ZERO_TIME;
|
||||
};
|
||||
}
|
||||
|
||||
#endif /* RISCV_SC_INCL_SYSC_GENERAL_TERMINAL_H_ */
|
Reference in New Issue
Block a user