DBT-RISE/DBT-RISE-TGC
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updates asmjit template, removes lots of comments from IR

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This commit is contained in:
Eyck-Alexander Jentzsch
2025-04-28 15:04:18 +02:00
parent 1afd77a942
commit fe3ed49519
2 changed files with 59 additions and 135 deletions
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71
gen_input/templates/asmjit/CORENAME.cpp.gtl
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@ -40,7 +40,11 @@
#include <iss/instruction_decoder.h>
<%def fcsr = registers.find {it.name=='FCSR'}
if(fcsr != null) {%>
#include <vm/fp_functions.h><%}%>
#include <vm/fp_functions.h><%}
def aes = functions.find { it.contains('aes') }
if(aes != null) {%>
#include <vm/aes_sbox.h>
<%}%>
#ifndef FMT_HEADER_ONLY
#define FMT_HEADER_ONLY
#endif
@ -49,6 +53,22 @@ if(fcsr != null) {%>
#include <array>
#include <iss/debugger/riscv_target_adapter.h>
#ifndef _MSC_VER
using int128_t = __int128;
using uint128_t = unsigned __int128;
namespace std {
template <> struct make_unsigned<__int128> { typedef unsigned __int128 type; };
template <> class __make_unsigned_selector<__int128 unsigned, false, false> {
public:
typedef unsigned __int128 __type;
};
template <> struct is_signed<int128_t> { static constexpr bool value = true; };
template <> struct is_signed<uint128_t> { static constexpr bool value = false; };
template <> struct is_unsigned<int128_t> { static constexpr bool value = false; };
template <> struct is_unsigned<uint128_t> { static constexpr bool value = true; };
} // namespace std
#endif
namespace iss {
namespace asmjit {
@ -116,38 +136,14 @@ protected:
auto sign_mask = 1ULL<<(W-1);
return (from & mask) | ((from & sign_mask) ? ~mask : 0);
}
inline void raise(uint16_t trap_id, uint16_t cause){
auto trap_val = 0x80ULL << 24 | (cause << 16) | trap_id;
this->core.reg.trap_state = trap_val;
}
<%functions.each{ it.eachLine { %>
${it}<%}
}
if(fcsr != null) {%>
x86_reg_t NaNBox16(jit_holder& jh , x86_reg_t NaNBox16_val){
x86::Compiler& cc = jh.cc;
if(static_cast<uint32_t>(traits::FLEN) == 16)
return gen_ext(cc, NaNBox16_val, traits::FLEN, false);
else {
auto box = gen_operation(cc, bnot, (gen_ext(cc, 0, traits::FLEN, false)));
return gen_ext(cc, (gen_operation(jh.cc, bor, gen_ext(jh.cc, gen_operation(jh.cc, shl, box, 16), traits::FLEN, false), gen_ext(jh.cc, NaNBox16_val, traits::FLEN, false))), traits::FLEN, false);
}
}
x86_reg_t NaNBox32(jit_holder& jh , x86_reg_t NaNBox32_val){
x86::Compiler& cc = jh.cc;
if(static_cast<uint32_t>(traits::FLEN) == 32)
return gen_ext(cc, NaNBox32_val, traits::FLEN, false);
else {
auto box = gen_operation(cc, bnot, (gen_ext(cc, 0, /* we need to shift for 32 so need larger dt*/ 64, false)));
return gen_ext(cc, (gen_operation(jh.cc, bor, gen_ext(jh.cc, gen_operation(jh.cc, shl, box, 32), traits::FLEN, false), gen_ext(jh.cc, NaNBox32_val, traits::FLEN, false))), traits::FLEN, false);
}
}
x86_reg_t NaNBox64(jit_holder& jh , x86_reg_t NaNBox64_val){
x86::Compiler& cc = jh.cc;
if(static_cast<uint32_t>(traits::FLEN) == 64)
return gen_ext(cc, NaNBox64_val, traits::FLEN, false);
else {
auto box = gen_operation(cc, bnot, (gen_ext(cc, 0, /* we need to shift for 32 so need larger dt*/ 128, false)));
return gen_ext(cc, (gen_operation(jh.cc, bor, gen_ext(jh.cc, gen_operation(jh.cc, shl, box, 64), traits::FLEN, false), gen_ext(jh.cc, NaNBox64_val, traits::FLEN, false))), traits::FLEN, false);
}
}
<%}%>
}%>
private:
/****************************************************************************
* start opcode definitions
@ -195,7 +191,6 @@ private:
mov(cc, jh.next_pc, pc.val);
gen_instr_prologue(jh);
cc.comment("//behavior:");
/*generate behavior*/
<%instr.behavior.eachLine{%>${it}
<%}%>
@ -226,7 +221,6 @@ private:
pc = pc + ((instr & 3) == 3 ? 4 : 2);
mov(cc, jh.next_pc, pc.val);
gen_instr_prologue(jh);
cc.comment("//behavior:");
gen_raise(jh, 0, 2);
gen_sync(jh, POST_SYNC, instr_descr.size());
gen_instr_epilogue(jh);
@ -272,24 +266,25 @@ template <typename ARCH>
void vm_impl<ARCH>::gen_instr_prologue(jit_holder& jh) {
auto& cc = jh.cc;
cc.comment("//gen_instr_prologue");
x86_reg_t current_trap_state = get_reg_for(cc, traits::TRAP_STATE);
mov(cc, current_trap_state, get_ptr_for(jh, traits::TRAP_STATE));
mov(cc, get_ptr_for(jh, traits::PENDING_TRAP), current_trap_state);
cc.comment("//Instruction prologue end");
}
template <typename ARCH>
void vm_impl<ARCH>::gen_instr_epilogue(jit_holder& jh) {
auto& cc = jh.cc;
cc.comment("//gen_instr_epilogue");
cc.comment("//Instruction epilogue begin");
x86_reg_t current_trap_state = get_reg_for(cc, traits::TRAP_STATE);
mov(cc, current_trap_state, get_ptr_for(jh, traits::TRAP_STATE));
cmp(cc, current_trap_state, 0);
cc.jne(jh.trap_entry);
cc.inc(get_ptr_for(jh, traits::ICOUNT));
cc.inc(get_ptr_for(jh, traits::CYCLE));
cc.comment("//Instruction epilogue end");
}
template <typename ARCH>
void vm_impl<ARCH>::gen_block_prologue(jit_holder& jh){
@ -301,7 +296,7 @@ void vm_impl<ARCH>::gen_block_prologue(jit_holder& jh){
template <typename ARCH>
void vm_impl<ARCH>::gen_block_epilogue(jit_holder& jh){
x86::Compiler& cc = jh.cc;
cc.comment("//gen_block_epilogue");
cc.comment("//block epilogue begin");
cc.ret(jh.next_pc);
cc.bind(jh.trap_entry);
@ -313,7 +308,6 @@ void vm_impl<ARCH>::gen_block_epilogue(jit_holder& jh){
x86::Gp current_pc = get_reg_for_Gp(cc, traits::PC);
mov(cc, current_pc, get_ptr_for(jh, traits::PC));
cc.comment("//enter trap call;");
InvokeNode* call_enter_trap;
cc.invoke(&call_enter_trap, &enter_trap, FuncSignature::build<uint64_t, void*, uint64_t, uint64_t, uint64_t>());
call_enter_trap->setArg(0, jh.arch_if_ptr);
@ -331,7 +325,6 @@ void vm_impl<ARCH>::gen_block_epilogue(jit_holder& jh){
template <typename ARCH>
inline void vm_impl<ARCH>::gen_raise(jit_holder& jh, uint16_t trap_id, uint16_t cause) {
auto& cc = jh.cc;
cc.comment("//gen_raise");
auto tmp1 = get_reg_for(cc, traits::TRAP_STATE);
mov(cc, tmp1, 0x80ULL << 24 | (cause << 16) | trap_id);
mov(cc, get_ptr_for(jh, traits::TRAP_STATE), tmp1);