Initial setup
This commit is contained in:
parent
f357e563f2
commit
fd2e40bfd2
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@ -55,6 +55,7 @@ set(LIB_SOURCES
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#src/vm/llvm/vm_rv64i.cpp
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#src/vm/llvm/vm_rv64gc.cpp
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src/vm/tcc/vm_mnrv32.cpp
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src/vm/interp/vm_mnrv32.cpp
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src/plugin/instruction_count.cpp
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src/plugin/cycle_estimate.cpp)
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@ -0,0 +1,229 @@
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/*******************************************************************************
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* Copyright (C) 2020 MINRES Technologies GmbH
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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*******************************************************************************/
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#include <iss/arch/${coreDef.name.toLowerCase()}.h>
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#include <iss/arch/riscv_hart_msu_vp.h>
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#include <iss/debugger/gdb_session.h>
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#include <iss/debugger/server.h>
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#include <iss/iss.h>
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#include <iss/interp/vm_base.h>
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#include <util/logging.h>
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#include <sstream>
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#ifndef FMT_HEADER_ONLY
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#define FMT_HEADER_ONLY
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#endif
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#include <fmt/format.h>
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#include <array>
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#include <iss/debugger/riscv_target_adapter.h>
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namespace iss {
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namespace interp {
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namespace ${coreDef.name.toLowerCase()} {
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using namespace iss::arch;
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using namespace iss::debugger;
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template <typename ARCH> class vm_impl : public vm::interp::vm_base<ARCH> {
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public:
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using super = typename vm::interp::vm_base<ARCH>;
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using virt_addr_t = typename super::virt_addr_t;
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using phys_addr_t = typename super::phys_addr_t;
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using code_word_t = typename super::code_word_t;
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using addr_t = typename super::addr_t;
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vm_impl();
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vm_impl(ARCH &core, unsigned core_id = 0, unsigned cluster_id = 0);
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void enableDebug(bool enable) { super::sync_exec = super::ALL_SYNC; }
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target_adapter_if *accquire_target_adapter(server_if *srv) override {
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debugger_if::dbg_enabled = true;
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if (vm::interp::vm_base<ARCH>::tgt_adapter == nullptr)
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vm::interp::vm_base<ARCH>::tgt_adapter = new riscv_target_adapter<ARCH>(srv, this->get_arch());
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return vm::interp::vm_base<ARCH>::tgt_adapter;
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}
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protected:
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using this_class = vm_impl<ARCH>;
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using compile_ret_t = virt_addr_t;
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using compile_func = compile_ret_t (this_class::*)(virt_addr_t &pc, code_word_t instr);
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inline const char *name(size_t index){return traits<ARCH>::reg_aliases.at(index);}
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virt_addr_t execute_single_inst(virt_addr_t pc) override;
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// some compile time constants
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// enum { MASK16 = 0b1111110001100011, MASK32 = 0b11111111111100000111000001111111 };
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enum { MASK16 = 0b1111111111111111, MASK32 = 0b11111111111100000111000001111111 };
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enum { EXTR_MASK16 = MASK16 >> 2, EXTR_MASK32 = MASK32 >> 2 };
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enum { LUT_SIZE = 1 << util::bit_count(EXTR_MASK32), LUT_SIZE_C = 1 << util::bit_count(EXTR_MASK16) };
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std::array<compile_func, LUT_SIZE> lut;
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std::array<compile_func, LUT_SIZE_C> lut_00, lut_01, lut_10;
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std::array<compile_func, LUT_SIZE> lut_11;
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std::array<compile_func *, 4> qlut;
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std::array<const uint32_t, 4> lutmasks = {{EXTR_MASK16, EXTR_MASK16, EXTR_MASK16, EXTR_MASK32}};
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void expand_bit_mask(int pos, uint32_t mask, uint32_t value, uint32_t valid, uint32_t idx, compile_func lut[],
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compile_func f) {
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if (pos < 0) {
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lut[idx] = f;
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} else {
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auto bitmask = 1UL << pos;
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if ((mask & bitmask) == 0) {
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expand_bit_mask(pos - 1, mask, value, valid, idx, lut, f);
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} else {
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if ((valid & bitmask) == 0) {
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expand_bit_mask(pos - 1, mask, value, valid, (idx << 1), lut, f);
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expand_bit_mask(pos - 1, mask, value, valid, (idx << 1) + 1, lut, f);
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} else {
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auto new_val = idx << 1;
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if ((value & bitmask) != 0) new_val++;
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expand_bit_mask(pos - 1, mask, value, valid, new_val, lut, f);
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}
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}
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}
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}
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inline uint32_t extract_fields(uint32_t val) { return extract_fields(29, val >> 2, lutmasks[val & 0x3], 0); }
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uint32_t extract_fields(int pos, uint32_t val, uint32_t mask, uint32_t lut_val) {
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if (pos >= 0) {
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auto bitmask = 1UL << pos;
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if ((mask & bitmask) == 0) {
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lut_val = extract_fields(pos - 1, val, mask, lut_val);
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} else {
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auto new_val = lut_val << 1;
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if ((val & bitmask) != 0) new_val++;
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lut_val = extract_fields(pos - 1, val, mask, new_val);
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}
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}
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return lut_val;
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}
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private:
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/****************************************************************************
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* start opcode definitions
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****************************************************************************/
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struct InstructionDesriptor {
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size_t length;
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uint32_t value;
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uint32_t mask;
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compile_func op;
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};
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const std::array<InstructionDesriptor, ${instructions.size}> instr_descr = {{
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/* entries are: size, valid value, valid mask, function ptr */<%instructions.each{instr -> %>
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/* instruction ${instr.instruction.name} */
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{${instr.length}, ${instr.value}, ${instr.mask}, &this_class::__${generator.functionName(instr.name)}},<%}%>
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}};
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/* instruction definitions */<%instructions.eachWithIndex{instr, idx -> %>
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/* instruction ${idx}: ${instr.name} */
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compile_ret_t __${generator.functionName(instr.name)}(virt_addr_t& pc, code_word_t instr){<%instr.code.eachLine{%>
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${it}<%}%>
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}
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<%}%>
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/****************************************************************************
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* end opcode definitions
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****************************************************************************/
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compile_ret_t illegal_intruction(virt_addr_t &pc, code_word_t instr) {
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pc = pc + ((instr & 3) == 3 ? 4 : 2);
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return pc;
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}
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};
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template <typename CODE_WORD> void debug_fn(CODE_WORD insn) {
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volatile CODE_WORD x = insn;
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insn = 2 * x;
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}
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template <typename ARCH> vm_impl<ARCH>::vm_impl() { this(new ARCH()); }
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template <typename ARCH>
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vm_impl<ARCH>::vm_impl(ARCH &core, unsigned core_id, unsigned cluster_id)
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: vm::interp::vm_base<ARCH>(core, core_id, cluster_id) {
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qlut[0] = lut_00.data();
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qlut[1] = lut_01.data();
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qlut[2] = lut_10.data();
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qlut[3] = lut_11.data();
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for (auto instr : instr_descr) {
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auto quantrant = instr.value & 0x3;
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expand_bit_mask(29, lutmasks[quantrant], instr.value >> 2, instr.mask >> 2, 0, qlut[quantrant], instr.op);
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}
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}
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template <typename ARCH>
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typename vm::interp::vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_single_inst(virt_addr_t pc) {
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// we fetch at max 4 byte, alignment is 2
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enum {TRAP_ID=1<<16};
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code_word_t insn = 0;
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const typename traits<ARCH>::addr_t upper_bits = ~traits<ARCH>::PGMASK;
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phys_addr_t paddr(pc);
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auto *const data = (uint8_t *)&insn;
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paddr = this->core.v2p(pc);
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if ((pc.val & upper_bits) != ((pc.val + 2) & upper_bits)) { // we may cross a page boundary
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auto res = this->core.read(paddr, 2, data);
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if (res != iss::Ok) throw trap_access(TRAP_ID, pc.val);
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if ((insn & 0x3) == 0x3) { // this is a 32bit instruction
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res = this->core.read(this->core.v2p(pc + 2), 2, data + 2);
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}
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} else {
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auto res = this->core.read(paddr, 4, data);
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if (res != iss::Ok) throw trap_access(TRAP_ID, pc.val);
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}
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if (insn == 0x0000006f || (insn&0xffff)==0xa001) throw simulation_stopped(0); // 'J 0' or 'C.J 0'
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// curr pc on stack
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auto lut_val = extract_fields(insn);
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auto f = qlut[insn & 0x3][lut_val];
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if (f == nullptr) {
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f = &this_class::illegal_intruction;
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}
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return (this->*f)(pc, insn);
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}
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} // namespace mnrv32
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template <>
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std::unique_ptr<vm_if> create<arch::${coreDef.name.toLowerCase()}>(arch::${coreDef.name.toLowerCase()} *core, unsigned short port, bool dump) {
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auto ret = new ${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*core, dump);
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if (port != 0) debugger::server<debugger::gdb_session>::run_server(ret, port);
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return std::unique_ptr<vm_if>(ret);
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}
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}
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} // namespace iss
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{
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"${coreDef.name}" : [<%instructions.eachWithIndex{instr,index -> %>${index==0?"":","}
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{
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"name" : "${instr.name}",
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"size" : ${instr.length},
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"delay" : ${generator.hasAttribute(instr.instruction, com.minres.coredsl.coreDsl.InstrAttribute.COND)?[1,1]:1}
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}<%}%>
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]
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}
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@ -0,0 +1,221 @@
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/*******************************************************************************
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* Copyright (C) 2017, 2018 MINRES Technologies GmbH
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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*******************************************************************************/
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<%
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import com.minres.coredsl.coreDsl.Register
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import com.minres.coredsl.coreDsl.RegisterFile
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import com.minres.coredsl.coreDsl.RegisterAlias
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def getTypeSize(size){
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if(size > 32) 64 else if(size > 16) 32 else if(size > 8) 16 else 8
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}
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def getOriginalName(reg){
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if( reg.original instanceof RegisterFile) {
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if( reg.index != null ) {
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return reg.original.name+generator.generateHostCode(reg.index)
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} else {
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return reg.original.name
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}
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} else if(reg.original instanceof Register){
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return reg.original.name
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}
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}
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def getRegisterNames(){
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def regNames = []
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allRegs.each { reg ->
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if( reg instanceof RegisterFile) {
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(reg.range.right..reg.range.left).each{
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regNames+=reg.name.toLowerCase()+it
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}
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} else if(reg instanceof Register){
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regNames+=reg.name.toLowerCase()
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}
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}
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return regNames
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}
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def getRegisterAliasNames(){
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def regMap = allRegs.findAll{it instanceof RegisterAlias }.collectEntries {[getOriginalName(it), it.name]}
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return allRegs.findAll{it instanceof Register || it instanceof RegisterFile}.collect{reg ->
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if( reg instanceof RegisterFile) {
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return (reg.range.right..reg.range.left).collect{ (regMap[reg.name]?:regMap[reg.name+it]?:reg.name.toLowerCase()+it).toLowerCase() }
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} else if(reg instanceof Register){
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regMap[reg.name]?:reg.name.toLowerCase()
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}
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}.flatten()
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}
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%>
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#ifndef _${coreDef.name.toUpperCase()}_H_
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#define _${coreDef.name.toUpperCase()}_H_
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#include <array>
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#include <iss/arch/traits.h>
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#include <iss/arch_if.h>
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#include <iss/vm_if.h>
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namespace iss {
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namespace arch {
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struct ${coreDef.name.toLowerCase()};
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template <> struct traits<${coreDef.name.toLowerCase()}> {
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constexpr static char const* const core_type = "${coreDef.name}";
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static constexpr std::array<const char*, ${getRegisterNames().size}> reg_names{
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{"${getRegisterNames().join("\", \"")}"}};
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static constexpr std::array<const char*, ${getRegisterAliasNames().size}> reg_aliases{
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{"${getRegisterAliasNames().join("\", \"")}"}};
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enum constants {${coreDef.constants.collect{c -> c.name+"="+c.value}.join(', ')}};
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constexpr static unsigned FP_REGS_SIZE = ${coreDef.constants.find {it.name=='FLEN'}?.value?:0};
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enum reg_e {<%
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allRegs.each { reg ->
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if( reg instanceof RegisterFile) {
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(reg.range.right..reg.range.left).each{%>
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${reg.name}${it},<%
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}
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} else if(reg instanceof Register){ %>
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${reg.name},<%
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}
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}%>
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NUM_REGS,
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NEXT_${pc.name}=NUM_REGS,
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TRAP_STATE,
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PENDING_TRAP,
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MACHINE_STATE,
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LAST_BRANCH,
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ICOUNT<%
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allRegs.each { reg ->
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if(reg instanceof RegisterAlias){ def aliasname=getOriginalName(reg)%>,
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${reg.name} = ${aliasname}<%
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}
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}%>
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};
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using reg_t = uint${regDataWidth}_t;
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using addr_t = uint${addrDataWidth}_t;
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using code_word_t = uint${addrDataWidth}_t; //TODO: check removal
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using virt_addr_t = iss::typed_addr_t<iss::address_type::VIRTUAL>;
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using phys_addr_t = iss::typed_addr_t<iss::address_type::PHYSICAL>;
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static constexpr std::array<const uint32_t, ${regSizes.size}> reg_bit_widths{
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{${regSizes.join(",")}}};
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static constexpr std::array<const uint32_t, ${regOffsets.size}> reg_byte_offsets{
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{${regOffsets.join(",")}}};
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static const uint64_t addr_mask = (reg_t(1) << (XLEN - 1)) | ((reg_t(1) << (XLEN - 1)) - 1);
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enum sreg_flag_e { FLAGS };
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enum mem_type_e { ${allSpaces.collect{s -> s.name}.join(', ')} };
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};
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struct ${coreDef.name.toLowerCase()}: public arch_if {
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using virt_addr_t = typename traits<${coreDef.name.toLowerCase()}>::virt_addr_t;
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using phys_addr_t = typename traits<${coreDef.name.toLowerCase()}>::phys_addr_t;
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using reg_t = typename traits<${coreDef.name.toLowerCase()}>::reg_t;
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using addr_t = typename traits<${coreDef.name.toLowerCase()}>::addr_t;
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${coreDef.name.toLowerCase()}();
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~${coreDef.name.toLowerCase()}();
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void reset(uint64_t address=0) override;
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uint8_t* get_regs_base_ptr() override;
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/// deprecated
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void get_reg(short idx, std::vector<uint8_t>& value) override {}
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void set_reg(short idx, const std::vector<uint8_t>& value) override {}
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/// deprecated
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bool get_flag(int flag) override {return false;}
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void set_flag(int, bool value) override {};
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/// deprecated
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void update_flags(operations op, uint64_t opr1, uint64_t opr2) override {};
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inline uint64_t get_icount() { return reg.icount; }
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|
||||
inline bool should_stop() { return interrupt_sim; }
|
||||
|
||||
inline phys_addr_t v2p(const iss::addr_t& addr){
|
||||
if (addr.space != traits<${coreDef.name.toLowerCase()}>::MEM || addr.type == iss::address_type::PHYSICAL ||
|
||||
addr_mode[static_cast<uint16_t>(addr.access)&0x3]==address_type::PHYSICAL) {
|
||||
return phys_addr_t(addr.access, addr.space, addr.val&traits<${coreDef.name.toLowerCase()}>::addr_mask);
|
||||
} else
|
||||
return virt2phys(addr);
|
||||
}
|
||||
|
||||
virtual phys_addr_t virt2phys(const iss::addr_t& addr);
|
||||
|
||||
virtual iss::sync_type needed_sync() const { return iss::NO_SYNC; }
|
||||
|
||||
inline uint32_t get_last_branch() { return reg.last_branch; }
|
||||
|
||||
protected:
|
||||
struct ${coreDef.name}_regs {<%
|
||||
allRegs.each { reg ->
|
||||
if( reg instanceof RegisterFile) {
|
||||
(reg.range.right..reg.range.left).each{%>
|
||||
uint${generator.getSize(reg)}_t ${reg.name}${it} = 0;<%
|
||||
}
|
||||
} else if(reg instanceof Register){ %>
|
||||
uint${generator.getSize(reg)}_t ${reg.name} = 0;<%
|
||||
}
|
||||
}%>
|
||||
uint${generator.getSize(pc)}_t NEXT_${pc.name} = 0;
|
||||
uint32_t trap_state = 0, pending_trap = 0, machine_state = 0, last_branch = 0;
|
||||
uint64_t icount = 0;
|
||||
} reg;
|
||||
|
||||
std::array<address_type, 4> addr_mode;
|
||||
|
||||
bool interrupt_sim=false;
|
||||
<%
|
||||
def fcsr = allRegs.find {it.name=='FCSR'}
|
||||
if(fcsr != null) {%>
|
||||
uint${generator.getSize(fcsr)}_t get_fcsr(){return reg.FCSR;}
|
||||
void set_fcsr(uint${generator.getSize(fcsr)}_t val){reg.FCSR = val;}
|
||||
<%} else { %>
|
||||
uint32_t get_fcsr(){return 0;}
|
||||
void set_fcsr(uint32_t val){}
|
||||
<%}%>
|
||||
};
|
||||
|
||||
}
|
||||
}
|
||||
#endif /* _${coreDef.name.toUpperCase()}_H_ */
|
||||
|
|
@ -0,0 +1,117 @@
|
|||
/*******************************************************************************
|
||||
* Copyright (C) 2017, 2018 MINRES Technologies GmbH
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of the copyright holder nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*******************************************************************************/
|
||||
<%
|
||||
import com.minres.coredsl.coreDsl.Register
|
||||
import com.minres.coredsl.coreDsl.RegisterFile
|
||||
import com.minres.coredsl.coreDsl.RegisterAlias
|
||||
def getOriginalName(reg){
|
||||
if( reg.original instanceof RegisterFile) {
|
||||
if( reg.index != null ) {
|
||||
return reg.original.name+generator.generateHostCode(reg.index)
|
||||
} else {
|
||||
return reg.original.name
|
||||
}
|
||||
} else if(reg.original instanceof Register){
|
||||
return reg.original.name
|
||||
}
|
||||
}
|
||||
def getRegisterNames(){
|
||||
def regNames = []
|
||||
allRegs.each { reg ->
|
||||
if( reg instanceof RegisterFile) {
|
||||
(reg.range.right..reg.range.left).each{
|
||||
regNames+=reg.name.toLowerCase()+it
|
||||
}
|
||||
} else if(reg instanceof Register){
|
||||
regNames+=reg.name.toLowerCase()
|
||||
}
|
||||
}
|
||||
return regNames
|
||||
}
|
||||
def getRegisterAliasNames(){
|
||||
def regMap = allRegs.findAll{it instanceof RegisterAlias }.collectEntries {[getOriginalName(it), it.name]}
|
||||
return allRegs.findAll{it instanceof Register || it instanceof RegisterFile}.collect{reg ->
|
||||
if( reg instanceof RegisterFile) {
|
||||
return (reg.range.right..reg.range.left).collect{ (regMap[reg.name]?:regMap[reg.name+it]?:reg.name.toLowerCase()+it).toLowerCase() }
|
||||
} else if(reg instanceof Register){
|
||||
regMap[reg.name]?:reg.name.toLowerCase()
|
||||
}
|
||||
}.flatten()
|
||||
}
|
||||
%>
|
||||
#include "util/ities.h"
|
||||
#include <util/logging.h>
|
||||
|
||||
#include <elfio/elfio.hpp>
|
||||
#include <iss/arch/${coreDef.name.toLowerCase()}.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
#include <ihex.h>
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#include <cstdio>
|
||||
#include <cstring>
|
||||
#include <fstream>
|
||||
|
||||
using namespace iss::arch;
|
||||
|
||||
constexpr std::array<const char*, ${getRegisterNames().size}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_names;
|
||||
constexpr std::array<const char*, ${getRegisterAliasNames().size}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_aliases;
|
||||
constexpr std::array<const uint32_t, ${regSizes.size}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_bit_widths;
|
||||
constexpr std::array<const uint32_t, ${regOffsets.size}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_byte_offsets;
|
||||
|
||||
${coreDef.name.toLowerCase()}::${coreDef.name.toLowerCase()}() {
|
||||
reg.icount = 0;
|
||||
}
|
||||
|
||||
${coreDef.name.toLowerCase()}::~${coreDef.name.toLowerCase()}() = default;
|
||||
|
||||
void ${coreDef.name.toLowerCase()}::reset(uint64_t address) {
|
||||
for(size_t i=0; i<traits<${coreDef.name.toLowerCase()}>::NUM_REGS; ++i) set_reg(i, std::vector<uint8_t>(sizeof(traits<${coreDef.name.toLowerCase()}>::reg_t),0));
|
||||
reg.PC=address;
|
||||
reg.NEXT_PC=reg.PC;
|
||||
reg.trap_state=0;
|
||||
reg.machine_state=0x3;
|
||||
reg.icount=0;
|
||||
}
|
||||
|
||||
uint8_t *${coreDef.name.toLowerCase()}::get_regs_base_ptr() {
|
||||
return reinterpret_cast<uint8_t*>(®);
|
||||
}
|
||||
|
||||
${coreDef.name.toLowerCase()}::phys_addr_t ${coreDef.name.toLowerCase()}::virt2phys(const iss::addr_t &pc) {
|
||||
return phys_addr_t(pc); // change logical address to physical address
|
||||
}
|
||||
|
||||
|
|
@ -35,9 +35,9 @@
|
|||
#include <iss/debugger/gdb_session.h>
|
||||
#include <iss/debugger/server.h>
|
||||
#include <iss/iss.h>
|
||||
#include <iss/llvm/vm_base.h>
|
||||
#include <iss/tcc/vm_base.h>
|
||||
#include <util/logging.h>
|
||||
#include <strstream>
|
||||
#include <sstream>
|
||||
|
||||
#ifndef FMT_HEADER_ONLY
|
||||
#define FMT_HEADER_ONLY
|
||||
|
|
@ -48,26 +48,24 @@
|
|||
#include <iss/debugger/riscv_target_adapter.h>
|
||||
|
||||
namespace iss {
|
||||
namespace vm {
|
||||
namespace fp_impl {
|
||||
void add_fp_functions_2_module(llvm::Module *, unsigned, unsigned);
|
||||
}
|
||||
}
|
||||
|
||||
namespace tcc {
|
||||
namespace ${coreDef.name.toLowerCase()} {
|
||||
using namespace iss::arch;
|
||||
using namespace iss::debugger;
|
||||
using namespace iss::vm::llvm;
|
||||
using namespace iss::vm::tcc;
|
||||
|
||||
template <typename ARCH> class vm_impl : public vm_base<ARCH> {
|
||||
public:
|
||||
using super = typename iss::vm::llvm::vm_base<ARCH>;
|
||||
using super = typename iss::vm::tcc::vm_base<ARCH>;
|
||||
using virt_addr_t = typename super::virt_addr_t;
|
||||
using phys_addr_t = typename super::phys_addr_t;
|
||||
using code_word_t = typename super::code_word_t;
|
||||
using addr_t = typename super::addr_t;
|
||||
|
||||
using Value = void;
|
||||
using ConstantInt = void;
|
||||
using Type = void;
|
||||
|
||||
vm_impl();
|
||||
|
||||
vm_impl(ARCH &core, unsigned core_id = 0, unsigned cluster_id = 0);
|
||||
|
|
@ -91,12 +89,11 @@ protected:
|
|||
inline const char *name(size_t index){return traits<ARCH>::reg_aliases.at(index);}
|
||||
|
||||
template <typename T> inline ConstantInt *size(T type) {
|
||||
return ConstantInt::get(getContext(), APInt(32, type->getType()->getScalarSizeInBits()));
|
||||
return nullptr;
|
||||
}
|
||||
|
||||
void setup_module(Module* m) override {
|
||||
super::setup_module(m);
|
||||
iss::vm::fp_impl::add_fp_functions_2_module(m, traits<ARCH>::FP_REGS_SIZE, traits<ARCH>::XLEN);
|
||||
}
|
||||
|
||||
inline Value *gen_choose(Value *cond, Value *trueVal, Value *falseVal, unsigned size) {
|
||||
|
|
@ -105,7 +102,7 @@ protected:
|
|||
|
||||
compile_ret_t gen_single_inst_behavior(virt_addr_t &, unsigned int &, std::ostringstream&) override;
|
||||
|
||||
void gen_leave_behavior(BasicBlock *leave_blk) override;
|
||||
void gen_leave_behavior(std::ostringstream& os) override;
|
||||
|
||||
void gen_raise_trap(uint16_t trap_id, uint16_t cause);
|
||||
|
||||
|
|
@ -113,9 +110,9 @@ protected:
|
|||
|
||||
void gen_wait(unsigned type);
|
||||
|
||||
void gen_trap_behavior(BasicBlock *) override;
|
||||
void gen_trap_behavior(std::ostringstream& os) override;
|
||||
|
||||
void gen_trap_check(BasicBlock *bb);
|
||||
void gen_trap_check(std::ostringstream& os){}
|
||||
|
||||
inline Value *gen_reg_load(unsigned i, unsigned level = 0) {
|
||||
return this->builder.CreateLoad(get_reg_ptr(i), false);
|
||||
|
|
@ -205,18 +202,12 @@ private:
|
|||
/****************************************************************************
|
||||
* end opcode definitions
|
||||
****************************************************************************/
|
||||
compile_ret_t illegal_intruction(virt_addr_t &pc, code_word_t instr, std::stringstream& os) {
|
||||
this->gen_sync(iss::PRE_SYNC, instr_descr.size());
|
||||
this->builder.CreateStore(this->builder.CreateLoad(get_reg_ptr(traits<ARCH>::NEXT_PC), true),
|
||||
get_reg_ptr(traits<ARCH>::PC), true);
|
||||
this->builder.CreateStore(
|
||||
this->builder.CreateAdd(this->builder.CreateLoad(get_reg_ptr(traits<ARCH>::ICOUNT), true),
|
||||
this->gen_const(64U, 1)),
|
||||
get_reg_ptr(traits<ARCH>::ICOUNT), true);
|
||||
compile_ret_t illegal_intruction(virt_addr_t &pc, code_word_t instr, std::ostringstream& oss) {
|
||||
vm_impl::gen_sync(iss::PRE_SYNC, instr_descr.size());
|
||||
pc = pc + ((instr & 3) == 3 ? 4 : 2);
|
||||
this->gen_raise_trap(0, 2); // illegal instruction trap
|
||||
this->gen_sync(iss::POST_SYNC, instr_descr.size());
|
||||
this->gen_trap_check(this->leave_blk);
|
||||
gen_raise_trap(0, 2); // illegal instruction trap
|
||||
vm_impl::gen_sync(iss::POST_SYNC, instr_descr.size());
|
||||
vm_impl::gen_trap_check(oss);
|
||||
return BRANCH;
|
||||
}
|
||||
};
|
||||
|
|
@ -269,53 +260,25 @@ vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, unsigned int &inst_cnt,
|
|||
if (f == nullptr) {
|
||||
f = &this_class::illegal_intruction;
|
||||
}
|
||||
return (this->*f)(pc, insn, this_block);
|
||||
return (this->*f)(pc, insn, os);
|
||||
}
|
||||
|
||||
template <typename ARCH> void vm_impl<ARCH>::gen_leave_behavior(BasicBlock *leave_blk) {
|
||||
this->builder.SetInsertPoint(leave_blk);
|
||||
this->builder.CreateRet(this->builder.CreateLoad(get_reg_ptr(arch::traits<ARCH>::NEXT_PC), false));
|
||||
template <typename ARCH> void vm_impl<ARCH>::gen_leave_behavior(std::ostringstream& os) {
|
||||
}
|
||||
|
||||
template <typename ARCH> void vm_impl<ARCH>::gen_raise_trap(uint16_t trap_id, uint16_t cause) {
|
||||
auto *TRAP_val = this->gen_const(32, 0x80 << 24 | (cause << 16) | trap_id);
|
||||
this->builder.CreateStore(TRAP_val, get_reg_ptr(traits<ARCH>::TRAP_STATE), true);
|
||||
this->builder.CreateStore(this->gen_const(32U, std::numeric_limits<uint32_t>::max()), get_reg_ptr(traits<ARCH>::LAST_BRANCH), false);
|
||||
}
|
||||
|
||||
template <typename ARCH> void vm_impl<ARCH>::gen_leave_trap(unsigned lvl) {
|
||||
std::vector<Value *> args{ this->core_ptr, ConstantInt::get(getContext(), APInt(64, lvl)) };
|
||||
this->builder.CreateCall(this->mod->getFunction("leave_trap"), args);
|
||||
auto *PC_val = this->gen_read_mem(traits<ARCH>::CSR, (lvl << 8) + 0x41, traits<ARCH>::XLEN / 8);
|
||||
this->builder.CreateStore(PC_val, get_reg_ptr(traits<ARCH>::NEXT_PC), false);
|
||||
this->builder.CreateStore(this->gen_const(32U, std::numeric_limits<uint32_t>::max()), get_reg_ptr(traits<ARCH>::LAST_BRANCH), false);
|
||||
}
|
||||
|
||||
template <typename ARCH> void vm_impl<ARCH>::gen_wait(unsigned type) {
|
||||
std::vector<Value *> args{ this->core_ptr, ConstantInt::get(getContext(), APInt(64, type)) };
|
||||
this->builder.CreateCall(this->mod->getFunction("wait"), args);
|
||||
}
|
||||
|
||||
template <typename ARCH> void vm_impl<ARCH>::gen_trap_behavior(BasicBlock *trap_blk) {
|
||||
this->builder.SetInsertPoint(trap_blk);
|
||||
auto *trap_state_val = this->builder.CreateLoad(get_reg_ptr(traits<ARCH>::TRAP_STATE), true);
|
||||
this->builder.CreateStore(this->gen_const(32U, std::numeric_limits<uint32_t>::max()),
|
||||
get_reg_ptr(traits<ARCH>::LAST_BRANCH), false);
|
||||
std::vector<Value *> args{this->core_ptr, this->adj_to64(trap_state_val),
|
||||
this->adj_to64(this->builder.CreateLoad(get_reg_ptr(traits<ARCH>::PC), false))};
|
||||
this->builder.CreateCall(this->mod->getFunction("enter_trap"), args);
|
||||
auto *trap_addr_val = this->builder.CreateLoad(get_reg_ptr(traits<ARCH>::NEXT_PC), false);
|
||||
this->builder.CreateRet(trap_addr_val);
|
||||
template <typename ARCH> void vm_impl<ARCH>::gen_trap_behavior(std::ostringstream& os) {
|
||||
}
|
||||
|
||||
template <typename ARCH> inline void vm_impl<ARCH>::gen_trap_check(BasicBlock *bb) {
|
||||
auto *v = this->builder.CreateLoad(get_reg_ptr(arch::traits<ARCH>::TRAP_STATE), true);
|
||||
this->gen_cond_branch(this->builder.CreateICmp(
|
||||
ICmpInst::ICMP_EQ, v,
|
||||
ConstantInt::get(getContext(), APInt(v->getType()->getIntegerBitWidth(), 0))),
|
||||
bb, this->trap_blk, 1);
|
||||
}
|
||||
} // namespace ${coreDef.name.toLowerCase()}
|
||||
} // namespace mnrv32
|
||||
|
||||
template <>
|
||||
std::unique_ptr<vm_if> create<arch::${coreDef.name.toLowerCase()}>(arch::${coreDef.name.toLowerCase()} *core, unsigned short port, bool dump) {
|
||||
|
|
|
|||
|
|
@ -0,0 +1,534 @@
|
|||
/*******************************************************************************
|
||||
* Copyright (C) 2020 MINRES Technologies GmbH
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of the copyright holder nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*******************************************************************************/
|
||||
|
||||
#include <iss/arch/mnrv32.h>
|
||||
#include <iss/arch/riscv_hart_msu_vp.h>
|
||||
#include <iss/debugger/gdb_session.h>
|
||||
#include <iss/debugger/server.h>
|
||||
#include <iss/iss.h>
|
||||
#include <iss/interp/vm_base.h>
|
||||
#include <util/logging.h>
|
||||
#include <sstream>
|
||||
|
||||
#ifndef FMT_HEADER_ONLY
|
||||
#define FMT_HEADER_ONLY
|
||||
#endif
|
||||
#include <fmt/format.h>
|
||||
|
||||
#include <array>
|
||||
#include <iss/debugger/riscv_target_adapter.h>
|
||||
|
||||
namespace iss {
|
||||
namespace interp {
|
||||
namespace mnrv32 {
|
||||
using namespace iss::arch;
|
||||
using namespace iss::debugger;
|
||||
|
||||
template <typename ARCH> class vm_impl : public vm::interp::vm_base<ARCH> {
|
||||
public:
|
||||
using super = typename vm::interp::vm_base<ARCH>;
|
||||
using virt_addr_t = typename super::virt_addr_t;
|
||||
using phys_addr_t = typename super::phys_addr_t;
|
||||
using code_word_t = typename super::code_word_t;
|
||||
using addr_t = typename super::addr_t;
|
||||
|
||||
vm_impl();
|
||||
|
||||
vm_impl(ARCH &core, unsigned core_id = 0, unsigned cluster_id = 0);
|
||||
|
||||
void enableDebug(bool enable) { super::sync_exec = super::ALL_SYNC; }
|
||||
|
||||
target_adapter_if *accquire_target_adapter(server_if *srv) override {
|
||||
debugger_if::dbg_enabled = true;
|
||||
if (vm::interp::vm_base<ARCH>::tgt_adapter == nullptr)
|
||||
vm::interp::vm_base<ARCH>::tgt_adapter = new riscv_target_adapter<ARCH>(srv, this->get_arch());
|
||||
return vm::interp::vm_base<ARCH>::tgt_adapter;
|
||||
}
|
||||
|
||||
protected:
|
||||
using this_class = vm_impl<ARCH>;
|
||||
using compile_ret_t = virt_addr_t;
|
||||
using compile_func = compile_ret_t (this_class::*)(virt_addr_t &pc, code_word_t instr);
|
||||
|
||||
inline const char *name(size_t index){return traits<ARCH>::reg_aliases.at(index);}
|
||||
|
||||
|
||||
virt_addr_t execute_single_inst(virt_addr_t pc) override;
|
||||
|
||||
// some compile time constants
|
||||
// enum { MASK16 = 0b1111110001100011, MASK32 = 0b11111111111100000111000001111111 };
|
||||
enum { MASK16 = 0b1111111111111111, MASK32 = 0b11111111111100000111000001111111 };
|
||||
enum { EXTR_MASK16 = MASK16 >> 2, EXTR_MASK32 = MASK32 >> 2 };
|
||||
enum { LUT_SIZE = 1 << util::bit_count(EXTR_MASK32), LUT_SIZE_C = 1 << util::bit_count(EXTR_MASK16) };
|
||||
|
||||
std::array<compile_func, LUT_SIZE> lut;
|
||||
|
||||
std::array<compile_func, LUT_SIZE_C> lut_00, lut_01, lut_10;
|
||||
std::array<compile_func, LUT_SIZE> lut_11;
|
||||
|
||||
std::array<compile_func *, 4> qlut;
|
||||
|
||||
std::array<const uint32_t, 4> lutmasks = {{EXTR_MASK16, EXTR_MASK16, EXTR_MASK16, EXTR_MASK32}};
|
||||
|
||||
void expand_bit_mask(int pos, uint32_t mask, uint32_t value, uint32_t valid, uint32_t idx, compile_func lut[],
|
||||
compile_func f) {
|
||||
if (pos < 0) {
|
||||
lut[idx] = f;
|
||||
} else {
|
||||
auto bitmask = 1UL << pos;
|
||||
if ((mask & bitmask) == 0) {
|
||||
expand_bit_mask(pos - 1, mask, value, valid, idx, lut, f);
|
||||
} else {
|
||||
if ((valid & bitmask) == 0) {
|
||||
expand_bit_mask(pos - 1, mask, value, valid, (idx << 1), lut, f);
|
||||
expand_bit_mask(pos - 1, mask, value, valid, (idx << 1) + 1, lut, f);
|
||||
} else {
|
||||
auto new_val = idx << 1;
|
||||
if ((value & bitmask) != 0) new_val++;
|
||||
expand_bit_mask(pos - 1, mask, value, valid, new_val, lut, f);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
inline uint32_t extract_fields(uint32_t val) { return extract_fields(29, val >> 2, lutmasks[val & 0x3], 0); }
|
||||
|
||||
uint32_t extract_fields(int pos, uint32_t val, uint32_t mask, uint32_t lut_val) {
|
||||
if (pos >= 0) {
|
||||
auto bitmask = 1UL << pos;
|
||||
if ((mask & bitmask) == 0) {
|
||||
lut_val = extract_fields(pos - 1, val, mask, lut_val);
|
||||
} else {
|
||||
auto new_val = lut_val << 1;
|
||||
if ((val & bitmask) != 0) new_val++;
|
||||
lut_val = extract_fields(pos - 1, val, mask, new_val);
|
||||
}
|
||||
}
|
||||
return lut_val;
|
||||
}
|
||||
|
||||
private:
|
||||
/****************************************************************************
|
||||
* start opcode definitions
|
||||
****************************************************************************/
|
||||
struct InstructionDesriptor {
|
||||
size_t length;
|
||||
uint32_t value;
|
||||
uint32_t mask;
|
||||
compile_func op;
|
||||
};
|
||||
|
||||
const std::array<InstructionDesriptor, 52> instr_descr = {{
|
||||
/* entries are: size, valid value, valid mask, function ptr */
|
||||
/* instruction LUI */
|
||||
{32, 0b00000000000000000000000000110111, 0b00000000000000000000000001111111, &this_class::__lui},
|
||||
/* instruction AUIPC */
|
||||
{32, 0b00000000000000000000000000010111, 0b00000000000000000000000001111111, &this_class::__auipc},
|
||||
/* instruction JAL */
|
||||
{32, 0b00000000000000000000000001101111, 0b00000000000000000000000001111111, &this_class::__jal},
|
||||
/* instruction JALR */
|
||||
{32, 0b00000000000000000000000001100111, 0b00000000000000000111000001111111, &this_class::__jalr},
|
||||
/* instruction BEQ */
|
||||
{32, 0b00000000000000000000000001100011, 0b00000000000000000111000001111111, &this_class::__beq},
|
||||
/* instruction BNE */
|
||||
{32, 0b00000000000000000001000001100011, 0b00000000000000000111000001111111, &this_class::__bne},
|
||||
/* instruction BLT */
|
||||
{32, 0b00000000000000000100000001100011, 0b00000000000000000111000001111111, &this_class::__blt},
|
||||
/* instruction BGE */
|
||||
{32, 0b00000000000000000101000001100011, 0b00000000000000000111000001111111, &this_class::__bge},
|
||||
/* instruction BLTU */
|
||||
{32, 0b00000000000000000110000001100011, 0b00000000000000000111000001111111, &this_class::__bltu},
|
||||
/* instruction BGEU */
|
||||
{32, 0b00000000000000000111000001100011, 0b00000000000000000111000001111111, &this_class::__bgeu},
|
||||
/* instruction LB */
|
||||
{32, 0b00000000000000000000000000000011, 0b00000000000000000111000001111111, &this_class::__lb},
|
||||
/* instruction LH */
|
||||
{32, 0b00000000000000000001000000000011, 0b00000000000000000111000001111111, &this_class::__lh},
|
||||
/* instruction LW */
|
||||
{32, 0b00000000000000000010000000000011, 0b00000000000000000111000001111111, &this_class::__lw},
|
||||
/* instruction LBU */
|
||||
{32, 0b00000000000000000100000000000011, 0b00000000000000000111000001111111, &this_class::__lbu},
|
||||
/* instruction LHU */
|
||||
{32, 0b00000000000000000101000000000011, 0b00000000000000000111000001111111, &this_class::__lhu},
|
||||
/* instruction SB */
|
||||
{32, 0b00000000000000000000000000100011, 0b00000000000000000111000001111111, &this_class::__sb},
|
||||
/* instruction SH */
|
||||
{32, 0b00000000000000000001000000100011, 0b00000000000000000111000001111111, &this_class::__sh},
|
||||
/* instruction SW */
|
||||
{32, 0b00000000000000000010000000100011, 0b00000000000000000111000001111111, &this_class::__sw},
|
||||
/* instruction ADDI */
|
||||
{32, 0b00000000000000000000000000010011, 0b00000000000000000111000001111111, &this_class::__addi},
|
||||
/* instruction SLTI */
|
||||
{32, 0b00000000000000000010000000010011, 0b00000000000000000111000001111111, &this_class::__slti},
|
||||
/* instruction SLTIU */
|
||||
{32, 0b00000000000000000011000000010011, 0b00000000000000000111000001111111, &this_class::__sltiu},
|
||||
/* instruction XORI */
|
||||
{32, 0b00000000000000000100000000010011, 0b00000000000000000111000001111111, &this_class::__xori},
|
||||
/* instruction ORI */
|
||||
{32, 0b00000000000000000110000000010011, 0b00000000000000000111000001111111, &this_class::__ori},
|
||||
/* instruction ANDI */
|
||||
{32, 0b00000000000000000111000000010011, 0b00000000000000000111000001111111, &this_class::__andi},
|
||||
/* instruction SLLI */
|
||||
{32, 0b00000000000000000001000000010011, 0b11111110000000000111000001111111, &this_class::__slli},
|
||||
/* instruction SRLI */
|
||||
{32, 0b00000000000000000101000000010011, 0b11111110000000000111000001111111, &this_class::__srli},
|
||||
/* instruction SRAI */
|
||||
{32, 0b01000000000000000101000000010011, 0b11111110000000000111000001111111, &this_class::__srai},
|
||||
/* instruction ADD */
|
||||
{32, 0b00000000000000000000000000110011, 0b11111110000000000111000001111111, &this_class::__add},
|
||||
/* instruction SUB */
|
||||
{32, 0b01000000000000000000000000110011, 0b11111110000000000111000001111111, &this_class::__sub},
|
||||
/* instruction SLL */
|
||||
{32, 0b00000000000000000001000000110011, 0b11111110000000000111000001111111, &this_class::__sll},
|
||||
/* instruction SLT */
|
||||
{32, 0b00000000000000000010000000110011, 0b11111110000000000111000001111111, &this_class::__slt},
|
||||
/* instruction SLTU */
|
||||
{32, 0b00000000000000000011000000110011, 0b11111110000000000111000001111111, &this_class::__sltu},
|
||||
/* instruction XOR */
|
||||
{32, 0b00000000000000000100000000110011, 0b11111110000000000111000001111111, &this_class::__xor},
|
||||
/* instruction SRL */
|
||||
{32, 0b00000000000000000101000000110011, 0b11111110000000000111000001111111, &this_class::__srl},
|
||||
/* instruction SRA */
|
||||
{32, 0b01000000000000000101000000110011, 0b11111110000000000111000001111111, &this_class::__sra},
|
||||
/* instruction OR */
|
||||
{32, 0b00000000000000000110000000110011, 0b11111110000000000111000001111111, &this_class::__or},
|
||||
/* instruction AND */
|
||||
{32, 0b00000000000000000111000000110011, 0b11111110000000000111000001111111, &this_class::__and},
|
||||
/* instruction FENCE */
|
||||
{32, 0b00000000000000000000000000001111, 0b11110000000000000111000001111111, &this_class::__fence},
|
||||
/* instruction FENCE_I */
|
||||
{32, 0b00000000000000000001000000001111, 0b00000000000000000111000001111111, &this_class::__fence_i},
|
||||
/* instruction ECALL */
|
||||
{32, 0b00000000000000000000000001110011, 0b11111111111111111111111111111111, &this_class::__ecall},
|
||||
/* instruction EBREAK */
|
||||
{32, 0b00000000000100000000000001110011, 0b11111111111111111111111111111111, &this_class::__ebreak},
|
||||
/* instruction URET */
|
||||
{32, 0b00000000001000000000000001110011, 0b11111111111111111111111111111111, &this_class::__uret},
|
||||
/* instruction SRET */
|
||||
{32, 0b00010000001000000000000001110011, 0b11111111111111111111111111111111, &this_class::__sret},
|
||||
/* instruction MRET */
|
||||
{32, 0b00110000001000000000000001110011, 0b11111111111111111111111111111111, &this_class::__mret},
|
||||
/* instruction WFI */
|
||||
{32, 0b00010000010100000000000001110011, 0b11111111111111111111111111111111, &this_class::__wfi},
|
||||
/* instruction SFENCE.VMA */
|
||||
{32, 0b00010010000000000000000001110011, 0b11111110000000000111111111111111, &this_class::__sfence_vma},
|
||||
/* instruction CSRRW */
|
||||
{32, 0b00000000000000000001000001110011, 0b00000000000000000111000001111111, &this_class::__csrrw},
|
||||
/* instruction CSRRS */
|
||||
{32, 0b00000000000000000010000001110011, 0b00000000000000000111000001111111, &this_class::__csrrs},
|
||||
/* instruction CSRRC */
|
||||
{32, 0b00000000000000000011000001110011, 0b00000000000000000111000001111111, &this_class::__csrrc},
|
||||
/* instruction CSRRWI */
|
||||
{32, 0b00000000000000000101000001110011, 0b00000000000000000111000001111111, &this_class::__csrrwi},
|
||||
/* instruction CSRRSI */
|
||||
{32, 0b00000000000000000110000001110011, 0b00000000000000000111000001111111, &this_class::__csrrsi},
|
||||
/* instruction CSRRCI */
|
||||
{32, 0b00000000000000000111000001110011, 0b00000000000000000111000001111111, &this_class::__csrrci},
|
||||
}};
|
||||
|
||||
/* instruction definitions */
|
||||
/* instruction 0: LUI */
|
||||
compile_ret_t __lui(virt_addr_t& pc, code_word_t instr){
|
||||
}
|
||||
|
||||
/* instruction 1: AUIPC */
|
||||
compile_ret_t __auipc(virt_addr_t& pc, code_word_t instr){
|
||||
}
|
||||
|
||||
/* instruction 2: JAL */
|
||||
compile_ret_t __jal(virt_addr_t& pc, code_word_t instr){
|
||||
}
|
||||
|
||||
/* instruction 3: JALR */
|
||||
compile_ret_t __jalr(virt_addr_t& pc, code_word_t instr){
|
||||
}
|
||||
|
||||
/* instruction 4: BEQ */
|
||||
compile_ret_t __beq(virt_addr_t& pc, code_word_t instr){
|
||||
}
|
||||
|
||||
/* instruction 5: BNE */
|
||||
compile_ret_t __bne(virt_addr_t& pc, code_word_t instr){
|
||||
}
|
||||
|
||||
/* instruction 6: BLT */
|
||||
compile_ret_t __blt(virt_addr_t& pc, code_word_t instr){
|
||||
}
|
||||
|
||||
/* instruction 7: BGE */
|
||||
compile_ret_t __bge(virt_addr_t& pc, code_word_t instr){
|
||||
}
|
||||
|
||||
/* instruction 8: BLTU */
|
||||
compile_ret_t __bltu(virt_addr_t& pc, code_word_t instr){
|
||||
}
|
||||
|
||||
/* instruction 9: BGEU */
|
||||
compile_ret_t __bgeu(virt_addr_t& pc, code_word_t instr){
|
||||
}
|
||||
|
||||
/* instruction 10: LB */
|
||||
compile_ret_t __lb(virt_addr_t& pc, code_word_t instr){
|
||||
}
|
||||
|
||||
/* instruction 11: LH */
|
||||
compile_ret_t __lh(virt_addr_t& pc, code_word_t instr){
|
||||
}
|
||||
|
||||
/* instruction 12: LW */
|
||||
compile_ret_t __lw(virt_addr_t& pc, code_word_t instr){
|
||||
}
|
||||
|
||||
/* instruction 13: LBU */
|
||||
compile_ret_t __lbu(virt_addr_t& pc, code_word_t instr){
|
||||
}
|
||||
|
||||
/* instruction 14: LHU */
|
||||
compile_ret_t __lhu(virt_addr_t& pc, code_word_t instr){
|
||||
}
|
||||
|
||||
/* instruction 15: SB */
|
||||
compile_ret_t __sb(virt_addr_t& pc, code_word_t instr){
|
||||
}
|
||||
|
||||
/* instruction 16: SH */
|
||||
compile_ret_t __sh(virt_addr_t& pc, code_word_t instr){
|
||||
}
|
||||
|
||||
/* instruction 17: SW */
|
||||
compile_ret_t __sw(virt_addr_t& pc, code_word_t instr){
|
||||
}
|
||||
|
||||
/* instruction 18: ADDI */
|
||||
compile_ret_t __addi(virt_addr_t& pc, code_word_t instr){
|
||||
}
|
||||
|
||||
/* instruction 19: SLTI */
|
||||
compile_ret_t __slti(virt_addr_t& pc, code_word_t instr){
|
||||
}
|
||||
|
||||
/* instruction 20: SLTIU */
|
||||
compile_ret_t __sltiu(virt_addr_t& pc, code_word_t instr){
|
||||
}
|
||||
|
||||
/* instruction 21: XORI */
|
||||
compile_ret_t __xori(virt_addr_t& pc, code_word_t instr){
|
||||
}
|
||||
|
||||
/* instruction 22: ORI */
|
||||
compile_ret_t __ori(virt_addr_t& pc, code_word_t instr){
|
||||
}
|
||||
|
||||
/* instruction 23: ANDI */
|
||||
compile_ret_t __andi(virt_addr_t& pc, code_word_t instr){
|
||||
}
|
||||
|
||||
/* instruction 24: SLLI */
|
||||
compile_ret_t __slli(virt_addr_t& pc, code_word_t instr){
|
||||
}
|
||||
|
||||
/* instruction 25: SRLI */
|
||||
compile_ret_t __srli(virt_addr_t& pc, code_word_t instr){
|
||||
}
|
||||
|
||||
/* instruction 26: SRAI */
|
||||
compile_ret_t __srai(virt_addr_t& pc, code_word_t instr){
|
||||
}
|
||||
|
||||
/* instruction 27: ADD */
|
||||
compile_ret_t __add(virt_addr_t& pc, code_word_t instr){
|
||||
}
|
||||
|
||||
/* instruction 28: SUB */
|
||||
compile_ret_t __sub(virt_addr_t& pc, code_word_t instr){
|
||||
}
|
||||
|
||||
/* instruction 29: SLL */
|
||||
compile_ret_t __sll(virt_addr_t& pc, code_word_t instr){
|
||||
}
|
||||
|
||||
/* instruction 30: SLT */
|
||||
compile_ret_t __slt(virt_addr_t& pc, code_word_t instr){
|
||||
}
|
||||
|
||||
/* instruction 31: SLTU */
|
||||
compile_ret_t __sltu(virt_addr_t& pc, code_word_t instr){
|
||||
}
|
||||
|
||||
/* instruction 32: XOR */
|
||||
compile_ret_t __xor(virt_addr_t& pc, code_word_t instr){
|
||||
}
|
||||
|
||||
/* instruction 33: SRL */
|
||||
compile_ret_t __srl(virt_addr_t& pc, code_word_t instr){
|
||||
}
|
||||
|
||||
/* instruction 34: SRA */
|
||||
compile_ret_t __sra(virt_addr_t& pc, code_word_t instr){
|
||||
}
|
||||
|
||||
/* instruction 35: OR */
|
||||
compile_ret_t __or(virt_addr_t& pc, code_word_t instr){
|
||||
}
|
||||
|
||||
/* instruction 36: AND */
|
||||
compile_ret_t __and(virt_addr_t& pc, code_word_t instr){
|
||||
}
|
||||
|
||||
/* instruction 37: FENCE */
|
||||
compile_ret_t __fence(virt_addr_t& pc, code_word_t instr){
|
||||
}
|
||||
|
||||
/* instruction 38: FENCE_I */
|
||||
compile_ret_t __fence_i(virt_addr_t& pc, code_word_t instr){
|
||||
}
|
||||
|
||||
/* instruction 39: ECALL */
|
||||
compile_ret_t __ecall(virt_addr_t& pc, code_word_t instr){
|
||||
}
|
||||
|
||||
/* instruction 40: EBREAK */
|
||||
compile_ret_t __ebreak(virt_addr_t& pc, code_word_t instr){
|
||||
}
|
||||
|
||||
/* instruction 41: URET */
|
||||
compile_ret_t __uret(virt_addr_t& pc, code_word_t instr){
|
||||
}
|
||||
|
||||
/* instruction 42: SRET */
|
||||
compile_ret_t __sret(virt_addr_t& pc, code_word_t instr){
|
||||
}
|
||||
|
||||
/* instruction 43: MRET */
|
||||
compile_ret_t __mret(virt_addr_t& pc, code_word_t instr){
|
||||
}
|
||||
|
||||
/* instruction 44: WFI */
|
||||
compile_ret_t __wfi(virt_addr_t& pc, code_word_t instr){
|
||||
}
|
||||
|
||||
/* instruction 45: SFENCE.VMA */
|
||||
compile_ret_t __sfence_vma(virt_addr_t& pc, code_word_t instr){
|
||||
}
|
||||
|
||||
/* instruction 46: CSRRW */
|
||||
compile_ret_t __csrrw(virt_addr_t& pc, code_word_t instr){
|
||||
}
|
||||
|
||||
/* instruction 47: CSRRS */
|
||||
compile_ret_t __csrrs(virt_addr_t& pc, code_word_t instr){
|
||||
}
|
||||
|
||||
/* instruction 48: CSRRC */
|
||||
compile_ret_t __csrrc(virt_addr_t& pc, code_word_t instr){
|
||||
}
|
||||
|
||||
/* instruction 49: CSRRWI */
|
||||
compile_ret_t __csrrwi(virt_addr_t& pc, code_word_t instr){
|
||||
}
|
||||
|
||||
/* instruction 50: CSRRSI */
|
||||
compile_ret_t __csrrsi(virt_addr_t& pc, code_word_t instr){
|
||||
}
|
||||
|
||||
/* instruction 51: CSRRCI */
|
||||
compile_ret_t __csrrci(virt_addr_t& pc, code_word_t instr){
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* end opcode definitions
|
||||
****************************************************************************/
|
||||
compile_ret_t illegal_intruction(virt_addr_t &pc, code_word_t instr) {
|
||||
pc = pc + ((instr & 3) == 3 ? 4 : 2);
|
||||
return pc;
|
||||
}
|
||||
};
|
||||
|
||||
template <typename CODE_WORD> void debug_fn(CODE_WORD insn) {
|
||||
volatile CODE_WORD x = insn;
|
||||
insn = 2 * x;
|
||||
}
|
||||
|
||||
template <typename ARCH> vm_impl<ARCH>::vm_impl() { this(new ARCH()); }
|
||||
|
||||
template <typename ARCH>
|
||||
vm_impl<ARCH>::vm_impl(ARCH &core, unsigned core_id, unsigned cluster_id)
|
||||
: vm::interp::vm_base<ARCH>(core, core_id, cluster_id) {
|
||||
qlut[0] = lut_00.data();
|
||||
qlut[1] = lut_01.data();
|
||||
qlut[2] = lut_10.data();
|
||||
qlut[3] = lut_11.data();
|
||||
for (auto instr : instr_descr) {
|
||||
auto quantrant = instr.value & 0x3;
|
||||
expand_bit_mask(29, lutmasks[quantrant], instr.value >> 2, instr.mask >> 2, 0, qlut[quantrant], instr.op);
|
||||
}
|
||||
}
|
||||
|
||||
template <typename ARCH>
|
||||
typename vm::interp::vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_single_inst(virt_addr_t pc) {
|
||||
// we fetch at max 4 byte, alignment is 2
|
||||
enum {TRAP_ID=1<<16};
|
||||
code_word_t insn = 0;
|
||||
const typename traits<ARCH>::addr_t upper_bits = ~traits<ARCH>::PGMASK;
|
||||
phys_addr_t paddr(pc);
|
||||
auto *const data = (uint8_t *)&insn;
|
||||
paddr = this->core.v2p(pc);
|
||||
if ((pc.val & upper_bits) != ((pc.val + 2) & upper_bits)) { // we may cross a page boundary
|
||||
auto res = this->core.read(paddr, 2, data);
|
||||
if (res != iss::Ok) throw trap_access(TRAP_ID, pc.val);
|
||||
if ((insn & 0x3) == 0x3) { // this is a 32bit instruction
|
||||
res = this->core.read(this->core.v2p(pc + 2), 2, data + 2);
|
||||
}
|
||||
} else {
|
||||
auto res = this->core.read(paddr, 4, data);
|
||||
if (res != iss::Ok) throw trap_access(TRAP_ID, pc.val);
|
||||
}
|
||||
if (insn == 0x0000006f || (insn&0xffff)==0xa001) throw simulation_stopped(0); // 'J 0' or 'C.J 0'
|
||||
// curr pc on stack
|
||||
auto lut_val = extract_fields(insn);
|
||||
auto f = qlut[insn & 0x3][lut_val];
|
||||
if (f == nullptr) {
|
||||
f = &this_class::illegal_intruction;
|
||||
}
|
||||
return (this->*f)(pc, insn);
|
||||
}
|
||||
|
||||
} // namespace mnrv32
|
||||
|
||||
template <>
|
||||
std::unique_ptr<vm_if> create<arch::mnrv32>(arch::mnrv32 *core, unsigned short port, bool dump) {
|
||||
auto ret = new mnrv32::vm_impl<arch::mnrv32>(*core, dump);
|
||||
if (port != 0) debugger::server<debugger::gdb_session>::run_server(ret, port);
|
||||
return std::unique_ptr<vm_if>(ret);
|
||||
}
|
||||
}
|
||||
} // namespace iss
|
||||
Loading…
Reference in New Issue