DBT-RISE/DBT-RISE-TGC
12
0
Fork 0
Code Issues 1 Pull Requests 1 Projects Releases Wiki Activity

Fixed implementation of RV64 so that remaining riscv-test pass

Browse Source
This commit is contained in:
eyck
2019-01-10 10:35:20 +00:00
parent d5d236bf10
commit f69b529cab
27 changed files with 19993 additions and 8967 deletions
Download Patch File Download Diff File Expand all files Collapse all files

21
riscv/gen_input/minres_rv.core_desc
View File

@ -5,7 +5,7 @@ import "RV32C.core_desc"
import "RV32F.core_desc"
import "RV32D.core_desc"
import "RV64IBase.core_desc"
//import "RV64M.core_desc"
import "RV64M.core_desc"
import "RV64A.core_desc"
Core RV32IMAC provides RV32IBase, RV32M, RV32A, RV32IC {
@ -33,15 +33,28 @@ Core RV32GC provides RV32IBase, RV32M, RV32A, RV32IC, RV32F, RV32FC, RV32D, RV32
}
}
Core RV64IA provides RV64IBase, RV64A, RV32A {
Core RV64I provides RV64IBase {
constants {
XLEN:=64;
PCLEN:=64;
// definitions for the architecture wrapper
// XL ZYXWVUTSRQPONMLKJIHGFEDCBA
MISA_VAL:=0b10000000000001000000000100000001;
MISA_VAL:=0b10000000000001000000000100000000;
PGSIZE := 0x1000; //1 << 12;
PGMASK := 0xfff; //PGSIZE-1
}
}
Core RV64GC provides RV64IC, RV64A, RV64M, RV32A, RV32M, RV64F, RV64D, RV32FC, RV32DC {
constants {
XLEN:=64;
FLEN:=64;
PCLEN:=64;
// definitions for the architecture wrapper
// XL ZYXWVUTSRQPONMLKJIHGFEDCBA
MISA_VAL:=0b01000000000101000001000100101101;
PGSIZE := 0x1000; //1 << 12;
PGMASK := 0xfff; //PGSIZE-1
}
}