Updated SC-Components

2019-04-11 05:40:02 +00:00 · 2019-04-11 05:40:02 +00:00 · eb8365f4c3
parent 3e8583977a
commit eb8365f4c3
12 changed files with 18 additions and 18 deletions
--- a/README.md
+++ b/README.md
@ -10,16 +10,9 @@ The implementation is based on LLVM 4.0. Eclipse CDT 4.7 (Oxygen) is recommended

 DBT-RISE-RISCV uses libGIS (https://github.com/vsergeev/libGIS) as well as ELFIO (http://elfio.sourceforge.net/), both under MIT license 

-**What's missing**
-
-* F & D standard extensions for 32bit to be implemented
-* MACF &D standard extensions for 64bit to be implemented and verified
-
 **Planned features**

 * add platform peripherals beyond programmers view to resemble E300 platform
-  * QSPI
-  * PWM
  * ...
 * and more

--- a/platform/src/sysc/plic.cpp
+++ b/platform/src/sysc/plic.cpp
@ -50,7 +50,7 @@ plic::plic(sc_core::sc_module_name nm)
 {
    regs->registerResources(*this);
    // register callbacks
-    regs->claim_complete.set_write_cb([this](scc::sc_register<uint32_t> reg, uint32_t v, sc_core::sc_time d) -> bool {
+    regs->claim_complete.set_write_cb([this](scc::sc_register<uint32_t>& reg, const uint32_t& v, sc_core::sc_time d) -> bool {
        reg.put(v);
        reset_pending_int(v);
        // std::cout << "Value of register: 0x" << std::hex << reg << std::endl;
--- a/platform/src/sysc/pwm.cpp
+++ b/platform/src/sysc/pwm.cpp
@ -51,14 +51,14 @@ pwm::pwm(sc_core::sc_module_name nm)
    regs->registerResources(*this);

    regs->pwmcfg.set_write_cb(
-        [this](const scc::sc_register<uint32_t> &reg, uint32_t &data, sc_core::sc_time d) -> bool {
+        [this](const scc::sc_register<uint32_t> &reg, const uint32_t &data, sc_core::sc_time d) -> bool {
            if (d.value()) wait(d);
            reg.put(data);
            update_counter();
            return true;
        });
    regs->pwmcount.set_write_cb(
-        [this](const scc::sc_register<uint32_t> &reg, uint32_t &data, sc_core::sc_time d) -> bool {
+        [this](const scc::sc_register<uint32_t> &reg, const uint32_t &data, sc_core::sc_time d) -> bool {
            if (d.value()) wait(d);
            reg.put(data);
            update_counter();
@ -83,25 +83,25 @@ pwm::pwm(sc_core::sc_module_name nm)
        return true;
    });
    regs->pwmcmp0.set_write_cb(
-        [this](const scc::sc_register<uint32_t> &reg, uint32_t &data, sc_core::sc_time d) -> bool {
+        [this](const scc::sc_register<uint32_t> &reg, const uint32_t &data, sc_core::sc_time d) -> bool {
            reg.put(data);
            update_counter();
            return true;
        });
    regs->pwmcmp1.set_write_cb(
-        [this](const scc::sc_register<uint32_t> &reg, uint32_t &data, sc_core::sc_time d) -> bool {
+        [this](const scc::sc_register<uint32_t> &reg, const uint32_t &data, sc_core::sc_time d) -> bool {
            reg.put(data);
            update_counter();
            return true;
        });
    regs->pwmcmp2.set_write_cb(
-        [this](const scc::sc_register<uint32_t> &reg, uint32_t &data, sc_core::sc_time d) -> bool {
+        [this](const scc::sc_register<uint32_t> &reg, const uint32_t &data, sc_core::sc_time d) -> bool {
            reg.put(data);
            update_counter();
            return true;
        });
    regs->pwmcmp3.set_write_cb(
-        [this](const scc::sc_register<uint32_t> &reg, uint32_t &data, sc_core::sc_time d) -> bool {
+        [this](const scc::sc_register<uint32_t> &reg, const uint32_t &data, sc_core::sc_time d) -> bool {
            reg.put(data);
            update_counter();
            return true;
--- a/platform/src/sysc/spi.cpp
+++ b/platform/src/sysc/spi.cpp
@ -124,7 +124,7 @@ beh::beh(sc_core::sc_module_name nm)
        return true;
    });
    regs->csmode.set_write_cb(
-        [this](const scc::sc_register<uint32_t> &reg, uint32_t &data, sc_core::sc_time d) -> bool {
+        [this](const scc::sc_register<uint32_t> &reg, const uint32_t &data, sc_core::sc_time d) -> bool {
            if (regs->r_csmode.mode == 2 && regs->r_csmode.mode != bit_sub<0, 2>(data) && regs->r_csid < 4) {
                tlm::tlm_phase phase(tlm::BEGIN_REQ);
                sc_core::sc_time delay(SC_ZERO_TIME);
@ -136,7 +136,7 @@ beh::beh(sc_core::sc_module_name nm)
            reg.put(data);
            return true;
        });
-    regs->csid.set_write_cb([this](const scc::sc_register<uint32_t> &reg, uint32_t &data, sc_core::sc_time d) -> bool {
+    regs->csid.set_write_cb([this](const scc::sc_register<uint32_t> &reg, const uint32_t &data, sc_core::sc_time d) -> bool {
        if (regs->r_csmode.mode == 2 && regs->csid != data && regs->r_csid < 4) {
            tlm::tlm_phase phase(tlm::BEGIN_REQ);
            sc_core::sc_time delay(SC_ZERO_TIME);
@ -148,7 +148,7 @@ beh::beh(sc_core::sc_module_name nm)
        reg.put(data);
        return true;
    });
-    regs->csdef.set_write_cb([this](const scc::sc_register<uint32_t> &reg, uint32_t &data, sc_core::sc_time d) -> bool {
+    regs->csdef.set_write_cb([this](const scc::sc_register<uint32_t> &reg, const uint32_t &data, sc_core::sc_time d) -> bool {
        auto diff = regs->csdef ^ data;
        if (regs->r_csmode.mode == 2 && diff != 0 && (regs->r_csid < 4) && (diff & (1 << regs->r_csid)) != 0) {
            tlm::tlm_phase phase(tlm::BEGIN_REQ);
--- a/riscv/gen_input/templates/vm-vm_CORENAME.cpp.gtl
+++ b/riscv/gen_input/templates/vm-vm_CORENAME.cpp.gtl
@ -38,6 +38,7 @@
 #include <iss/llvm/vm_base.h>
 #include <util/logging.h>

+#define FMT_HEADER_ONLY
 #include <fmt/format.h>

 #include <array>
--- a/riscv/incl/iss/arch/riscv_hart_msu_vp.h
+++ b/riscv/incl/iss/arch/riscv_hart_msu_vp.h
@ -40,6 +40,7 @@
 #include "iss/instrumentation_if.h"
 #include "iss/log_categories.h"
 #include "iss/vm_if.h"
+#define FMT_HEADER_ONLY
 #include <fmt/format.h>
 #include <array>
 #include <elfio/elfio.hpp>
--- a/riscv/incl/iss/debugger/riscv_target_adapter.h
+++ b/riscv/incl/iss/debugger/riscv_target_adapter.h
@ -40,6 +40,7 @@

 #include <array>
 #include <memory>
+#define FMT_HEADER_ONLY
 #include <fmt/format.h>
 #include <util/logging.h>

--- a/riscv/src/internal/vm_rv32gc.cpp
+++ b/riscv/src/internal/vm_rv32gc.cpp
@ -38,6 +38,7 @@
 #include <iss/llvm/vm_base.h>
 #include <util/logging.h>

+#define FMT_HEADER_ONLY
 #include <fmt/format.h>

 #include <array>
--- a/riscv/src/internal/vm_rv32imac.cpp
+++ b/riscv/src/internal/vm_rv32imac.cpp
@ -38,6 +38,7 @@
 #include <iss/llvm/vm_base.h>
 #include <util/logging.h>

+#define FMT_HEADER_ONLY
 #include <fmt/format.h>

 #include <array>
--- a/riscv/src/internal/vm_rv64gc.cpp
+++ b/riscv/src/internal/vm_rv64gc.cpp
@ -38,6 +38,7 @@
 #include <iss/llvm/vm_base.h>
 #include <util/logging.h>

+#define FMT_HEADER_ONLY
 #include <fmt/format.h>

 #include <array>
--- a/riscv/src/internal/vm_rv64i.cpp
+++ b/riscv/src/internal/vm_rv64i.cpp
@ -38,6 +38,7 @@
 #include <iss/llvm/vm_base.h>
 #include <util/logging.h>

+#define FMT_HEADER_ONLY
 #include <fmt/format.h>

 #include <array>
--- a/2
+++ b/2
@ -1 +1 @@
-Subproject commit 05ba88052cf922b1e93550342d8e297338619b5d
+Subproject commit 7c989da05673bb40e1358561d51b86e71c1ac68c