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adds formatting fixes

This commit is contained in:
Eyck Jentzsch 2023-11-05 17:19:43 +01:00
parent 458c773e19
commit e48597b2b7
11 changed files with 1726 additions and 1692 deletions
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50
contrib/instr/TGC5C_instr.yaml
View File

@ -1,5 +1,5 @@
RV32I: RVI:
LUI: LUI:
index: 0 index: 0
encoding: 0b00000000000000000000000000110111 encoding: 0b00000000000000000000000000110111
@ -27,84 +27,84 @@ RV32I:
mask: 0b00000000000000000111000001111111 mask: 0b00000000000000000111000001111111
size: 32 size: 32
branch: true branch: true
delay: [1,2] delay: [1,1]
BEQ: BEQ:
index: 4 index: 4
encoding: 0b00000000000000000000000001100011 encoding: 0b00000000000000000000000001100011
mask: 0b00000000000000000111000001111111 mask: 0b00000000000000000111000001111111
size: 32 size: 32
branch: true branch: true
delay: [1,2] delay: [1,1]
BNE: BNE:
index: 5 index: 5
encoding: 0b00000000000000000001000001100011 encoding: 0b00000000000000000001000001100011
mask: 0b00000000000000000111000001111111 mask: 0b00000000000000000111000001111111
size: 32 size: 32
branch: true branch: true
delay: [1,2] delay: [1,1]
BLT: BLT:
index: 6 index: 6
encoding: 0b00000000000000000100000001100011 encoding: 0b00000000000000000100000001100011
mask: 0b00000000000000000111000001111111 mask: 0b00000000000000000111000001111111
size: 32 size: 32
branch: true branch: true
delay: [1,2] delay: [1,1]
BGE: BGE:
index: 7 index: 7
encoding: 0b00000000000000000101000001100011 encoding: 0b00000000000000000101000001100011
mask: 0b00000000000000000111000001111111 mask: 0b00000000000000000111000001111111
size: 32 size: 32
branch: true branch: true
delay: [1,2] delay: [1,1]
BLTU: BLTU:
index: 8 index: 8
encoding: 0b00000000000000000110000001100011 encoding: 0b00000000000000000110000001100011
mask: 0b00000000000000000111000001111111 mask: 0b00000000000000000111000001111111
size: 32 size: 32
branch: true branch: true
delay: [1,2] delay: [1,1]
BGEU: BGEU:
index: 9 index: 9
encoding: 0b00000000000000000111000001100011 encoding: 0b00000000000000000111000001100011
mask: 0b00000000000000000111000001111111 mask: 0b00000000000000000111000001111111
size: 32 size: 32
branch: true branch: true
delay: [1,2] delay: [1,1]
LB: LB:
index: 10 index: 10
encoding: 0b00000000000000000000000000000011 encoding: 0b00000000000000000000000000000011
mask: 0b00000000000000000111000001111111 mask: 0b00000000000000000111000001111111
size: 32 size: 32
branch: false branch: false
delay: 2 delay: 1
LH: LH:
index: 11 index: 11
encoding: 0b00000000000000000001000000000011 encoding: 0b00000000000000000001000000000011
mask: 0b00000000000000000111000001111111 mask: 0b00000000000000000111000001111111
size: 32 size: 32
branch: false branch: false
delay: 2 delay: 1
LW: LW:
index: 12 index: 12
encoding: 0b00000000000000000010000000000011 encoding: 0b00000000000000000010000000000011
mask: 0b00000000000000000111000001111111 mask: 0b00000000000000000111000001111111
size: 32 size: 32
branch: false branch: false
delay: 2 delay: 1
LBU: LBU:
index: 13 index: 13
encoding: 0b00000000000000000100000000000011 encoding: 0b00000000000000000100000000000011
mask: 0b00000000000000000111000001111111 mask: 0b00000000000000000111000001111111
size: 32 size: 32
branch: false branch: false
delay: 2 delay: 1
LHU: LHU:
index: 14 index: 14
encoding: 0b00000000000000000101000000000011 encoding: 0b00000000000000000101000000000011
mask: 0b00000000000000000111000001111111 mask: 0b00000000000000000111000001111111
size: 32 size: 32
branch: false branch: false
delay: 2 delay: 1
SB: SB:
index: 15 index: 15
encoding: 0b00000000000000000000000000100011 encoding: 0b00000000000000000000000000100011
@ -356,56 +356,56 @@ RV32M:
mask: 0b11111110000000000111000001111111 mask: 0b11111110000000000111000001111111
size: 32 size: 32
branch: false branch: false
delay: 2 delay: 1
MULH: MULH:
index: 50 index: 50
encoding: 0b00000010000000000001000000110011 encoding: 0b00000010000000000001000000110011
mask: 0b11111110000000000111000001111111 mask: 0b11111110000000000111000001111111
size: 32 size: 32
branch: false branch: false
delay: 2 delay: 1
MULHSU: MULHSU:
index: 51 index: 51
encoding: 0b00000010000000000010000000110011 encoding: 0b00000010000000000010000000110011
mask: 0b11111110000000000111000001111111 mask: 0b11111110000000000111000001111111
size: 32 size: 32
branch: false branch: false
delay: 2 delay: 1
MULHU: MULHU:
index: 52 index: 52
encoding: 0b00000010000000000011000000110011 encoding: 0b00000010000000000011000000110011
mask: 0b11111110000000000111000001111111 mask: 0b11111110000000000111000001111111
size: 32 size: 32
branch: false branch: false
delay: 2 delay: 1
DIV: DIV:
index: 53 index: 53
encoding: 0b00000010000000000100000000110011 encoding: 0b00000010000000000100000000110011
mask: 0b11111110000000000111000001111111 mask: 0b11111110000000000111000001111111
size: 32 size: 32
branch: false branch: false
delay: 17 delay: 1
DIVU: DIVU:
index: 54 index: 54
encoding: 0b00000010000000000101000000110011 encoding: 0b00000010000000000101000000110011
mask: 0b11111110000000000111000001111111 mask: 0b11111110000000000111000001111111
size: 32 size: 32
branch: false branch: false
delay: 17 delay: 1
REM: REM:
index: 55 index: 55
encoding: 0b00000010000000000110000000110011 encoding: 0b00000010000000000110000000110011
mask: 0b11111110000000000111000001111111 mask: 0b11111110000000000111000001111111
size: 32 size: 32
branch: false branch: false
delay: 17 delay: 1
REMU: REMU:
index: 56 index: 56
encoding: 0b00000010000000000111000000110011 encoding: 0b00000010000000000111000000110011
mask: 0b11111110000000000111000001111111 mask: 0b11111110000000000111000001111111
size: 32 size: 32
branch: false branch: false
delay: 17 delay: 1
Zca: Zca:
C__ADDI4SPN: C__ADDI4SPN:
index: 57 index: 57
@ -420,7 +420,7 @@ Zca:
mask: 0b1110000000000011 mask: 0b1110000000000011
size: 16 size: 16
branch: false branch: false
delay: 2 delay: 1
C__SW: C__SW:
index: 59 index: 59
encoding: 0b1100000000000000 encoding: 0b1100000000000000
@ -542,14 +542,14 @@ Zca:
mask: 0b1110000000000011 mask: 0b1110000000000011
size: 16 size: 16
branch: true branch: true
delay: [1,2] delay: [1,1]
C__BNEZ: C__BNEZ:
index: 76 index: 76
encoding: 0b1110000000000001 encoding: 0b1110000000000001
mask: 0b1110000000000011 mask: 0b1110000000000011
size: 16 size: 16
branch: true branch: true
delay: [1,2] delay: [1,1]
C__SLLI: C__SLLI:
index: 77 index: 77
encoding: 0b0000000000000010 encoding: 0b0000000000000010
@ -564,7 +564,7 @@ Zca:
mask: 0b1110000000000011 mask: 0b1110000000000011
size: 16 size: 16
branch: false branch: false
delay: 2 delay: 1
C__MV: C__MV:
index: 79 index: 79
encoding: 0b1000000000000010 encoding: 0b1000000000000010

3
gen_input/templates/CORENAME.cpp.gtl
View File

@ -37,6 +37,7 @@ def getRegisterSizes(){
return regs return regs
} }
%> %>
// clang-format off
#include "${coreDef.name.toLowerCase()}.h" #include "${coreDef.name.toLowerCase()}.h"
#include "util/ities.h" #include "util/ities.h"
#include <util/logging.h> #include <util/logging.h>
@ -73,4 +74,4 @@ uint8_t *${coreDef.name.toLowerCase()}::get_regs_base_ptr() {
${coreDef.name.toLowerCase()}::phys_addr_t ${coreDef.name.toLowerCase()}::virt2phys(const iss::addr_t &addr) { ${coreDef.name.toLowerCase()}::phys_addr_t ${coreDef.name.toLowerCase()}::virt2phys(const iss::addr_t &addr) {
return phys_addr_t(addr.access, addr.space, addr.val&traits<${coreDef.name.toLowerCase()}>::addr_mask); return phys_addr_t(addr.access, addr.space, addr.val&traits<${coreDef.name.toLowerCase()}>::addr_mask);
} }
// clang-format on

3
gen_input/templates/CORENAME.h.gtl
View File

@ -60,7 +60,7 @@ def getCString(def val){
%> %>
#ifndef _${coreDef.name.toUpperCase()}_H_ #ifndef _${coreDef.name.toUpperCase()}_H_
#define _${coreDef.name.toUpperCase()}_H_ #define _${coreDef.name.toUpperCase()}_H_
// clang-format off
#include <array> #include <array>
#include <iss/arch/traits.h> #include <iss/arch/traits.h>
#include <iss/arch_if.h> #include <iss/arch_if.h>
@ -174,3 +174,4 @@ if(fcsr != null) {%>
} }
} }
#endif /* _${coreDef.name.toUpperCase()}_H_ */ #endif /* _${coreDef.name.toUpperCase()}_H_ */
// clang-format on

3
gen_input/templates/CORENAME_sysc.cpp.gtl
View File

@ -29,7 +29,7 @@
* POSSIBILITY OF SUCH DAMAGE. * POSSIBILITY OF SUCH DAMAGE.
* *
*******************************************************************************/ *******************************************************************************/
// clang-format off
#include <sysc/iss_factory.h> #include <sysc/iss_factory.h>
#include <iss/arch/${coreDef.name.toLowerCase()}.h> #include <iss/arch/${coreDef.name.toLowerCase()}.h>
#include <iss/arch/riscv_hart_m_p.h> #include <iss/arch/riscv_hart_m_p.h>
@ -128,3 +128,4 @@ volatile std::array<bool, ${array_count}> ${coreDef.name.toLowerCase()}_init = {
} }
#endif #endif
} }
// clang-format on

3
gen_input/templates/asmjit/CORENAME.cpp.gtl
View File

@ -29,7 +29,7 @@
* POSSIBILITY OF SUCH DAMAGE. * POSSIBILITY OF SUCH DAMAGE.
* *
*******************************************************************************/ *******************************************************************************/
// clang-format off
#include <iss/arch/${coreDef.name.toLowerCase()}.h> #include <iss/arch/${coreDef.name.toLowerCase()}.h>
#include <iss/debugger/gdb_session.h> #include <iss/debugger/gdb_session.h>
#include <iss/debugger/server.h> #include <iss/debugger/server.h>
@ -278,3 +278,4 @@ volatile std::array<bool, 2> dummy = {
}; };
} }
} }
// clang-format on

2
gen_input/templates/interp/CORENAME.cpp.gtl
View File

@ -34,6 +34,7 @@ def nativeTypeSize(int size){
if(size<=8) return 8; else if(size<=16) return 16; else if(size<=32) return 32; else return 64; if(size<=8) return 8; else if(size<=16) return 16; else if(size<=32) return 32; else return 64;
} }
%> %>
// clang-format off
#include <iss/arch/${coreDef.name.toLowerCase()}.h> #include <iss/arch/${coreDef.name.toLowerCase()}.h>
#include <iss/debugger/gdb_session.h> #include <iss/debugger/gdb_session.h>
#include <iss/debugger/server.h> #include <iss/debugger/server.h>
@ -377,3 +378,4 @@ volatile std::array<bool, 2> dummy = {
}; };
} }
} }
// clang-format on

3
gen_input/templates/llvm/CORENAME.cpp.gtl
View File

@ -29,7 +29,7 @@
* POSSIBILITY OF SUCH DAMAGE. * POSSIBILITY OF SUCH DAMAGE.
* *
*******************************************************************************/ *******************************************************************************/
// clang-format off
#include <iss/arch/${coreDef.name.toLowerCase()}.h> #include <iss/arch/${coreDef.name.toLowerCase()}.h>
#include <iss/debugger/gdb_session.h> #include <iss/debugger/gdb_session.h>
#include <iss/debugger/server.h> #include <iss/debugger/server.h>
@ -380,3 +380,4 @@ volatile std::array<bool, 2> dummy = {
}; };
} }
} }
// clang-format on

3
gen_input/templates/tcc/CORENAME.cpp.gtl
View File

@ -29,7 +29,7 @@
* POSSIBILITY OF SUCH DAMAGE. * POSSIBILITY OF SUCH DAMAGE.
* *
*******************************************************************************/ *******************************************************************************/
// clang-format off
#include <iss/arch/${coreDef.name.toLowerCase()}.h> #include <iss/arch/${coreDef.name.toLowerCase()}.h>
#include <iss/debugger/gdb_session.h> #include <iss/debugger/gdb_session.h>
#include <iss/debugger/server.h> #include <iss/debugger/server.h>
@ -344,3 +344,4 @@ volatile std::array<bool, 2> dummy = {
}; };
} }
} }
// clang-format on

28
src/iss/arch/tgc5c.cpp
View File

@ -30,12 +30,13 @@
* *
*******************************************************************************/ *******************************************************************************/
// clang-format off
#include "tgc5c.h" #include "tgc5c.h"
#include "util/ities.h" #include "util/ities.h"
#include <util/logging.h>
#include <cstdio> #include <cstdio>
#include <cstring> #include <cstring>
#include <fstream> #include <fstream>
#include <util/logging.h>
using namespace iss::arch; using namespace iss::arch;
@ -50,17 +51,20 @@ tgc5c::~tgc5c() = default;
void tgc5c::reset(uint64_t address) { void tgc5c::reset(uint64_t address) {
auto base_ptr = reinterpret_cast<traits<tgc5c>::reg_t*>(get_regs_base_ptr()); auto base_ptr = reinterpret_cast<traits<tgc5c>::reg_t*>(get_regs_base_ptr());
for(size_t i = 0; i < traits<tgc5c>::NUM_REGS; ++i) for(size_t i=0; i<traits<tgc5c>::NUM_REGS; ++i)
*(base_ptr + i) = 0; *(base_ptr+i)=0;
reg.PC = address; reg.PC=address;
reg.NEXT_PC = reg.PC; reg.NEXT_PC=reg.PC;
reg.PRIV = 0x3; reg.PRIV=0x3;
reg.trap_state = 0; reg.trap_state=0;
reg.icount = 0; reg.icount=0;
} }
uint8_t* tgc5c::get_regs_base_ptr() { return reinterpret_cast<uint8_t*>(&reg); } uint8_t *tgc5c::get_regs_base_ptr() {
return reinterpret_cast<uint8_t*>(&reg);
tgc5c::phys_addr_t tgc5c::virt2phys(const iss::addr_t& addr) {
return phys_addr_t(addr.access, addr.space, addr.val & traits<tgc5c>::addr_mask);
} }
tgc5c::phys_addr_t tgc5c::virt2phys(const iss::addr_t &addr) {
return phys_addr_t(addr.access, addr.space, addr.val&traits<tgc5c>::addr_mask);
}
// clang-format on

97
src/iss/arch/tgc5c.h
View File

@ -32,7 +32,7 @@
#ifndef _TGC5C_H_ #ifndef _TGC5C_H_
#define _TGC5C_H_ #define _TGC5C_H_
// clang-format off
#include <array> #include <array>
#include <iss/arch/traits.h> #include <iss/arch/traits.h>
#include <iss/arch_if.h> #include <iss/arch_if.h>
@ -47,95 +47,35 @@ template <> struct traits<tgc5c> {
constexpr static char const* const core_type = "TGC5C"; constexpr static char const* const core_type = "TGC5C";
static constexpr std::array<const char*, 36> reg_names{{"x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", static constexpr std::array<const char*, 36> reg_names{
"x9", "x10", "x11", "x12", "x13", "x14", "x15", "x16", "x17", {"x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28", "x29", "x30", "x31", "pc", "next_pc", "priv", "dpc"}};
"x18", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26",
"x27", "x28", "x29", "x30", "x31", "pc", "next_pc", "priv", "dpc"}};
static constexpr std::array<const char*, 36> reg_aliases{ static constexpr std::array<const char*, 36> reg_aliases{
{"zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", "s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5", "a6", "a7", {"zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", "s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5", "a6", "a7", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6", "pc", "next_pc", "priv", "dpc"}};
"s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6", "pc", "next_pc", "priv", "dpc"}};
enum constants { enum constants {MISA_VAL=1073746180ULL, MARCHID_VAL=2147483651ULL, XLEN=32ULL, INSTR_ALIGNMENT=2ULL, RFS=32ULL, fence=0ULL, fencei=1ULL, fencevmal=2ULL, fencevmau=3ULL, CSR_SIZE=4096ULL, MUL_LEN=64ULL};
MISA_VAL = 1073746180ULL,
MARCHID_VAL = 2147483651ULL,
XLEN = 32ULL,
INSTR_ALIGNMENT = 2ULL,
RFS = 32ULL,
fence = 0ULL,
fencei = 1ULL,
fencevmal = 2ULL,
fencevmau = 3ULL,
CSR_SIZE = 4096ULL,
MUL_LEN = 64ULL
};
constexpr static unsigned FP_REGS_SIZE = 0; constexpr static unsigned FP_REGS_SIZE = 0;
enum reg_e { enum reg_e {
X0, X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X12, X13, X14, X15, X16, X17, X18, X19, X20, X21, X22, X23, X24, X25, X26, X27, X28, X29, X30, X31, PC, NEXT_PC, PRIV, DPC, NUM_REGS, TRAP_STATE=NUM_REGS, PENDING_TRAP, ICOUNT, CYCLE, INSTRET, INSTRUCTION, LAST_BRANCH
X1,
X2,
X3,
X4,
X5,
X6,
X7,
X8,
X9,
X10,
X11,
X12,
X13,
X14,
X15,
X16,
X17,
X18,
X19,
X20,
X21,
X22,
X23,
X24,
X25,
X26,
X27,
X28,
X29,
X30,
X31,
PC,
NEXT_PC,
PRIV,
DPC,
NUM_REGS,
TRAP_STATE = NUM_REGS,
PENDING_TRAP,
ICOUNT,
CYCLE,
INSTRET,
INSTRUCTION,
LAST_BRANCH
}; };
using reg_t = uint32_t; using reg_t = uint32_t;
using addr_t = uint32_t; using addr_t = uint32_t;
using code_word_t = uint32_t; // TODO: check removal using code_word_t = uint32_t; //TODO: check removal
using virt_addr_t = iss::typed_addr_t<iss::address_type::VIRTUAL>; using virt_addr_t = iss::typed_addr_t<iss::address_type::VIRTUAL>;
using phys_addr_t = iss::typed_addr_t<iss::address_type::PHYSICAL>; using phys_addr_t = iss::typed_addr_t<iss::address_type::PHYSICAL>;
static constexpr std::array<const uint32_t, 43> reg_bit_widths{{32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, static constexpr std::array<const uint32_t, 43> reg_bit_widths{
32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, {32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,8,32,32,32,64,64,64,32,32}};
32, 32, 32, 32, 8, 32, 32, 32, 64, 64, 64, 32, 32}};
static constexpr std::array<const uint32_t, 43> reg_byte_offsets{ static constexpr std::array<const uint32_t, 43> reg_byte_offsets{
{0, 4, 8, 12, 16, 20, 24, 28, 32, 36, 40, 44, 48, 52, 56, 60, 64, 68, 72, 76, 80, 84, {0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,137,141,145,149,157,165,173,177}};
88, 92, 96, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 137, 141, 145, 149, 157, 165, 173, 177}};
static const uint64_t addr_mask = (reg_t(1) << (XLEN - 1)) | ((reg_t(1) << (XLEN - 1)) - 1); static const uint64_t addr_mask = (reg_t(1) << (XLEN - 1)) | ((reg_t(1) << (XLEN - 1)) - 1);
@ -235,7 +175,7 @@ template <> struct traits<tgc5c> {
}; };
}; };
struct tgc5c : public arch_if { struct tgc5c: public arch_if {
using virt_addr_t = typename traits<tgc5c>::virt_addr_t; using virt_addr_t = typename traits<tgc5c>::virt_addr_t;
using phys_addr_t = typename traits<tgc5c>::phys_addr_t; using phys_addr_t = typename traits<tgc5c>::phys_addr_t;
@ -245,7 +185,7 @@ struct tgc5c : public arch_if {
tgc5c(); tgc5c();
~tgc5c(); ~tgc5c();
void reset(uint64_t address = 0) override; void reset(uint64_t address=0) override;
uint8_t* get_regs_base_ptr() override; uint8_t* get_regs_base_ptr() override;
@ -261,6 +201,7 @@ struct tgc5c : public arch_if {
inline uint32_t get_last_branch() { return reg.last_branch; } inline uint32_t get_last_branch() { return reg.last_branch; }
#pragma pack(push, 1) #pragma pack(push, 1)
struct TGC5C_regs { struct TGC5C_regs {
uint32_t X0 = 0; uint32_t X0 = 0;
@ -309,12 +250,14 @@ struct tgc5c : public arch_if {
#pragma pack(pop) #pragma pack(pop)
std::array<address_type, 4> addr_mode; std::array<address_type, 4> addr_mode;
uint64_t interrupt_sim = 0; uint64_t interrupt_sim=0;
uint32_t get_fcsr(){return 0;}
void set_fcsr(uint32_t val){}
uint32_t get_fcsr() { return 0; }
void set_fcsr(uint32_t val) {}
}; };
} // namespace arch }
} // namespace iss }
#endif /* _TGC5C_H_ */ #endif /* _TGC5C_H_ */
// clang-format on

2113
src/vm/interp/vm_tgc5c.cpp
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