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DBT-RISE-TGC
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[WIP] Cleanup of namespaces etc to get compile clean

This commit is contained in:
Eyck Jentzsch 2020-01-10 09:37:48 +01:00
parent fd2e40bfd2
commit e483887c43
15 changed files with 2673 additions and 81 deletions
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3
CMakeLists.txt
View File

@ -50,8 +50,9 @@ set(LIB_SOURCES
#src/iss/rv64gc.cpp
src/iss/mnrv32.cpp
src/vm/llvm/fp_functions.cpp
src/vm/llvm/vm_mnrv32.cpp
#src/vm/llvm/vm_rv32gc.cpp
src/vm/llvm/vm_rv32imac.cpp
#src/vm/llvm/vm_rv32imac.cpp
#src/vm/llvm/vm_rv64i.cpp
#src/vm/llvm/vm_rv64gc.cpp
src/vm/tcc/vm_mnrv32.cpp

18
gen_input/templates/interp/vm-vm_CORENAME.cpp.gtl
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@ -53,13 +53,15 @@ namespace ${coreDef.name.toLowerCase()} {
using namespace iss::arch;
using namespace iss::debugger;
template <typename ARCH> class vm_impl : public vm::interp::vm_base<ARCH> {
template <typename ARCH> class vm_impl : public iss::interp::vm_base<ARCH> {
public:
using super = typename vm::interp::vm_base<ARCH>;
using super = typename iss::interp::vm_base<ARCH>;
using virt_addr_t = typename super::virt_addr_t;
using phys_addr_t = typename super::phys_addr_t;
using code_word_t = typename super::code_word_t;
using addr_t = typename super::addr_t;
using reg_t = typename traits<ARCH>::reg_t;
using iss::interp::vm_base<ARCH>::get_reg;
vm_impl();
@ -69,9 +71,9 @@ public:
target_adapter_if *accquire_target_adapter(server_if *srv) override {
debugger_if::dbg_enabled = true;
if (vm::interp::vm_base<ARCH>::tgt_adapter == nullptr)
vm::interp::vm_base<ARCH>::tgt_adapter = new riscv_target_adapter<ARCH>(srv, this->get_arch());
return vm::interp::vm_base<ARCH>::tgt_adapter;
if (super::tgt_adapter == nullptr)
super::tgt_adapter = new riscv_target_adapter<ARCH>(srv, this->get_arch());
return super::tgt_adapter;
}
protected:
@ -177,7 +179,7 @@ template <typename ARCH> vm_impl<ARCH>::vm_impl() { this(new ARCH()); }
template <typename ARCH>
vm_impl<ARCH>::vm_impl(ARCH &core, unsigned core_id, unsigned cluster_id)
: vm::interp::vm_base<ARCH>(core, core_id, cluster_id) {
: vm_base<ARCH>(core, core_id, cluster_id) {
qlut[0] = lut_00.data();
qlut[1] = lut_01.data();
qlut[2] = lut_10.data();
@ -189,7 +191,7 @@ vm_impl<ARCH>::vm_impl(ARCH &core, unsigned core_id, unsigned cluster_id)
}
template <typename ARCH>
typename vm::interp::vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_single_inst(virt_addr_t pc) {
typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_single_inst(virt_addr_t pc) {
// we fetch at max 4 byte, alignment is 2
enum {TRAP_ID=1<<16};
code_word_t insn = 0;
@ -225,5 +227,5 @@ std::unique_ptr<vm_if> create<arch::${coreDef.name.toLowerCase()}>(arch::${coreD
if (port != 0) debugger::server<debugger::gdb_session>::run_server(ret, port);
return std::unique_ptr<vm_if>(ret);
}
}
} // namespace interp
} // namespace iss

12
gen_input/templates/llvm/vm-vm_CORENAME.cpp.gtl
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@ -49,19 +49,17 @@
namespace iss {
namespace llvm {
namespace fp_impl {
void add_fp_functions_2_module(llvm::Module *, unsigned, unsigned);
}
void add_fp_functions_2_module(::llvm::Module *, unsigned, unsigned);
}
namespace ${coreDef.name.toLowerCase()} {
using namespace ::llvm;
using namespace iss::arch;
using namespace llvm;
using namespace iss::debugger;
using namespace iss::vm::llvm;
template <typename ARCH> class vm_impl : public vm_base<ARCH> {
template <typename ARCH> class vm_impl : public vm::llvm::vm_base<ARCH> {
public:
using super = typename iss::vm::llvm::vm_base<ARCH>;
using super = typename iss::llvm::vm_base<ARCH>;
using virt_addr_t = typename super::virt_addr_t;
using phys_addr_t = typename super::phys_addr_t;
using code_word_t = typename super::code_word_t;
@ -323,5 +321,5 @@ std::unique_ptr<vm_if> create<arch::${coreDef.name.toLowerCase()}>(arch::${coreD
if (port != 0) debugger::server<debugger::gdb_session>::run_server(ret, port);
return std::unique_ptr<vm_if>(ret);
}
} // namespace llvm
} // namespace iss

7
gen_input/templates/tcc/vm-vm_CORENAME.cpp.gtl
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@ -52,11 +52,10 @@ namespace tcc {
namespace ${coreDef.name.toLowerCase()} {
using namespace iss::arch;
using namespace iss::debugger;
using namespace iss::vm::tcc;
template <typename ARCH> class vm_impl : public vm_base<ARCH> {
template <typename ARCH> class vm_impl : public iss::tcc::vm_base<ARCH> {
public:
using super = typename iss::vm::tcc::vm_base<ARCH>;
using super = typename iss::tcc::vm_base<ARCH>;
using virt_addr_t = typename super::virt_addr_t;
using phys_addr_t = typename super::phys_addr_t;
using code_word_t = typename super::code_word_t;
@ -92,7 +91,7 @@ protected:
return nullptr;
}
void setup_module(Module* m) override {
void setup_module(std::string m) override {
super::setup_module(m);
}

2
incl/sysc/core_complex.h
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@ -75,8 +75,6 @@ class core_wrapper;
class core_complex : public sc_core::sc_module, public scc::traceable {
public:
SC_HAS_PROCESS(core_complex);// NOLINT
scc::initiator_mixin<scv4tlm::tlm_rec_initiator_socket<32>> initiator;
sc_core::sc_in<sc_core::sc_time> clk_i;

26
src/main.cpp
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@ -36,10 +36,7 @@
#include <boost/lexical_cast.hpp>
#include <boost/program_options.hpp>
#include <iss/arch/riscv_hart_msu_vp.h>
#include <iss/arch/rv32imac.h>
#include <iss/arch/rv32gc.h>
#include <iss/arch/rv64gc.h>
#include <iss/arch/rv64i.h>
#include <iss/arch/mnrv32.h>
#include <iss/llvm/jit_helper.h>
#include <iss/log_categories.h>
#include <iss/plugin/cycle_estimate.h>
@ -107,26 +104,9 @@ int main(int argc, char *argv[]) {
std::unique_ptr<iss::vm_if> vm{nullptr};
std::unique_ptr<iss::arch_if> cpu{nullptr};
std::string isa_opt(clim["isa"].as<std::string>());
// if (isa_opt=="rv64ia") {
// iss::arch::rv64i* lcpu = new iss::arch::riscv_hart_msu_vp<iss::arch::rv64i>();
// vm = iss::llvm::create(lcpu, clim["gdb-port"].as<unsigned>());
// cpu.reset(lcpu);
// } else if (isa_opt=="rv64gc") {
// iss::arch::rv64gc* lcpu = new iss::arch::riscv_hart_msu_vp<iss::arch::rv64gc>();
// vm = iss::llvm::create(lcpu, clim["gdb-port"].as<unsigned>());
// cpu.reset(lcpu);
// } else if (isa_opt=="rv32imac") {
iss::arch::rv32imac* lcpu = new iss::arch::riscv_hart_msu_vp<iss::arch::rv32imac>();
iss::arch::mnrv32* lcpu = new iss::arch::riscv_hart_msu_vp<iss::arch::mnrv32>();
vm = iss::llvm::create(lcpu, clim["gdb-port"].as<unsigned>());
cpu.reset(lcpu);
// } else if (isa_opt=="rv32gc") {
// iss::arch::rv32gc* lcpu = new iss::arch::riscv_hart_msu_vp<iss::arch::rv32gc>();
// vm = iss::llvm::create(lcpu, clim["gdb-port"].as<unsigned>());
// cpu.reset(lcpu);
// } else {
// LOG(ERROR) << "Illegal argument value for '--isa': " << clim["isa"].as<std::string>() << std::endl;
// return 127;
// }
if (clim.count("plugin")) {
for (std::string opt_val : clim["plugin"].as<std::vector<std::string>>()) {
std::string plugin_name{opt_val};
@ -162,7 +142,7 @@ int main(int argc, char *argv[]) {
}
uint64_t start_address = 0;
if (clim.count("mem"))
vm->get_arch()->load_file(clim["mem"].as<std::string>(), iss::arch::traits<iss::arch::rv32imac>::MEM);
vm->get_arch()->load_file(clim["mem"].as<std::string>(), iss::arch::traits<iss::arch::mnrv32>::MEM);
if (clim.count("elf"))
for (std::string input : clim["elf"].as<std::vector<std::string>>()) {
auto start_addr = vm->get_arch()->load_file(input);

16
src/sysc/core_complex.cpp
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@ -32,7 +32,8 @@
#include "sysc/core_complex.h"
#include "iss/arch/riscv_hart_msu_vp.h"
#include "iss/arch/rv32imac.h"
//#include "iss/arch/rv32imac.h"
#include "iss/arch/mnrv32.h"
#include "iss/debugger/encoderdecoder.h"
#include "iss/debugger/gdb_session.h"
#include "iss/debugger/server.h"
@ -59,6 +60,9 @@ namespace {
iss::debugger::encoder_decoder encdec;
}
//using core_type = iss::arch::rv32imac;
using core_type = iss::arch::mnrv32;
namespace {
std::array<const char, 4> lvl = {{'U', 'S', 'H', 'M'}};
@ -87,11 +91,10 @@ std::array<const char*, 12> irq_str = { {
"User external interrupt", "Supervisor external interrupt", "Reserved", "Machine external interrupt" } };
}
class core_wrapper : public iss::arch::riscv_hart_msu_vp<iss::arch::rv32imac> {
class core_wrapper : public iss::arch::riscv_hart_msu_vp<core_type> {
public:
using core_type = arch::rv32imac;
using base_type = arch::riscv_hart_msu_vp<arch::rv32imac>;
using phys_addr_t = typename arch::traits<arch::rv32imac>::phys_addr_t;
using base_type = arch::riscv_hart_msu_vp<core_type>;
using phys_addr_t = typename arch::traits<core_type>::phys_addr_t;
core_wrapper(core_complex *owner)
: owner(owner)
{
@ -252,6 +255,7 @@ core_complex::core_complex(sc_module_name name)
, fetch_tr_handle(nullptr)
#endif
{
SC_HAS_PROCESS(core_complex);// NOLINT
initiator.register_invalidate_direct_mem_ptr([=](uint64_t start, uint64_t end) -> void {
auto lut_entry = read_lut.getEntry(start);
if (lut_entry.get_granted_access() != tlm::tlm_dmi::DMI_ACCESS_NONE && end <= lut_entry.get_end_address() + 1) {
@ -282,7 +286,7 @@ void core_complex::trace(sc_trace_file *trf) const {}
void core_complex::before_end_of_elaboration() {
cpu = scc::make_unique<core_wrapper>(this);
vm = llvm::create<arch::rv32imac>(cpu.get(), gdb_server_port.get_value(), dump_ir.get_value());
vm = llvm::create<core_type>(cpu.get(), gdb_server_port.get_value(), dump_ir.get_value());
#ifdef WITH_SCV
vm->setDisassEnabled(enable_disass.get_value() || m_db != nullptr);
#else

45
src/vm/interp/vm_mnrv32.cpp
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@ -53,13 +53,15 @@ namespace mnrv32 {
using namespace iss::arch;
using namespace iss::debugger;
template <typename ARCH> class vm_impl : public vm::interp::vm_base<ARCH> {
template <typename ARCH> class vm_impl : public iss::interp::vm_base<ARCH> {
public:
using super = typename vm::interp::vm_base<ARCH>;
using super = typename iss::interp::vm_base<ARCH>;
using virt_addr_t = typename super::virt_addr_t;
using phys_addr_t = typename super::phys_addr_t;
using code_word_t = typename super::code_word_t;
using addr_t = typename super::addr_t;
using reg_t = typename traits<ARCH>::reg_t;
using iss::interp::vm_base<ARCH>::get_reg;
vm_impl();
@ -69,9 +71,9 @@ public:
target_adapter_if *accquire_target_adapter(server_if *srv) override {
debugger_if::dbg_enabled = true;
if (vm::interp::vm_base<ARCH>::tgt_adapter == nullptr)
vm::interp::vm_base<ARCH>::tgt_adapter = new riscv_target_adapter<ARCH>(srv, this->get_arch());
return vm::interp::vm_base<ARCH>::tgt_adapter;
if (super::tgt_adapter == nullptr)
super::tgt_adapter = new riscv_target_adapter<ARCH>(srv, this->get_arch());
return super::tgt_adapter;
}
protected:
@ -266,6 +268,33 @@ private:
/* instruction 2: JAL */
compile_ret_t __jal(virt_addr_t& pc, code_word_t instr){
this->do_sync(PRE_SYNC, 2);
uint8_t rd = ((bit_sub<7,5>(instr)));
int32_t imm = signextend<int32_t,21>((bit_sub<12,8>(instr) << 12) | (bit_sub<20,1>(instr) << 11) | (bit_sub<21,10>(instr) << 1) | (bit_sub<31,1>(instr) << 20));
if(this->disass_enabled){
/* generate console output when executing the command */
auto mnemonic = fmt::format(
"{mnemonic:10} {rd}, {imm:#0x}", fmt::arg("mnemonic", "jal"),
fmt::arg("rd", name(rd)), fmt::arg("imm", imm));
this->core.disass_output(pc.val, mnemonic);
}
auto cur_pc = pc.val;
pc=pc+4;
if(rd != 0){
auto& rs = this->template get_reg<reg_t>(traits<ARCH>::X0 + rd);
rs=pc.val;
}
auto& pc_reg = this->template get_reg<reg_t>(arch::traits<ARCH>::PC);
pc_reg = cur_pc+imm;
this->do_sync(POST_SYNC, 2);
auto& trap_state = this->template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
if(trap_state!=0){
auto& last_br = this->template get_reg<uint32_t>(arch::traits<ARCH>::LAST_BRANCH);
last_br = std::numeric_limits<uint32_t>::max();
this->core.enter_trap(trap_state, cur_pc);
pc.val=this->template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC);
}
return pc;
}
/* instruction 3: JALR */
@ -482,7 +511,7 @@ template <typename ARCH> vm_impl<ARCH>::vm_impl() { this(new ARCH()); }
template <typename ARCH>
vm_impl<ARCH>::vm_impl(ARCH &core, unsigned core_id, unsigned cluster_id)
: vm::interp::vm_base<ARCH>(core, core_id, cluster_id) {
: vm_base<ARCH>(core, core_id, cluster_id) {
qlut[0] = lut_00.data();
qlut[1] = lut_01.data();
qlut[2] = lut_10.data();
@ -494,7 +523,7 @@ vm_impl<ARCH>::vm_impl(ARCH &core, unsigned core_id, unsigned cluster_id)
}
template <typename ARCH>
typename vm::interp::vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_single_inst(virt_addr_t pc) {
typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_single_inst(virt_addr_t pc) {
// we fetch at max 4 byte, alignment is 2
enum {TRAP_ID=1<<16};
code_word_t insn = 0;
@ -530,5 +559,5 @@ std::unique_ptr<vm_if> create<arch::mnrv32>(arch::mnrv32 *core, unsigned short p
if (port != 0) debugger::server<debugger::gdb_session>::run_server(ret, port);
return std::unique_ptr<vm_if>(ret);
}
}
} // namespace interp
} // namespace iss

6
src/vm/llvm/fp_functions.cpp
View File

@ -44,10 +44,11 @@ extern "C" {
#include <limits>
namespace iss {
namespace vm {
namespace llvm {
namespace fp_impl {
using namespace std;
using namespace ::llvm;
#define INT_TYPE(L) Type::getIntNTy(mod->getContext(), L)
#define FLOAT_TYPE Type::getFloatTy(mod->getContext())
@ -65,10 +66,9 @@ using namespace std;
#define FDECL(NAME, RET, ...) \
std::vector<Type *> NAME##_args{__VA_ARGS__}; \
FunctionType *NAME##_type = llvm::FunctionType::get(RET, NAME##_args, false); \
FunctionType *NAME##_type = FunctionType::get(RET, NAME##_args, false); \
mod->getOrInsertFunction(#NAME, NAME##_type);
using namespace llvm;
void add_fp_functions_2_module(Module *mod, uint32_t flen, uint32_t xlen) {
if(flen){

2582
src/vm/llvm/vm_mnrv32.cpp Normal file
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File diff suppressed because it is too large Load Diff

4
src/vm/llvm/vm_rv32gc.cpp
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@ -47,7 +47,7 @@
#include <iss/debugger/riscv_target_adapter.h>
namespace iss {
namespace vm {
namespace llvm {
namespace fp_impl {
void add_fp_functions_2_module(llvm::Module *, unsigned, unsigned);
}
@ -91,7 +91,7 @@ protected:
void setup_module(Module* m) override {
super::setup_module(m);
iss::vm::fp_impl::add_fp_functions_2_module(m, traits<ARCH>::FP_REGS_SIZE, traits<ARCH>::XLEN);
iss::llvm::fp_impl::add_fp_functions_2_module(m, traits<ARCH>::FP_REGS_SIZE, traits<ARCH>::XLEN);
}
inline Value *gen_choose(Value *cond, Value *trueVal, Value *falseVal, unsigned size) {

12
src/vm/llvm/vm_rv32imac.cpp
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@ -47,21 +47,21 @@
#include <iss/debugger/riscv_target_adapter.h>
namespace iss {
namespace vm {
namespace llvm {
namespace fp_impl {
void add_fp_functions_2_module(llvm::Module *, unsigned, unsigned);
}
}
namespace llvm {
namespace rv32imac {
using namespace iss::arch;
using namespace llvm;
using namespace iss::debugger;
using namespace iss::llvm;
using namespace iss::vm::llvm;
template <typename ARCH> class vm_impl : public vm_base<ARCH> {
public:
using super = typename iss::llvm::vm_base<ARCH>;
using super = typename iss::vm::llvm::vm_base<ARCH>;
using virt_addr_t = typename super::virt_addr_t;
using phys_addr_t = typename super::phys_addr_t;
using code_word_t = typename super::code_word_t;
@ -91,7 +91,7 @@ protected:
void setup_module(Module* m) override {
super::setup_module(m);
iss::vm::fp_impl::add_fp_functions_2_module(m, traits<ARCH>::FP_REGS_SIZE, traits<ARCH>::XLEN);
iss::llvm::fp_impl::add_fp_functions_2_module(m, traits<ARCH>::FP_REGS_SIZE, traits<ARCH>::XLEN);
}
inline Value *gen_choose(Value *cond, Value *trueVal, Value *falseVal, unsigned size) {
@ -4815,5 +4815,5 @@ std::unique_ptr<vm_if> create<arch::rv32imac>(arch::rv32imac *core, unsigned sho
if (port != 0) debugger::server<debugger::gdb_session>::run_server(ret, port);
return std::unique_ptr<vm_if>(ret);
}
}
} // namespace iss

4
src/vm/llvm/vm_rv64gc.cpp
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@ -47,7 +47,7 @@
#include <iss/debugger/riscv_target_adapter.h>
namespace iss {
namespace vm {
namespace llvm {
namespace fp_impl {
void add_fp_functions_2_module(llvm::Module *, unsigned, unsigned);
}
@ -91,7 +91,7 @@ protected:
void setup_module(Module* m) override {
super::setup_module(m);
iss::vm::fp_impl::add_fp_functions_2_module(m, traits<ARCH>::FP_REGS_SIZE, traits<ARCH>::XLEN);
iss::llvm::fp_impl::add_fp_functions_2_module(m, traits<ARCH>::FP_REGS_SIZE, traits<ARCH>::XLEN);
}
inline Value *gen_choose(Value *cond, Value *trueVal, Value *falseVal, unsigned size) {

4
src/vm/llvm/vm_rv64i.cpp
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@ -47,7 +47,7 @@
#include <iss/debugger/riscv_target_adapter.h>
namespace iss {
namespace vm {
namespace llvm {
namespace fp_impl {
void add_fp_functions_2_module(llvm::Module *, unsigned, unsigned);
}
@ -91,7 +91,7 @@ protected:
void setup_module(Module* m) override {
super::setup_module(m);
iss::vm::fp_impl::add_fp_functions_2_module(m, traits<ARCH>::FP_REGS_SIZE, traits<ARCH>::XLEN);
iss::llvm::fp_impl::add_fp_functions_2_module(m, traits<ARCH>::FP_REGS_SIZE, traits<ARCH>::XLEN);
}
inline Value *gen_choose(Value *cond, Value *trueVal, Value *falseVal, unsigned size) {

7
src/vm/tcc/vm_mnrv32.cpp
View File

@ -52,11 +52,10 @@ namespace tcc {
namespace mnrv32 {
using namespace iss::arch;
using namespace iss::debugger;
using namespace iss::vm::tcc;
template <typename ARCH> class vm_impl : public vm_base<ARCH> {
template <typename ARCH> class vm_impl : public iss::tcc::vm_base<ARCH> {
public:
using super = typename iss::vm::tcc::vm_base<ARCH>;
using super = typename iss::tcc::vm_base<ARCH>;
using virt_addr_t = typename super::virt_addr_t;
using phys_addr_t = typename super::phys_addr_t;
using code_word_t = typename super::code_word_t;
@ -92,7 +91,7 @@ protected:
return nullptr;
}
void setup_module(Module* m) override {
void setup_module(std::string m) override {
super::setup_module(m);
}