DBT-RISE/DBT-RISE-TGC
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add factory for ISS and use it in main.cpp

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This commit is contained in:
Eyck Jentzsch
2021-05-16 16:44:14 +02:00
parent a35974c9f5
commit d41e1d816a
2 changed files with 67 additions and 11 deletions
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16
src/sysc/core_complex.cpp
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@@ -58,7 +58,7 @@ using tgc_d_plat_type = iss::arch::riscv_hart_mu_p<iss::arch::tgc_d>;
#define STR(X) #X
#define CREATE_CORE(CN) \
else if (type == STR(CN)) { std::tie(cpu, vm) = create_core<CN ## _plat_type>(backend, gdb_port, hart_id); }
if (type == STR(CN)) { std::tie(cpu, vm) = create_core<CN ## _plat_type>(backend, gdb_port, hart_id); } else
#ifdef WITH_SCV
#include <array>
@@ -261,19 +261,14 @@ public:
}
void create_cpu(std::string const& type, std::string const& backend, unsigned gdb_port, uint32_t hart_id){
if (type == "") {
LOG(ERROR) << "Illegal argument value for core type: " << type << std::endl;
}
CREATE_CORE(tgc_c)
#ifdef CORE_TGC_B
CREATE_CORE(tgc_c)
#endif
#ifdef CORE_TGC_C
CREATE_CORE(tgc_c)
CREATE_CORE(tgc_c)
#endif
#ifdef CORE_TGC_D
CREATE_CORE(tgc_d)
CREATE_CORE(tgc_d)
#endif
else {
{
LOG(ERROR) << "Illegal argument value for core type: " << type << std::endl;
}
auto *srv = debugger::server<debugger::gdb_session>::get();
@@ -286,7 +281,6 @@ public:
}
core_complex * const owner;
vm_ptr vm{nullptr};
cpu_ptr cpu{nullptr};