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Merge branch 'feature/privilege_refactor' into develop

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This commit is contained in:
Eyck Jentzsch
2025-03-14 20:00:07 +01:00
parent 71260a3ef4 502f3e8df9
commit cfc980a069
12 changed files with 1805 additions and 2588 deletions
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543
src/iss/arch/riscv_hart_common.h
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@@ -1,5 +1,5 @@
/*******************************************************************************
* Copyright (C) 2017, 2018, 2021 MINRES Technologies GmbH
* Copyright (C) 2017 - 2025 MINRES Technologies GmbH
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -35,18 +35,25 @@
#ifndef _RISCV_HART_COMMON
#define _RISCV_HART_COMMON
#include "iss/arch/traits.h"
#include "iss/log_categories.h"
#include "iss/mmio/memory_if.h"
#include "iss/vm_types.h"
#include "mstatus.h"
#include "util/delegate.h"
#include <array>
#include <cstdint>
#include <elfio/elfio.hpp>
#include <fmt/format.h>
#include <iss/arch_if.h>
#include <iss/log_categories.h>
#include <iss/semihosting/semihosting.h>
#include <limits>
#include <sstream>
#include <string>
#include <unordered_map>
#include <util/logging.h>
#include <util/sparse_array.h>
#if defined(__GNUC__)
#define likely(x) ::__builtin_expect(!!(x), 1)
@@ -59,7 +66,7 @@
namespace iss {
namespace arch {
enum features_e { FEAT_NONE, FEAT_PMP = 1, FEAT_EXT_N = 2, FEAT_CLIC = 4, FEAT_DEBUG = 8, FEAT_TCM = 16 };
enum features_e { FEAT_NONE, FEAT_EXT_N = 1, FEAT_DEBUG = 2 };
enum riscv_csr {
/* user-level CSR */
@@ -235,10 +242,6 @@ struct vm_info {
};
struct feature_config {
uint64_t clic_base{0xc0000000};
unsigned clic_int_ctl_bits{4};
unsigned clic_num_irq{16};
unsigned clic_num_trigger{0};
uint64_t tcm_base{0x10000000};
uint64_t tcm_size{0x8000};
uint64_t io_address{0xf0000000};
@@ -271,62 +274,145 @@ public:
: trap_access(15 << 16, badaddr) {}
};
inline void read_reg_uint32(uint64_t offs, uint32_t& reg, uint8_t* const data, unsigned length) {
auto reg_ptr = reinterpret_cast<uint8_t*>(&reg);
switch(offs & 0x3) {
case 0:
for(auto i = 0U; i < length; ++i)
*(data + i) = *(reg_ptr + i);
break;
case 1:
for(auto i = 0U; i < length; ++i)
*(data + i) = *(reg_ptr + 1 + i);
break;
case 2:
for(auto i = 0U; i < length; ++i)
*(data + i) = *(reg_ptr + 2 + i);
break;
case 3:
*data = *(reg_ptr + 3);
break;
}
}
template <typename WORD_TYPE> struct priv_if {
using rd_csr_f = std::function<iss::status(unsigned addr, WORD_TYPE&)>;
using wr_csr_f = std::function<iss::status(unsigned addr, WORD_TYPE)>;
inline void write_reg_uint32(uint64_t offs, uint32_t& reg, const uint8_t* const data, unsigned length) {
auto reg_ptr = reinterpret_cast<uint8_t*>(&reg);
switch(offs & 0x3) {
case 0:
for(auto i = 0U; i < length; ++i)
*(reg_ptr + i) = *(data + i);
break;
case 1:
for(auto i = 0U; i < length; ++i)
*(reg_ptr + 1 + i) = *(data + i);
break;
case 2:
for(auto i = 0U; i < length; ++i)
*(reg_ptr + 2 + i) = *(data + i);
break;
case 3:
*(reg_ptr + 3) = *data;
break;
}
}
struct riscv_hart_common {
riscv_hart_common(){};
std::function<iss::status(unsigned, WORD_TYPE&)> read_csr;
std::function<iss::status(unsigned, WORD_TYPE)> write_csr;
std::function<iss::status(uint8_t const*)> exec_htif;
std::unordered_map<unsigned, rd_csr_f>& csr_rd_cb;
std::unordered_map<unsigned, wr_csr_f>& csr_wr_cb;
hart_state<WORD_TYPE>& mstatus;
uint64_t& tohost;
uint64_t& fromhost;
unsigned& mcause_max_irq;
};
template <typename BASE, typename LOGCAT = logging::disass> struct riscv_hart_common : public BASE, public mmio::memory_elem {
const std::array<const char, 4> lvl = {{'U', 'S', 'H', 'M'}};
const std::array<const char*, 16> trap_str = {{""
"Instruction address misaligned", // 0
"Instruction access fault", // 1
"Illegal instruction", // 2
"Breakpoint", // 3
"Load address misaligned", // 4
"Load access fault", // 5
"Store/AMO address misaligned", // 6
"Store/AMO access fault", // 7
"Environment call from U-mode", // 8
"Environment call from S-mode", // 9
"Reserved", // a
"Environment call from M-mode", // b
"Instruction page fault", // c
"Load page fault", // d
"Reserved", // e
"Store/AMO page fault"}};
const std::array<const char*, 12> irq_str = {{"User software interrupt", "Supervisor software interrupt", "Reserved",
"Machine software interrupt", "User timer interrupt", "Supervisor timer interrupt",
"Reserved", "Machine timer interrupt", "User external interrupt",
"Supervisor external interrupt", "Reserved", "Machine external interrupt"}};
constexpr static unsigned MEM = traits<BASE>::MEM;
using core = BASE;
using this_class = riscv_hart_common<BASE, LOGCAT>;
using phys_addr_t = typename core::phys_addr_t;
using reg_t = typename core::reg_t;
using addr_t = typename core::addr_t;
using rd_csr_f = std::function<iss::status(unsigned addr, reg_t&)>;
using wr_csr_f = std::function<iss::status(unsigned addr, reg_t)>;
#define MK_CSR_RD_CB(FCT) [this](unsigned a, reg_t& r) -> iss::status { return this->FCT(a, r); };
#define MK_CSR_WR_CB(FCT) [this](unsigned a, reg_t r) -> iss::status { return this->FCT(a, r); };
riscv_hart_common()
: state()
, instr_if(*this) {
// reset values
csr[misa] = traits<BASE>::MISA_VAL;
csr[mvendorid] = 0x669;
csr[marchid] = traits<BASE>::MARCHID_VAL;
csr[mimpid] = 1;
if(traits<BASE>::FLEN > 0) {
csr_rd_cb[fcsr] = MK_CSR_RD_CB(read_fcsr);
csr_wr_cb[fcsr] = MK_CSR_WR_CB(write_fcsr);
csr_rd_cb[fflags] = MK_CSR_RD_CB(read_fcsr);
csr_wr_cb[fflags] = MK_CSR_WR_CB(write_fcsr);
csr_rd_cb[frm] = MK_CSR_RD_CB(read_fcsr);
csr_wr_cb[frm] = MK_CSR_WR_CB(write_fcsr);
}
for(unsigned addr = mhpmcounter3; addr <= mhpmcounter31; ++addr) {
csr_rd_cb[addr] = MK_CSR_RD_CB(read_null);
csr_wr_cb[addr] = MK_CSR_WR_CB(write_plain);
}
if(traits<BASE>::XLEN == 32)
for(unsigned addr = mhpmcounter3h; addr <= mhpmcounter31h; ++addr) {
csr_rd_cb[addr] = MK_CSR_RD_CB(read_null);
csr_wr_cb[addr] = MK_CSR_WR_CB(write_plain);
}
for(unsigned addr = mhpmevent3; addr <= mhpmevent31; ++addr) {
csr_rd_cb[addr] = MK_CSR_RD_CB(read_null);
csr_wr_cb[addr] = MK_CSR_WR_CB(write_plain);
}
for(unsigned addr = hpmcounter3; addr <= hpmcounter31; ++addr) {
csr_rd_cb[addr] = MK_CSR_RD_CB(read_null);
}
if(traits<BASE>::XLEN == 32)
for(unsigned addr = hpmcounter3h; addr <= hpmcounter31h; ++addr) {
csr_rd_cb[addr] = MK_CSR_RD_CB(read_null);
}
// common regs
const std::array<unsigned, 4> roaddrs{{misa, mvendorid, marchid, mimpid}};
for(auto addr : roaddrs) {
csr_rd_cb[addr] = MK_CSR_RD_CB(read_plain);
csr_wr_cb[addr] = MK_CSR_WR_CB(write_null);
}
// special handling & overrides
csr_rd_cb[time] = MK_CSR_RD_CB(read_time);
if(traits<BASE>::XLEN == 32)
csr_rd_cb[timeh] = MK_CSR_RD_CB(read_time);
csr_rd_cb[cycle] = MK_CSR_RD_CB(read_cycle);
if(traits<BASE>::XLEN == 32)
csr_rd_cb[cycleh] = MK_CSR_RD_CB(read_cycle);
csr_rd_cb[instret] = MK_CSR_RD_CB(read_instret);
if(traits<BASE>::XLEN == 32)
csr_rd_cb[instreth] = MK_CSR_RD_CB(read_instret);
csr_rd_cb[mcycle] = MK_CSR_RD_CB(read_cycle);
csr_wr_cb[mcycle] = MK_CSR_WR_CB(write_cycle);
if(traits<BASE>::XLEN == 32)
csr_rd_cb[mcycleh] = MK_CSR_RD_CB(read_cycle);
if(traits<BASE>::XLEN == 32)
csr_wr_cb[mcycleh] = MK_CSR_WR_CB(write_cycle);
csr_rd_cb[minstret] = MK_CSR_RD_CB(read_instret);
csr_wr_cb[minstret] = MK_CSR_WR_CB(write_instret);
if(traits<BASE>::XLEN == 32)
csr_rd_cb[minstreth] = MK_CSR_RD_CB(read_instret);
if(traits<BASE>::XLEN == 32)
csr_wr_cb[minstreth] = MK_CSR_WR_CB(write_instret);
csr_rd_cb[mhartid] = MK_CSR_RD_CB(read_hartid);
};
~riscv_hart_common() {
if(io_buf.str().length()) {
CPPLOG(INFO) << "tohost send '" << io_buf.str() << "'";
}
};
}
std::unordered_map<std::string, uint64_t> symbol_table;
uint64_t entry_address{0};
uint64_t tohost = std::numeric_limits<uint64_t>::max();
uint64_t fromhost = std::numeric_limits<uint64_t>::max();
std::stringstream io_buf;
bool read_elf_file(std::string name, uint8_t expected_elf_class,
std::function<iss::status(uint64_t, uint64_t, const uint8_t* const)> cb) {
void set_semihosting_callback(semihosting_cb_t<reg_t> cb) { semihosting_cb = cb; };
std::pair<uint64_t, bool> load_file(std::string name, int type) {
return std::make_pair(entry_address, read_elf_file(name, sizeof(reg_t) == 4 ? ELFIO::ELFCLASS32 : ELFIO::ELFCLASS64));
}
bool read_elf_file(std::string name, uint8_t expected_elf_class) {
// Create elfio reader
ELFIO::elfio reader;
// Load ELF data
@@ -344,7 +430,8 @@ struct riscv_hart_common {
const auto seg_data = pseg->get_data();
const auto type = pseg->get_type();
if(type == ELFIO::PT_LOAD && fsize > 0) {
auto res = cb(pseg->get_physical_address(), fsize, reinterpret_cast<const uint8_t* const>(seg_data));
auto res = this->write(iss::address_type::PHYSICAL, iss::access_type::DEBUG_WRITE, traits<BASE>::MEM,
pseg->get_physical_address(), fsize, reinterpret_cast<const uint8_t* const>(seg_data));
if(res != iss::Ok)
CPPLOG(ERR) << "problem writing " << fsize << "bytes to 0x" << std::hex << pseg->get_physical_address();
}
@@ -382,6 +469,7 @@ struct riscv_hart_common {
}
return false;
};
iss::status execute_sys_write(arch_if* aif, const std::array<uint64_t, 8>& loaded_payload, unsigned mem_type) {
uint64_t fd = loaded_payload[1];
uint64_t buf_ptr = loaded_payload[2];
@@ -409,6 +497,357 @@ struct riscv_hart_common {
}
return iss::Ok;
}
constexpr bool has_compressed() { return traits<BASE>::MISA_VAL & 0b0100; }
constexpr reg_t get_pc_mask() { return has_compressed() ? (reg_t)~1 : (reg_t)~3; }
void disass_output(uint64_t pc, const std::string instr) override {
// NSCLOG(INFO, LOGCAT) << fmt::format("0x{:016x} {:40} [p:{};s:0x{:x};c:{}]", pc, instr, lvl[this->reg.PRIV],
// (reg_t)state.mstatus,
// this->reg.cycle + cycle_offset);
NSCLOG(INFO, LOGCAT) << fmt::format("0x{:016x} {:40} [p:{};c:{}]", pc, instr, lvl[this->reg.PRIV],
this->reg.cycle + cycle_offset);
};
void register_csr(unsigned addr, rd_csr_f f) { csr_rd_cb[addr] = f; }
void register_csr(unsigned addr, wr_csr_f f) { csr_wr_cb[addr] = f; }
void register_csr(unsigned addr, rd_csr_f rdf, wr_csr_f wrf) {
csr_rd_cb[addr] = rdf;
csr_wr_cb[addr] = wrf;
}
void unregister_csr_rd(unsigned addr) { csr_rd_cb.erase(addr); }
void unregister_csr_wr(unsigned addr) { csr_wr_cb.erase(addr); }
bool debug_mode_active() { return this->reg.PRIV & 0x4; }
const reg_t& get_mhartid() const { return mhartid_reg; }
void set_mhartid(reg_t mhartid) { mhartid_reg = mhartid; };
iss::status read_csr(unsigned addr, reg_t& val) {
if(addr >= csr.size())
return iss::Err;
auto req_priv_lvl = (addr >> 8) & 0x3;
if(this->reg.PRIV < req_priv_lvl) // not having required privileges
throw illegal_instruction_fault(this->fault_data);
auto it = csr_rd_cb.find(addr);
if(it == csr_rd_cb.end() || !it->second) // non existent register
throw illegal_instruction_fault(this->fault_data);
return it->second(addr, val);
}
iss::status write_csr(unsigned addr, reg_t val) {
if(addr >= csr.size())
return iss::Err;
auto req_priv_lvl = (addr >> 8) & 0x3;
if(this->reg.PRIV < req_priv_lvl) // not having required privileges
throw illegal_instruction_fault(this->fault_data);
if((addr & 0xc00) == 0xc00) // writing to read-only region
throw illegal_instruction_fault(this->fault_data);
auto it = csr_wr_cb.find(addr);
if(it == csr_wr_cb.end() || !it->second) // non existent register
throw illegal_instruction_fault(this->fault_data);
return it->second(addr, val);
}
iss::status read_null(unsigned addr, reg_t& val) {
val = 0;
return iss::Ok;
}
iss::status write_null(unsigned addr, reg_t val) { return iss::status::Ok; }
iss::status read_plain(unsigned addr, reg_t& val) {
val = csr[addr];
return iss::Ok;
}
iss::status write_plain(unsigned addr, reg_t val) {
csr[addr] = val;
return iss::Ok;
}
iss::status read_cycle(unsigned addr, reg_t& val) {
auto cycle_val = this->reg.cycle + cycle_offset;
if(addr == mcycle) {
val = static_cast<reg_t>(cycle_val);
} else if(addr == mcycleh) {
val = static_cast<reg_t>(cycle_val >> 32);
}
return iss::Ok;
}
iss::status write_cycle(unsigned addr, reg_t val) {
if(sizeof(typename traits<BASE>::reg_t) != 4) {
mcycle_csr = static_cast<uint64_t>(val);
} else {
if(addr == mcycle) {
mcycle_csr = (mcycle_csr & 0xffffffff00000000) + val;
} else {
mcycle_csr = (static_cast<uint64_t>(val) << 32) + (mcycle_csr & 0xffffffff);
}
}
cycle_offset = mcycle_csr - this->reg.cycle; // TODO: relying on wrap-around
return iss::Ok;
}
iss::status read_instret(unsigned addr, reg_t& val) {
if((addr & 0xff) == (minstret & 0xff)) {
val = static_cast<reg_t>(this->reg.instret);
} else if((addr & 0xff) == (minstreth & 0xff)) {
val = static_cast<reg_t>(this->reg.instret >> 32);
}
return iss::Ok;
}
iss::status write_instret(unsigned addr, reg_t val) {
if(sizeof(typename traits<BASE>::reg_t) != 4) {
this->reg.instret = static_cast<uint64_t>(val);
} else {
if((addr & 0xff) == (minstret & 0xff)) {
this->reg.instret = (this->reg.instret & 0xffffffff00000000) + val;
} else {
this->reg.instret = (static_cast<uint64_t>(val) << 32) + (this->reg.instret & 0xffffffff);
}
}
this->reg.instret--;
return iss::Ok;
}
iss::status read_time(unsigned addr, reg_t& val) {
uint64_t time_val = this->reg.cycle / (100000000 / 32768 - 1); //-> ~3052;
if(addr == time) {
val = static_cast<reg_t>(time_val);
} else if(addr == timeh) {
if(sizeof(typename traits<BASE>::reg_t) != 4)
return iss::Err;
val = static_cast<reg_t>(time_val >> 32);
}
return iss::Ok;
}
iss::status read_tvec(unsigned addr, reg_t& val) {
val = csr[addr] & ~2;
return iss::Ok;
}
iss::status read_hartid(unsigned addr, reg_t& val) {
val = mhartid_reg;
return iss::Ok;
}
iss::status write_epc(unsigned addr, reg_t val) {
csr[addr] = val & get_pc_mask();
return iss::Ok;
}
iss::status write_dcsr(unsigned addr, reg_t val) {
if(!debug_mode_active())
throw illegal_instruction_fault(this->fault_data);
// +-------------- ebreakm
// | +---------- stepi
// | | +++----- cause
// | | ||| +- step
csr[addr] = val & 0b1000100111000100U;
return iss::Ok;
}
iss::status read_debug(unsigned addr, reg_t& val) {
if(!debug_mode_active())
throw illegal_instruction_fault(this->fault_data);
val = csr[addr];
return iss::Ok;
}
iss::status write_dscratch(unsigned addr, reg_t val) {
if(!debug_mode_active())
throw illegal_instruction_fault(this->fault_data);
csr[addr] = val;
return iss::Ok;
}
iss::status read_dpc(unsigned addr, reg_t& val) {
if(!debug_mode_active())
throw illegal_instruction_fault(this->fault_data);
val = this->reg.DPC;
return iss::Ok;
}
iss::status write_dpc(unsigned addr, reg_t val) {
if(!debug_mode_active())
throw illegal_instruction_fault(this->fault_data);
this->reg.DPC = val;
return iss::Ok;
}
iss::status read_fcsr(unsigned addr, reg_t& val) {
switch(addr) {
case 1: // fflags, 4:0
val = bit_sub<0, 5>(this->get_fcsr());
break;
case 2: // frm, 7:5
val = bit_sub<5, 3>(this->get_fcsr());
break;
case 3: // fcsr
val = this->get_fcsr();
break;
default:
return iss::Err;
}
return iss::Ok;
}
iss::status write_fcsr(unsigned addr, reg_t val) {
switch(addr) {
case 1: // fflags, 4:0
this->set_fcsr((this->get_fcsr() & 0xffffffe0) | (val & 0x1f));
break;
case 2: // frm, 7:5
this->set_fcsr((this->get_fcsr() & 0xffffff1f) | ((val & 0x7) << 5));
break;
case 3: // fcsr
this->set_fcsr(val & 0xff);
break;
default:
return iss::Err;
}
return iss::Ok;
}
priv_if<reg_t> get_priv_if() {
return priv_if<reg_t>{.read_csr = [this](unsigned addr, reg_t& val) -> iss::status { return read_csr(addr, val); },
.write_csr = [this](unsigned addr, reg_t val) -> iss::status { return write_csr(addr, val); },
.exec_htif = [this](uint8_t const* data) -> iss::status { return execute_htif(data); },
.csr_rd_cb{this->csr_rd_cb},
.csr_wr_cb{csr_wr_cb},
.mstatus{this->state},
.tohost{this->tohost},
.fromhost{this->fromhost},
.mcause_max_irq{mcause_max_irq}};
}
iss::status execute_htif(uint8_t const* data) {
reg_t cur_data = *reinterpret_cast<const reg_t*>(data);
// Extract Device (bits 63:56)
uint8_t device = traits<BASE>::XLEN == 32 ? 0 : (cur_data >> 56) & 0xFF;
// Extract Command (bits 55:48)
uint8_t command = traits<BASE>::XLEN == 32 ? 0 : (cur_data >> 48) & 0xFF;
// Extract payload (bits 47:0)
uint64_t payload_addr = cur_data & 0xFFFFFFFFFFFFULL;
if(payload_addr & 1) {
CPPLOG(FATAL) << "this->tohost value is 0x" << std::hex << payload_addr << std::dec << " (" << payload_addr
<< "), stopping simulation";
this->reg.trap_state = std::numeric_limits<uint32_t>::max();
this->interrupt_sim = payload_addr;
return iss::Ok;
} else if(device == 0 && command == 0) {
std::array<uint64_t, 8> loaded_payload;
if(memory.rd_mem(access_type::DEBUG_READ, payload_addr, 8 * sizeof(uint64_t),
reinterpret_cast<uint8_t*>(loaded_payload.data())) == iss::Err)
CPPLOG(ERR) << "Syscall read went wrong";
uint64_t syscall_num = loaded_payload.at(0);
if(syscall_num == 64) { // SYS_WRITE
return this->execute_sys_write(this, loaded_payload, traits<BASE>::MEM);
} else {
CPPLOG(ERR) << "this->tohost syscall with number 0x" << std::hex << syscall_num << std::dec << " (" << syscall_num
<< ") not implemented";
this->reg.trap_state = std::numeric_limits<uint32_t>::max();
this->interrupt_sim = payload_addr;
return iss::Ok;
}
} else {
CPPLOG(ERR) << "this->tohost functionality not implemented for device " << device << " and command " << command;
this->reg.trap_state = std::numeric_limits<uint32_t>::max();
this->interrupt_sim = payload_addr;
return iss::Ok;
}
}
mmio::memory_hierarchy memories;
virtual mmio::memory_if get_mem_if() override {
assert(false || "This function should nevver be called");
return mmio::memory_if{};
}
virtual void set_next(mmio::memory_if mem_if) { memory = mem_if; };
void set_irq_num(unsigned i) { mcause_max_irq = 1 << util::ilog2(i); }
protected:
hart_state<reg_t> state;
static constexpr reg_t get_mstatus_mask_t(unsigned priv_lvl = PRIV_M) {
if(sizeof(reg_t) == 4) {
return priv_lvl == PRIV_U ? 0x80000011UL : // 0b1...0 0001 0001
priv_lvl == PRIV_S ? 0x800de133UL // 0b0...0 0001 1000 1001 1001;
: 0x807ff9ddUL;
} else {
return priv_lvl == PRIV_U ? 0x011ULL : // 0b1...0 0001 0001
priv_lvl == PRIV_S ? 0x000de133ULL
: 0x007ff9ddULL;
}
}
mmio::memory_if memory;
struct riscv_instrumentation_if : public iss::instrumentation_if {
riscv_instrumentation_if(riscv_hart_common<BASE, LOGCAT>& arch)
: arch(arch) {}
/**
* get the name of this architecture
*
* @return the name of this architecture
*/
const std::string core_type_name() const override { return traits<BASE>::core_type; }
uint64_t get_pc() override { return arch.reg.PC; }
uint64_t get_next_pc() override { return arch.reg.NEXT_PC; }
uint64_t get_instr_word() override { return arch.reg.instruction; }
uint64_t get_instr_count() override { return arch.reg.icount; }
uint64_t get_pendig_traps() override { return arch.reg.trap_state; }
uint64_t get_total_cycles() override { return arch.reg.cycle + arch.cycle_offset; }
void update_last_instr_cycles(unsigned cycles) override { arch.cycle_offset += cycles - 1; }
bool is_branch_taken() override { return arch.reg.last_branch; }
unsigned get_reg_num() override { return traits<BASE>::NUM_REGS; }
unsigned get_reg_size(unsigned num) override { return traits<BASE>::reg_bit_widths[num]; }
std::unordered_map<std::string, uint64_t> const& get_symbol_table(std::string name) override { return arch.symbol_table; }
riscv_hart_common<BASE, LOGCAT>& arch;
};
friend struct riscv_instrumentation_if;
riscv_instrumentation_if instr_if;
instrumentation_if* get_instrumentation_if() override { return &instr_if; };
using csr_type = util::sparse_array<typename traits<BASE>::reg_t, 1ULL << 12, 12>;
using csr_page_type = typename csr_type::page_type;
csr_type csr;
std::unordered_map<unsigned, rd_csr_f> csr_rd_cb;
std::unordered_map<unsigned, wr_csr_f> csr_wr_cb;
reg_t mhartid_reg{0x0};
uint64_t mcycle_csr{0};
uint64_t minstret_csr{0};
reg_t fault_data;
int64_t cycle_offset{0};
int64_t instret_offset{0};
semihosting_cb_t<reg_t> semihosting_cb;
std::array<vm_info, 2> vm;
unsigned mcause_max_irq{16U};
};
} // namespace arch