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Adapted namespace changes in sc-components

This commit is contained in:
Eyck Jentzsch 2017-10-04 14:30:25 +02:00
parent 4867cca187
commit ccc3f5d47d
29 changed files with 184 additions and 178 deletions
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2
.cproject
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@ -76,7 +76,7 @@
</toolChain>
</folderInfo>
<sourceEntries>
<entry excluding="riscv/src-gen|sysc|blink.S|flash.s" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
<entry excluding="riscv/src-gen|blink.S|scc|flash.s" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
</sourceEntries>
</configuration>
</storageModule>

4
riscv.sc/incl/sysc/SiFive/aon.h
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@ -17,13 +17,13 @@
#ifndef _AON_H_
#define _AON_H_
#include <sysc/tlm_target.h>
#include "scc/tlm_target.h"
namespace sysc {
class aon_regs;
class aon : public sc_core::sc_module, public tlm_target<> {
class aon : public sc_core::sc_module, public scc::tlm_target<> {
public:
SC_HAS_PROCESS(aon);
sc_core::sc_in<sc_core::sc_time> clk_i;

4
riscv.sc/incl/sysc/SiFive/clint.h
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@ -17,7 +17,7 @@
#ifndef _CLINT_H_
#define _CLINT_H_
#include <sysc/tlm_target.h>
#include "scc/tlm_target.h"
namespace iss {
namespace arch {
@ -32,7 +32,7 @@ namespace SiFive {
class core_complex;
}
class clint : public sc_core::sc_module, public tlm_target<> {
class clint : public sc_core::sc_module, public scc::tlm_target<> {
public:
SC_HAS_PROCESS(clint);
sc_core::sc_in<sc_core::sc_time> clk_i;

22
riscv.sc/incl/sysc/SiFive/core_complex.h
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@ -37,13 +37,13 @@
#ifndef _SYSC_SIFIVE_FE310_H_
#define _SYSC_SIFIVE_FE310_H_
#include <sysc/ext_attribute.h>
#include <sysc/initiator_mixin.h>
#include <sysc/traceable.h>
#include <sysc/utilities.h>
#include <tlm>
#include <tlm_utils/tlm_quantumkeeper.h>
#include <util/range_lut.h>
#include "scc/ext_attribute.h"
#include "scc/initiator_mixin.h"
#include "scc/traceable.h"
#include "scc/utilities.h"
namespace iss {
class vm_if;
@ -67,25 +67,25 @@ public:
namespace SiFive {
class core_wrapper;
class core_complex : public sc_core::sc_module, public sysc::traceable {
class core_complex : public sc_core::sc_module, public scc::traceable {
public:
SC_HAS_PROCESS(core_complex);
sysc::initiator_mixin<tlm::tlm_initiator_socket<32>> initiator;
scc::initiator_mixin<tlm::tlm_initiator_socket<32>> initiator;
sc_core::sc_in<sc_core::sc_time> clk_i;
sc_core::sc_in<bool> rst_i;
sysc::ext_attribute<std::string> elf_file;
scc::ext_attribute<std::string> elf_file;
sysc::ext_attribute<bool> enable_disass;
scc::ext_attribute<bool> enable_disass;
sysc::ext_attribute<uint64_t> reset_address;
scc::ext_attribute<uint64_t> reset_address;
sysc::ext_attribute<unsigned short> gdb_server_port;
scc::ext_attribute<unsigned short> gdb_server_port;
sysc::ext_attribute<bool> dump_ir;
scc::ext_attribute<bool> dump_ir;
core_complex(sc_core::sc_module_name name);

50
riscv.sc/incl/sysc/SiFive/gen/aon_regs.h
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@ -36,14 +36,14 @@
#ifndef _AON_REGS_H_
#define _AON_REGS_H_
#include <sysc/register.h>
#include <sysc/tlm_target.h>
#include <sysc/utilities.h>
#include <util/bit_field.h>
#include "scc/register.h"
#include "scc/tlm_target.h"
#include "scc/utilities.h"
namespace sysc {
class aon_regs : public sc_core::sc_module, public sysc::resetable {
class aon_regs : public sc_core::sc_module, public scc::resetable {
public:
// storage declarations
uint32_t r_wdogcfg;
@ -97,29 +97,29 @@ public:
uint32_t r_pmukey;
// register declarations
sysc::sc_register<uint32_t> wdogcfg;
sysc::sc_register<uint32_t> wdogcount;
sysc::sc_register<uint32_t> wdogs;
sysc::sc_register<uint32_t> wdogfeed;
sysc::sc_register<uint32_t> wdogkey;
sysc::sc_register<uint32_t> wdogcmp;
sysc::sc_register<uint32_t> rtccfg;
sysc::sc_register<uint32_t> rtclo;
sysc::sc_register<uint32_t> rtchi;
sysc::sc_register<uint32_t> rtcs;
sysc::sc_register<uint32_t> rtccmp;
sysc::sc_register<uint32_t> lfrosccfg;
sysc::sc_register_indexed<uint32_t, 32> backup;
sysc::sc_register_indexed<pmuwakeupi_t, 8> pmuwakeupi;
sysc::sc_register_indexed<pmusleepi_t, 8> pmusleepi;
sysc::sc_register<uint32_t> pmuie;
sysc::sc_register<uint32_t> pmucause;
sysc::sc_register<uint32_t> pmusleep;
sysc::sc_register<uint32_t> pmukey;
scc::sc_register<uint32_t> wdogcfg;
scc::sc_register<uint32_t> wdogcount;
scc::sc_register<uint32_t> wdogs;
scc::sc_register<uint32_t> wdogfeed;
scc::sc_register<uint32_t> wdogkey;
scc::sc_register<uint32_t> wdogcmp;
scc::sc_register<uint32_t> rtccfg;
scc::sc_register<uint32_t> rtclo;
scc::sc_register<uint32_t> rtchi;
scc::sc_register<uint32_t> rtcs;
scc::sc_register<uint32_t> rtccmp;
scc::sc_register<uint32_t> lfrosccfg;
scc::sc_register_indexed<uint32_t, 32> backup;
scc::sc_register_indexed<pmuwakeupi_t, 8> pmuwakeupi;
scc::sc_register_indexed<pmusleepi_t, 8> pmusleepi;
scc::sc_register<uint32_t> pmuie;
scc::sc_register<uint32_t> pmucause;
scc::sc_register<uint32_t> pmusleep;
scc::sc_register<uint32_t> pmukey;
aon_regs(sc_core::sc_module_name nm);
template <unsigned BUSWIDTH = 32> void registerResources(sysc::tlm_target<BUSWIDTH> &target);
template <unsigned BUSWIDTH = 32> void registerResources(scc::tlm_target<BUSWIDTH> &target);
};
}
//////////////////////////////////////////////////////////////////////////////
@ -148,7 +148,7 @@ inline sysc::aon_regs::aon_regs(sc_core::sc_module_name nm)
, NAMED(pmusleep, r_pmusleep, 0, *this)
, NAMED(pmukey, r_pmukey, 0, *this) {}
template <unsigned BUSWIDTH> inline void sysc::aon_regs::registerResources(sysc::tlm_target<BUSWIDTH> &target) {
template <unsigned BUSWIDTH> inline void sysc::aon_regs::registerResources(scc::tlm_target<BUSWIDTH> &target) {
target.addResource(wdogcfg, 0x0UL);
target.addResource(wdogcount, 0x8UL);
target.addResource(wdogs, 0x10UL);

18
riscv.sc/incl/sysc/SiFive/gen/clint_regs.h
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@ -36,14 +36,14 @@
#ifndef _CLINT_REGS_H_
#define _CLINT_REGS_H_
#include <sysc/register.h>
#include <sysc/tlm_target.h>
#include <sysc/utilities.h>
#include <util/bit_field.h>
#include "scc/register.h"
#include "scc/tlm_target.h"
#include "scc/utilities.h"
namespace sysc {
class clint_regs : public sc_core::sc_module, public sysc::resetable {
class clint_regs : public sc_core::sc_module, public scc::resetable {
public:
// storage declarations
BEGIN_BF_DECL(msip_t, uint32_t);
@ -55,13 +55,13 @@ public:
uint64_t r_mtime;
// register declarations
sysc::sc_register<msip_t> msip;
sysc::sc_register<uint64_t> mtimecmp;
sysc::sc_register<uint64_t> mtime;
scc::sc_register<msip_t> msip;
scc::sc_register<uint64_t> mtimecmp;
scc::sc_register<uint64_t> mtime;
clint_regs(sc_core::sc_module_name nm);
template <unsigned BUSWIDTH = 32> void registerResources(sysc::tlm_target<BUSWIDTH> &target);
template <unsigned BUSWIDTH = 32> void registerResources(scc::tlm_target<BUSWIDTH> &target);
};
}
//////////////////////////////////////////////////////////////////////////////
@ -74,7 +74,7 @@ inline sysc::clint_regs::clint_regs(sc_core::sc_module_name nm)
, NAMED(mtimecmp, r_mtimecmp, 0, *this)
, NAMED(mtime, r_mtime, 0, *this) {}
template <unsigned BUSWIDTH> inline void sysc::clint_regs::registerResources(sysc::tlm_target<BUSWIDTH> &target) {
template <unsigned BUSWIDTH> inline void sysc::clint_regs::registerResources(scc::tlm_target<BUSWIDTH> &target) {
target.addResource(msip, 0x0UL);
target.addResource(mtimecmp, 0x4000UL);
target.addResource(mtime, 0xbff8UL);

2
riscv.sc/incl/sysc/SiFive/gen/e300_plat_t.h
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@ -2,7 +2,7 @@
#define _E300_PLAT_MAP_H_
// need double braces, see
// https://stackoverflow.com/questions/6893700/how-to-construct-stdarray-object-with-initializer-list#6894191
const std::array<sysc::target_memory_map_entry<32>, 8> e300_plat_map = {{
const std::array<scc::target_memory_map_entry<32>, 8> e300_plat_map = {{
{&i_clint, 0x2000000, 0xc000},
{&i_plic, 0xc000000, 0x200008},
{&i_aon, 0x10000000, 0x150},

46
riscv.sc/incl/sysc/SiFive/gen/gpio_regs.h
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@ -36,14 +36,14 @@
#ifndef _GPIO_REGS_H_
#define _GPIO_REGS_H_
#include <sysc/register.h>
#include <sysc/tlm_target.h>
#include <sysc/utilities.h>
#include <util/bit_field.h>
#include "scc/register.h"
#include "scc/tlm_target.h"
#include "scc/utilities.h"
namespace sysc {
class gpio_regs : public sc_core::sc_module, public sysc::resetable {
class gpio_regs : public sc_core::sc_module, public scc::resetable {
public:
// storage declarations
uint32_t r_value;
@ -81,27 +81,27 @@ public:
uint32_t r_out_xor;
// register declarations
sysc::sc_register<uint32_t> value;
sysc::sc_register<uint32_t> input_en;
sysc::sc_register<uint32_t> output_en;
sysc::sc_register<uint32_t> port;
sysc::sc_register<uint32_t> pue;
sysc::sc_register<uint32_t> ds;
sysc::sc_register<uint32_t> rise_ie;
sysc::sc_register<uint32_t> rise_ip;
sysc::sc_register<uint32_t> fall_ie;
sysc::sc_register<uint32_t> fall_ip;
sysc::sc_register<uint32_t> high_ie;
sysc::sc_register<uint32_t> high_ip;
sysc::sc_register<uint32_t> low_ie;
sysc::sc_register<uint32_t> low_ip;
sysc::sc_register<uint32_t> iof_en;
sysc::sc_register<uint32_t> iof_sel;
sysc::sc_register<uint32_t> out_xor;
scc::sc_register<uint32_t> value;
scc::sc_register<uint32_t> input_en;
scc::sc_register<uint32_t> output_en;
scc::sc_register<uint32_t> port;
scc::sc_register<uint32_t> pue;
scc::sc_register<uint32_t> ds;
scc::sc_register<uint32_t> rise_ie;
scc::sc_register<uint32_t> rise_ip;
scc::sc_register<uint32_t> fall_ie;
scc::sc_register<uint32_t> fall_ip;
scc::sc_register<uint32_t> high_ie;
scc::sc_register<uint32_t> high_ip;
scc::sc_register<uint32_t> low_ie;
scc::sc_register<uint32_t> low_ip;
scc::sc_register<uint32_t> iof_en;
scc::sc_register<uint32_t> iof_sel;
scc::sc_register<uint32_t> out_xor;
gpio_regs(sc_core::sc_module_name nm);
template <unsigned BUSWIDTH = 32> void registerResources(sysc::tlm_target<BUSWIDTH> &target);
template <unsigned BUSWIDTH = 32> void registerResources(scc::tlm_target<BUSWIDTH> &target);
};
}
//////////////////////////////////////////////////////////////////////////////
@ -128,7 +128,7 @@ inline sysc::gpio_regs::gpio_regs(sc_core::sc_module_name nm)
, NAMED(iof_sel, r_iof_sel, 0, *this)
, NAMED(out_xor, r_out_xor, 0, *this) {}
template <unsigned BUSWIDTH> inline void sysc::gpio_regs::registerResources(sysc::tlm_target<BUSWIDTH> &target) {
template <unsigned BUSWIDTH> inline void sysc::gpio_regs::registerResources(scc::tlm_target<BUSWIDTH> &target) {
target.addResource(value, 0x0UL);
target.addResource(input_en, 0x4UL);
target.addResource(output_en, 0x8UL);

22
riscv.sc/incl/sysc/SiFive/gen/plic_regs.h
View File

@ -36,14 +36,14 @@
#ifndef _PLIC_REGS_H_
#define _PLIC_REGS_H_
#include <sysc/register.h>
#include <sysc/tlm_target.h>
#include <sysc/utilities.h>
#include <util/bit_field.h>
#include "scc/register.h"
#include "scc/tlm_target.h"
#include "scc/utilities.h"
namespace sysc {
class plic_regs : public sc_core::sc_module, public sysc::resetable {
class plic_regs : public sc_core::sc_module, public scc::resetable {
public:
// storage declarations
BEGIN_BF_DECL(priority_t, uint32_t);
@ -62,15 +62,15 @@ public:
uint32_t r_claim_complete;
// register declarations
sysc::sc_register_indexed<priority_t, 255> priority;
sysc::sc_register<uint32_t> pending;
sysc::sc_register<uint32_t> enabled;
sysc::sc_register<threshold_t> threshold;
sysc::sc_register<uint32_t> claim_complete;
scc::sc_register_indexed<priority_t, 255> priority;
scc::sc_register<uint32_t> pending;
scc::sc_register<uint32_t> enabled;
scc::sc_register<threshold_t> threshold;
scc::sc_register<uint32_t> claim_complete;
plic_regs(sc_core::sc_module_name nm);
template <unsigned BUSWIDTH = 32> void registerResources(sysc::tlm_target<BUSWIDTH> &target);
template <unsigned BUSWIDTH = 32> void registerResources(scc::tlm_target<BUSWIDTH> &target);
};
}
//////////////////////////////////////////////////////////////////////////////
@ -85,7 +85,7 @@ inline sysc::plic_regs::plic_regs(sc_core::sc_module_name nm)
, NAMED(threshold, r_threshold, 0, *this)
, NAMED(claim_complete, r_claim_complete, 0, *this) {}
template <unsigned BUSWIDTH> inline void sysc::plic_regs::registerResources(sysc::tlm_target<BUSWIDTH> &target) {
template <unsigned BUSWIDTH> inline void sysc::plic_regs::registerResources(scc::tlm_target<BUSWIDTH> &target) {
target.addResource(priority, 0x4UL);
target.addResource(pending, 0x1000UL);
target.addResource(enabled, 0x2000UL);

22
riscv.sc/incl/sysc/SiFive/gen/prci_regs.h
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@ -36,14 +36,14 @@
#ifndef _PRCI_REGS_H_
#define _PRCI_REGS_H_
#include <sysc/register.h>
#include <sysc/tlm_target.h>
#include <sysc/utilities.h>
#include <util/bit_field.h>
#include "scc/register.h"
#include "scc/tlm_target.h"
#include "scc/utilities.h"
namespace sysc {
class prci_regs : public sc_core::sc_module, public sysc::resetable {
class prci_regs : public sc_core::sc_module, public scc::resetable {
public:
// storage declarations
BEGIN_BF_DECL(hfrosccfg_t, uint32_t);
@ -73,15 +73,15 @@ public:
uint32_t r_coreclkcfg;
// register declarations
sysc::sc_register<hfrosccfg_t> hfrosccfg;
sysc::sc_register<hfxosccfg_t> hfxosccfg;
sysc::sc_register<pllcfg_t> pllcfg;
sysc::sc_register<uint32_t> plloutdiv;
sysc::sc_register<uint32_t> coreclkcfg;
scc::sc_register<hfrosccfg_t> hfrosccfg;
scc::sc_register<hfxosccfg_t> hfxosccfg;
scc::sc_register<pllcfg_t> pllcfg;
scc::sc_register<uint32_t> plloutdiv;
scc::sc_register<uint32_t> coreclkcfg;
prci_regs(sc_core::sc_module_name nm);
template <unsigned BUSWIDTH = 32> void registerResources(sysc::tlm_target<BUSWIDTH> &target);
template <unsigned BUSWIDTH = 32> void registerResources(scc::tlm_target<BUSWIDTH> &target);
};
}
//////////////////////////////////////////////////////////////////////////////
@ -96,7 +96,7 @@ inline sysc::prci_regs::prci_regs(sc_core::sc_module_name nm)
, NAMED(plloutdiv, r_plloutdiv, 0, *this)
, NAMED(coreclkcfg, r_coreclkcfg, 0, *this) {}
template <unsigned BUSWIDTH> inline void sysc::prci_regs::registerResources(sysc::tlm_target<BUSWIDTH> &target) {
template <unsigned BUSWIDTH> inline void sysc::prci_regs::registerResources(scc::tlm_target<BUSWIDTH> &target) {
target.addResource(hfrosccfg, 0x0UL);
target.addResource(hfxosccfg, 0x4UL);
target.addResource(pllcfg, 0x8UL);

44
riscv.sc/incl/sysc/SiFive/gen/spi_regs.h
View File

@ -36,14 +36,14 @@
#ifndef _SPI_REGS_H_
#define _SPI_REGS_H_
#include <sysc/register.h>
#include <sysc/tlm_target.h>
#include <sysc/utilities.h>
#include <util/bit_field.h>
#include "scc/register.h"
#include "scc/tlm_target.h"
#include "scc/utilities.h"
namespace sysc {
class spi_regs : public sc_core::sc_module, public sysc::resetable {
class spi_regs : public sc_core::sc_module, public scc::resetable {
public:
// storage declarations
BEGIN_BF_DECL(sckdiv_t, uint32_t);
@ -124,26 +124,26 @@ public:
END_BF_DECL() r_ip;
// register declarations
sysc::sc_register<sckdiv_t> sckdiv;
sysc::sc_register<sckmode_t> sckmode;
sysc::sc_register<uint32_t> csid;
sysc::sc_register<uint32_t> csdef;
sysc::sc_register<csmode_t> csmode;
sysc::sc_register<delay0_t> delay0;
sysc::sc_register<delay1_t> delay1;
sysc::sc_register<fmt_t> fmt;
sysc::sc_register<txdata_t> txdata;
sysc::sc_register<rxdata_t> rxdata;
sysc::sc_register<txmark_t> txmark;
sysc::sc_register<rxmark_t> rxmark;
sysc::sc_register<fctrl_t> fctrl;
sysc::sc_register<ffmt_t> ffmt;
sysc::sc_register<ie_t> ie;
sysc::sc_register<ip_t> ip;
scc::sc_register<sckdiv_t> sckdiv;
scc::sc_register<sckmode_t> sckmode;
scc::sc_register<uint32_t> csid;
scc::sc_register<uint32_t> csdef;
scc::sc_register<csmode_t> csmode;
scc::sc_register<delay0_t> delay0;
scc::sc_register<delay1_t> delay1;
scc::sc_register<fmt_t> fmt;
scc::sc_register<txdata_t> txdata;
scc::sc_register<rxdata_t> rxdata;
scc::sc_register<txmark_t> txmark;
scc::sc_register<rxmark_t> rxmark;
scc::sc_register<fctrl_t> fctrl;
scc::sc_register<ffmt_t> ffmt;
scc::sc_register<ie_t> ie;
scc::sc_register<ip_t> ip;
spi_regs(sc_core::sc_module_name nm);
template <unsigned BUSWIDTH = 32> void registerResources(sysc::tlm_target<BUSWIDTH> &target);
template <unsigned BUSWIDTH = 32> void registerResources(scc::tlm_target<BUSWIDTH> &target);
};
}
//////////////////////////////////////////////////////////////////////////////
@ -169,7 +169,7 @@ inline sysc::spi_regs::spi_regs(sc_core::sc_module_name nm)
, NAMED(ie, r_ie, 0, *this)
, NAMED(ip, r_ip, 0, *this) {}
template <unsigned BUSWIDTH> inline void sysc::spi_regs::registerResources(sysc::tlm_target<BUSWIDTH> &target) {
template <unsigned BUSWIDTH> inline void sysc::spi_regs::registerResources(scc::tlm_target<BUSWIDTH> &target) {
target.addResource(sckdiv, 0x0UL);
target.addResource(sckmode, 0x4UL);
target.addResource(csid, 0x10UL);

26
riscv.sc/incl/sysc/SiFive/gen/uart_regs.h
View File

@ -36,14 +36,14 @@
#ifndef _UART_REGS_H_
#define _UART_REGS_H_
#include <sysc/register.h>
#include <sysc/tlm_target.h>
#include <sysc/utilities.h>
#include <util/bit_field.h>
#include "scc/register.h"
#include "scc/tlm_target.h"
#include "scc/utilities.h"
namespace sysc {
class uart_regs : public sc_core::sc_module, public sysc::resetable {
class uart_regs : public sc_core::sc_module, public scc::resetable {
public:
// storage declarations
BEGIN_BF_DECL(txdata_t, uint32_t);
@ -82,17 +82,17 @@ public:
END_BF_DECL() r_div;
// register declarations
sysc::sc_register<txdata_t> txdata;
sysc::sc_register<rxdata_t> rxdata;
sysc::sc_register<txctrl_t> txctrl;
sysc::sc_register<rxctrl_t> rxctrl;
sysc::sc_register<ie_t> ie;
sysc::sc_register<ip_t> ip;
sysc::sc_register<div_t> div;
scc::sc_register<txdata_t> txdata;
scc::sc_register<rxdata_t> rxdata;
scc::sc_register<txctrl_t> txctrl;
scc::sc_register<rxctrl_t> rxctrl;
scc::sc_register<ie_t> ie;
scc::sc_register<ip_t> ip;
scc::sc_register<div_t> div;
uart_regs(sc_core::sc_module_name nm);
template <unsigned BUSWIDTH = 32> void registerResources(sysc::tlm_target<BUSWIDTH> &target);
template <unsigned BUSWIDTH = 32> void registerResources(scc::tlm_target<BUSWIDTH> &target);
};
}
//////////////////////////////////////////////////////////////////////////////
@ -109,7 +109,7 @@ inline sysc::uart_regs::uart_regs(sc_core::sc_module_name nm)
, NAMED(ip, r_ip, 0, *this)
, NAMED(div, r_div, 0, *this) {}
template <unsigned BUSWIDTH> inline void sysc::uart_regs::registerResources(sysc::tlm_target<BUSWIDTH> &target) {
template <unsigned BUSWIDTH> inline void sysc::uart_regs::registerResources(scc::tlm_target<BUSWIDTH> &target) {
target.addResource(txdata, 0x0UL);
target.addResource(rxdata, 0x4UL);
target.addResource(txctrl, 0x8UL);

4
riscv.sc/incl/sysc/SiFive/gpio.h
View File

@ -17,13 +17,13 @@
#ifndef _GPIO_H_
#define _GPIO_H_
#include <sysc/tlm_target.h>
#include "scc/tlm_target.h"
namespace sysc {
class gpio_regs;
class gpio : public sc_core::sc_module, public tlm_target<> {
class gpio : public sc_core::sc_module, public scc::tlm_target<> {
public:
SC_HAS_PROCESS(gpio);
sc_core::sc_in<sc_core::sc_time> clk_i;

12
riscv.sc/incl/sysc/SiFive/platform.h
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@ -33,10 +33,10 @@
#include <array>
#include <sysc/kernel/sc_module.h>
#include <sysc/memory.h>
#include <sysc/router.h>
#include <sysc/utilities.h>
#include "scc/memory.h"
#include "scc/router.h"
#include "scc/utilities.h"
#include "core_complex.h"
namespace sysc {
@ -46,7 +46,7 @@ public:
SC_HAS_PROCESS(platform);
SiFive::core_complex i_core_complex;
router<> i_router;
scc::router<> i_router;
uart i_uart0, i_uart1;
spi i_spi;
gpio i_gpio;
@ -55,8 +55,8 @@ public:
prci i_prci;
clint i_clint;
memory<512_MB, 32> i_mem_qspi;
memory<128_kB, 32> i_mem_ram;
scc::memory<512_MB, 32> i_mem_qspi;
scc::memory<128_kB, 32> i_mem_ram;
sc_core::sc_signal<sc_core::sc_time> s_clk;
sc_core::sc_signal<bool> s_rst, s_mtime_int, s_msie_int;

4
riscv.sc/incl/sysc/SiFive/plic.h
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@ -17,13 +17,13 @@
#ifndef _PLIC_H_
#define _PLIC_H_
#include <sysc/tlm_target.h>
#include "scc/tlm_target.h"
namespace sysc {
class plic_regs;
class plic : public sc_core::sc_module, public tlm_target<> {
class plic : public sc_core::sc_module, public scc::tlm_target<> {
public:
SC_HAS_PROCESS(plic);
sc_core::sc_in<sc_core::sc_time> clk_i;

4
riscv.sc/incl/sysc/SiFive/prci.h
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@ -17,13 +17,13 @@
#ifndef _PRCI_H_
#define _PRCI_H_
#include <sysc/tlm_target.h>
#include "scc/tlm_target.h"
namespace sysc {
class prci_regs;
class prci : public sc_core::sc_module, public tlm_target<> {
class prci : public sc_core::sc_module, public scc::tlm_target<> {
public:
SC_HAS_PROCESS(prci);
sc_core::sc_in<sc_core::sc_time> clk_i;

4
riscv.sc/incl/sysc/SiFive/spi.h
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@ -17,13 +17,13 @@
#ifndef _SPI_H_
#define _SPI_H_
#include <sysc/tlm_target.h>
#include "scc/tlm_target.h"
namespace sysc {
class spi_regs;
class spi : public sc_core::sc_module, public tlm_target<> {
class spi : public sc_core::sc_module, public scc::tlm_target<> {
public:
SC_HAS_PROCESS(spi);
sc_core::sc_in<sc_core::sc_time> clk_i;

4
riscv.sc/incl/sysc/SiFive/uart.h
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@ -17,13 +17,13 @@
#ifndef _UART_H_
#define _UART_H_
#include <sysc/tlm_target.h>
#include "scc/tlm_target.h"
namespace sysc {
class uart_regs;
class uart : public sc_core::sc_module, public tlm_target<> {
class uart : public sc_core::sc_module, public scc::tlm_target<> {
public:
SC_HAS_PROCESS(uart);
sc_core::sc_in<sc_core::sc_time> clk_i;

16
riscv.sc/src/sc_main.cpp
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@ -26,10 +26,10 @@
#include <sr_report/sr_report.h>
#include <sstream>
#include <sysc/SiFive/platform.h>
#include <sysc/configurer.h>
#include <sysc/report.h>
#include <sysc/scv_tr_db.h>
#include <sysc/tracer.h>
#include "scc/configurer.h"
#include "scc/report.h"
#include "scc/scv_tr_db.h"
#include "scc/tracer.h"
using namespace sysc;
namespace po = boost::program_options;
@ -42,7 +42,7 @@ const size_t ERROR_UNHANDLED_EXCEPTION = 2;
int sc_main(int argc, char *argv[]) {
// sc_report_handler::set_handler(my_report_handler);
sysc::Logger<>::reporting_level() = log::ERROR;
scc::Logger<>::reporting_level() = logging::ERROR;
///////////////////////////////////////////////////////////////////////////
// CLI argument parsing
///////////////////////////////////////////////////////////////////////////
@ -84,7 +84,7 @@ int sc_main(int argc, char *argv[]) {
LOGGER(DEFAULT)::reporting_level() = l;
LOGGER(connection)::reporting_level() = l;
LOGGER(SystemC)::reporting_level() = l;
sysc::Logger<>::reporting_level() = l;
scc::Logger<>::reporting_level() = l;
}
if (vm.count("log-file")) {
// configure the connection logger
@ -100,12 +100,12 @@ int sc_main(int argc, char *argv[]) {
///////////////////////////////////////////////////////////////////////////
// set up tracing & transaction recording
///////////////////////////////////////////////////////////////////////////
sysc::tracer trace("simple_system", static_cast<sysc::tracer::file_type>(vm["trace"].as<uint8_t>() >> 1),
scc::tracer trace("simple_system", static_cast<scc::tracer::file_type>(vm["trace"].as<uint8_t>() >> 1),
vm["trace"].as<uint8_t>() != 0);
///////////////////////////////////////////////////////////////////////////
// set up configuration
///////////////////////////////////////////////////////////////////////////
sysc::configurer cfg(vm["config-file"].as<std::string>());
scc::configurer cfg(vm["config-file"].as<std::string>());
///////////////////////////////////////////////////////////////////////////
// instantiate top level
///////////////////////////////////////////////////////////////////////////

3
riscv.sc/src/sysc/aon.cpp
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@ -15,8 +15,9 @@
////////////////////////////////////////////////////////////////////////////////
#include "sysc/SiFive/aon.h"
#include "scc/utilities.h"
#include "sysc/SiFive/gen/aon_regs.h"
#include "sysc/utilities.h"
namespace sysc {

11
riscv.sc/src/sysc/clint.cpp
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@ -15,8 +15,9 @@
////////////////////////////////////////////////////////////////////////////////
#include "sysc/SiFive/clint.h"
#include "scc/utilities.h"
#include "sysc/SiFive/gen/clint_regs.h"
#include "sysc/utilities.h"
namespace sysc {
@ -37,20 +38,20 @@ clint::clint(sc_core::sc_module_name nm)
SC_METHOD(reset_cb);
sensitive << rst_i;
dont_initialize();
regs->mtimecmp.set_write_cb([this](sc_register<uint64_t> &reg, uint64_t data) -> bool {
regs->mtimecmp.set_write_cb([this](scc::sc_register<uint64_t> &reg, uint64_t data) -> bool {
if (!regs->in_reset()) {
reg.put(data);
this->update_mtime();
}
return true;
});
regs->mtime.set_read_cb([this](const sc_register<uint64_t> &reg, uint64_t &data) -> bool {
regs->mtime.set_read_cb([this](const scc::sc_register<uint64_t> &reg, uint64_t &data) -> bool {
this->update_mtime();
data = reg.get();
return true;
});
regs->mtime.set_write_cb([this](sc_register<uint64_t> &reg, uint64_t data) -> bool { return false; });
regs->msip.set_write_cb([this](sc_register<uint32_t> &reg, uint32_t data) -> bool {
regs->mtime.set_write_cb([this](scc::sc_register<uint64_t> &reg, uint64_t data) -> bool { return false; });
regs->msip.set_write_cb([this](scc::sc_register<uint32_t> &reg, uint32_t data) -> bool {
reg.put(data);
msip_int_o.write(regs->r_msip.msip);
return true;

3
riscv.sc/src/sysc/core_complex.cpp
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@ -39,7 +39,8 @@
#include <iss/iss.h>
#include <iss/vm_types.h>
#include <sysc/SiFive/core_complex.h>
#include <sysc/report.h>
#include "scc/report.h"
namespace sysc {
namespace SiFive {

3
riscv.sc/src/sysc/gpio.cpp
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@ -15,8 +15,9 @@
////////////////////////////////////////////////////////////////////////////////
#include "sysc/SiFive/gpio.h"
#include "scc/utilities.h"
#include "sysc/SiFive/gen/gpio_regs.h"
#include "sysc/utilities.h"
namespace sysc {

3
riscv.sc/src/sysc/plic.cpp
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@ -15,8 +15,9 @@
////////////////////////////////////////////////////////////////////////////////
#include "sysc/SiFive/plic.h"
#include "scc/utilities.h"
#include "sysc/SiFive/gen/plic_regs.h"
#include "sysc/utilities.h"
namespace sysc {

7
riscv.sc/src/sysc/prci.cpp
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@ -15,8 +15,9 @@
////////////////////////////////////////////////////////////////////////////////
#include "sysc/SiFive/prci.h"
#include "scc/utilities.h"
#include "sysc/SiFive/gen/prci_regs.h"
#include "sysc/utilities.h"
namespace sysc {
@ -36,14 +37,14 @@ prci::prci(sc_core::sc_module_name nm)
sensitive << hfrosc_en_evt;
dont_initialize();
regs->hfrosccfg.set_write_cb([this](sysc::sc_register<uint32_t> &reg, uint32_t data) -> bool {
regs->hfrosccfg.set_write_cb([this](scc::sc_register<uint32_t> &reg, uint32_t data) -> bool {
reg.put(data);
if (this->regs->r_hfrosccfg & (1 << 30)) { // check rosc_en
this->hfrosc_en_evt.notify(1, sc_core::SC_US);
}
return true;
});
regs->pllcfg.set_write_cb([this](sysc::sc_register<uint32_t> &reg, uint32_t data) -> bool {
regs->pllcfg.set_write_cb([this](scc::sc_register<uint32_t> &reg, uint32_t data) -> bool {
reg.put(data);
auto &pllcfg = this->regs->r_pllcfg;
if (pllcfg.pllbypass == 0 && pllcfg.pllq != 0) { // set pll_lock if pll is selected

3
riscv.sc/src/sysc/spi.cpp
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@ -15,8 +15,9 @@
////////////////////////////////////////////////////////////////////////////////
#include "sysc/SiFive/spi.h"
#include "scc/utilities.h"
#include "sysc/SiFive/gen/spi_regs.h"
#include "sysc/utilities.h"
namespace sysc {

7
riscv.sc/src/sysc/uart.cpp
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@ -15,9 +15,10 @@
////////////////////////////////////////////////////////////////////////////////
#include "sysc/SiFive/uart.h"
#include "scc/report.h"
#include "scc/utilities.h"
#include "sysc/SiFive/gen/uart_regs.h"
#include "sysc/report.h"
#include "sysc/utilities.h"
namespace sysc {
@ -33,7 +34,7 @@ uart::uart(sc_core::sc_module_name nm)
SC_METHOD(reset_cb);
sensitive << rst_i;
dont_initialize();
regs->txdata.set_write_cb([this](sc_register<uint32_t> &reg, uint32_t data) -> bool {
regs->txdata.set_write_cb([this](scc::sc_register<uint32_t> &reg, uint32_t data) -> bool {
if (!this->regs->in_reset()) {
reg.put(data);
this->transmit_data();

14
riscv/incl/iss/arch/riscv_hart_msu_vp.h
View File

@ -893,10 +893,10 @@ iss::status riscv_hart_msu_vp<BASE>::read_mem(phys_addr_t paddr, unsigned length
const auto &p = mem(paddr.val / mem.page_size);
auto offs = paddr.val & mem.page_addr_mask;
std::copy(p.data() + offs, p.data() + offs + length, data);
}
}
return iss::Ok;
}
}
}
template <typename BASE>
iss::status riscv_hart_msu_vp<BASE>::write_mem(phys_addr_t paddr, unsigned length, const uint8_t *const data) {
@ -911,22 +911,20 @@ iss::status riscv_hart_msu_vp<BASE>::write_mem(phys_addr_t paddr, unsigned lengt
std::cout << uart_buf.str();
uart_buf.str("");
}
return iss::Ok;
break;
case 0x10008000: { // HFROSC base, hfrosccfg reg
mem_type::page_type &p = mem(paddr.val / mem.page_size);
size_t offs = paddr.val & mem.page_addr_mask;
std::copy(data, data + length, p.data() + offs);
uint8_t &x = *(p.data() + offs + 3);
if (x & 0x40) x |= 0x80; // hfroscrdy = 1 if hfroscen==1
return iss::Ok;
}
} break;
case 0x10008008: { // HFROSC base, pllcfg reg
mem_type::page_type &p = mem(paddr.val / mem.page_size);
size_t offs = paddr.val & mem.page_addr_mask;
std::copy(data, data + length, p.data() + offs);
uint8_t &x = *(p.data() + offs + 3);
x |= 0x80; // set pll lock upon writing
return iss::Ok;
} break;
default: {
mem_type::page_type &p = mem(paddr.val / mem.page_size);
@ -969,10 +967,10 @@ iss::status riscv_hart_msu_vp<BASE>::write_mem(phys_addr_t paddr, unsigned lengt
*reinterpret_cast<uint64_t *>(p.data() + (tohost & mem.page_addr_mask)) = fhostvar;
}
}
}
}
return iss::Ok;
}
}
}
template <typename BASE> void riscv_hart_msu_vp<BASE>::check_interrupt() {
auto status = csr[mstatus];

2
sc-components

@ -1 +1 @@
Subproject commit 35379b77b6297557de15e37c009501dbdfc747f7
Subproject commit f1c733dc2caed17742feca32a275eb21d15a4c8d