DBT-RISE/DBT-RISE-TGC
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adds comment to indicate purpose of arch state members

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This commit is contained in:
Eyck Jentzsch 2025-03-19 12:03:12 +01:00
parent 31c6bb55f4
commit cbe4c2d62f
2 changed files with 10 additions and 10 deletions
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10
gen_input/templates/CORENAME.h.gtl
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@ -146,11 +146,11 @@ struct ${coreDef.name.toLowerCase()}: public arch_if {
uint${byteSize(reg.size)}_t ${reg.name} = 0;<% uint${byteSize(reg.size)}_t ${reg.name} = 0;<%
}}%> }}%>
uint32_t trap_state = 0, pending_trap = 0; uint32_t trap_state = 0, pending_trap = 0;
uint64_t icount = 0; uint64_t icount = 0; // counts number of instructions undisturbed
uint64_t cycle = 0; uint64_t cycle = 0; // counts number of cycles, in functional mode equals icount
uint64_t instret = 0; uint64_t instret = 0; // counts number of instructions, can be reset via CSR write
uint32_t instruction = 0; uint32_t instruction = 0; // holds op code of currently executed instruction
uint32_t last_branch = 0; uint32_t last_branch = 0; // indicates if last branch was taken
} reg; } reg;
#pragma pack(pop) #pragma pack(pop)
std::array<address_type, 4> addr_mode; std::array<address_type, 4> addr_mode;

10
src/iss/arch/tgc5c.h
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@ -237,11 +237,11 @@ struct tgc5c: public arch_if {
uint8_t PRIV = 0; uint8_t PRIV = 0;
uint32_t DPC = 0; uint32_t DPC = 0;
uint32_t trap_state = 0, pending_trap = 0; uint32_t trap_state = 0, pending_trap = 0;
uint64_t icount = 0; uint64_t icount = 0; // counts number of instructions undisturbed
uint64_t cycle = 0; uint64_t cycle = 0; // counts number of cycles, in functional mode equals icount
uint64_t instret = 0; uint64_t instret = 0; // counts number of instructions, can be reset via CSR write
uint32_t instruction = 0; uint32_t instruction = 0; // holds op code of currently executed instruction
uint32_t last_branch = 0; uint32_t last_branch = 0; // indicates if last branch was taken
} reg; } reg;
#pragma pack(pop) #pragma pack(pop)