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updates naming in checked-in sources

This commit is contained in:
Eyck Jentzsch 2023-09-19 12:11:49 +02:00
parent 40f50b0ec0
commit c7038cafa5
2 changed files with 108 additions and 108 deletions
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54
src/iss/arch/tgc5c.h
View File

@ -141,35 +141,35 @@ template <> struct traits<tgc5c> {
DIVU = 54, DIVU = 54,
REM = 55, REM = 55,
REMU = 56, REMU = 56,
CADDI4SPN = 57, C__ADDI4SPN = 57,
CLW = 58, C__LW = 58,
CSW = 59, C__SW = 59,
CADDI = 60, C__ADDI = 60,
CNOP = 61, C__NOP = 61,
CJAL = 62, C__JAL = 62,
CLI = 63, C__LI = 63,
CLUI = 64, C__LUI = 64,
CADDI16SP = 65, C__ADDI16SP = 65,
__reserved_clui = 66, __reserved_clui = 66,
CSRLI = 67, C__SRLI = 67,
CSRAI = 68, C__SRAI = 68,
CANDI = 69, C__ANDI = 69,
CSUB = 70, C__SUB = 70,
CXOR = 71, C__XOR = 71,
COR = 72, C__OR = 72,
CAND = 73, C__AND = 73,
CJ = 74, C__J = 74,
CBEQZ = 75, C__BEQZ = 75,
CBNEZ = 76, C__BNEZ = 76,
CSLLI = 77, C__SLLI = 77,
CLWSP = 78, C__LWSP = 78,
CMV = 79, C__MV = 79,
CJR = 80, C__JR = 80,
__reserved_cmv = 81, __reserved_cmv = 81,
CADD = 82, C__ADD = 82,
CJALR = 83, C__JALR = 83,
CEBREAK = 84, C__EBREAK = 84,
CSWSP = 85, C__SWSP = 85,
DII = 86, DII = 86,
MAX_OPCODE MAX_OPCODE
}; };

162
src/vm/interp/vm_tgc5c.cpp
View File

@ -210,35 +210,35 @@ private:
{32, 0b00000010000000000101000000110011, 0b11111110000000000111000001111111, arch::traits<ARCH>::opcode_e::DIVU}, {32, 0b00000010000000000101000000110011, 0b11111110000000000111000001111111, arch::traits<ARCH>::opcode_e::DIVU},
{32, 0b00000010000000000110000000110011, 0b11111110000000000111000001111111, arch::traits<ARCH>::opcode_e::REM}, {32, 0b00000010000000000110000000110011, 0b11111110000000000111000001111111, arch::traits<ARCH>::opcode_e::REM},
{32, 0b00000010000000000111000000110011, 0b11111110000000000111000001111111, arch::traits<ARCH>::opcode_e::REMU}, {32, 0b00000010000000000111000000110011, 0b11111110000000000111000001111111, arch::traits<ARCH>::opcode_e::REMU},
{16, 0b0000000000000000, 0b1110000000000011, arch::traits<ARCH>::opcode_e::CADDI4SPN}, {16, 0b0000000000000000, 0b1110000000000011, arch::traits<ARCH>::opcode_e::C__ADDI4SPN},
{16, 0b0100000000000000, 0b1110000000000011, arch::traits<ARCH>::opcode_e::CLW}, {16, 0b0100000000000000, 0b1110000000000011, arch::traits<ARCH>::opcode_e::C__LW},
{16, 0b1100000000000000, 0b1110000000000011, arch::traits<ARCH>::opcode_e::CSW}, {16, 0b1100000000000000, 0b1110000000000011, arch::traits<ARCH>::opcode_e::C__SW},
{16, 0b0000000000000001, 0b1110000000000011, arch::traits<ARCH>::opcode_e::CADDI}, {16, 0b0000000000000001, 0b1110000000000011, arch::traits<ARCH>::opcode_e::C__ADDI},
{16, 0b0000000000000001, 0b1110111110000011, arch::traits<ARCH>::opcode_e::CNOP}, {16, 0b0000000000000001, 0b1110111110000011, arch::traits<ARCH>::opcode_e::C__NOP},
{16, 0b0010000000000001, 0b1110000000000011, arch::traits<ARCH>::opcode_e::CJAL}, {16, 0b0010000000000001, 0b1110000000000011, arch::traits<ARCH>::opcode_e::C__JAL},
{16, 0b0100000000000001, 0b1110000000000011, arch::traits<ARCH>::opcode_e::CLI}, {16, 0b0100000000000001, 0b1110000000000011, arch::traits<ARCH>::opcode_e::C__LI},
{16, 0b0110000000000001, 0b1110000000000011, arch::traits<ARCH>::opcode_e::CLUI}, {16, 0b0110000000000001, 0b1110000000000011, arch::traits<ARCH>::opcode_e::C__LUI},
{16, 0b0110000100000001, 0b1110111110000011, arch::traits<ARCH>::opcode_e::CADDI16SP}, {16, 0b0110000100000001, 0b1110111110000011, arch::traits<ARCH>::opcode_e::C__ADDI16SP},
{16, 0b0110000000000001, 0b1111000001111111, arch::traits<ARCH>::opcode_e::__reserved_clui}, {16, 0b0110000000000001, 0b1111000001111111, arch::traits<ARCH>::opcode_e::__reserved_clui},
{16, 0b1000000000000001, 0b1111110000000011, arch::traits<ARCH>::opcode_e::CSRLI}, {16, 0b1000000000000001, 0b1111110000000011, arch::traits<ARCH>::opcode_e::C__SRLI},
{16, 0b1000010000000001, 0b1111110000000011, arch::traits<ARCH>::opcode_e::CSRAI}, {16, 0b1000010000000001, 0b1111110000000011, arch::traits<ARCH>::opcode_e::C__SRAI},
{16, 0b1000100000000001, 0b1110110000000011, arch::traits<ARCH>::opcode_e::CANDI}, {16, 0b1000100000000001, 0b1110110000000011, arch::traits<ARCH>::opcode_e::C__ANDI},
{16, 0b1000110000000001, 0b1111110001100011, arch::traits<ARCH>::opcode_e::CSUB}, {16, 0b1000110000000001, 0b1111110001100011, arch::traits<ARCH>::opcode_e::C__SUB},
{16, 0b1000110000100001, 0b1111110001100011, arch::traits<ARCH>::opcode_e::CXOR}, {16, 0b1000110000100001, 0b1111110001100011, arch::traits<ARCH>::opcode_e::C__XOR},
{16, 0b1000110001000001, 0b1111110001100011, arch::traits<ARCH>::opcode_e::COR}, {16, 0b1000110001000001, 0b1111110001100011, arch::traits<ARCH>::opcode_e::C__OR},
{16, 0b1000110001100001, 0b1111110001100011, arch::traits<ARCH>::opcode_e::CAND}, {16, 0b1000110001100001, 0b1111110001100011, arch::traits<ARCH>::opcode_e::C__AND},
{16, 0b1010000000000001, 0b1110000000000011, arch::traits<ARCH>::opcode_e::CJ}, {16, 0b1010000000000001, 0b1110000000000011, arch::traits<ARCH>::opcode_e::C__J},
{16, 0b1100000000000001, 0b1110000000000011, arch::traits<ARCH>::opcode_e::CBEQZ}, {16, 0b1100000000000001, 0b1110000000000011, arch::traits<ARCH>::opcode_e::C__BEQZ},
{16, 0b1110000000000001, 0b1110000000000011, arch::traits<ARCH>::opcode_e::CBNEZ}, {16, 0b1110000000000001, 0b1110000000000011, arch::traits<ARCH>::opcode_e::C__BNEZ},
{16, 0b0000000000000010, 0b1111000000000011, arch::traits<ARCH>::opcode_e::CSLLI}, {16, 0b0000000000000010, 0b1111000000000011, arch::traits<ARCH>::opcode_e::C__SLLI},
{16, 0b0100000000000010, 0b1110000000000011, arch::traits<ARCH>::opcode_e::CLWSP}, {16, 0b0100000000000010, 0b1110000000000011, arch::traits<ARCH>::opcode_e::C__LWSP},
{16, 0b1000000000000010, 0b1111000000000011, arch::traits<ARCH>::opcode_e::CMV}, {16, 0b1000000000000010, 0b1111000000000011, arch::traits<ARCH>::opcode_e::C__MV},
{16, 0b1000000000000010, 0b1111000001111111, arch::traits<ARCH>::opcode_e::CJR}, {16, 0b1000000000000010, 0b1111000001111111, arch::traits<ARCH>::opcode_e::C__JR},
{16, 0b1000000000000010, 0b1111111111111111, arch::traits<ARCH>::opcode_e::__reserved_cmv}, {16, 0b1000000000000010, 0b1111111111111111, arch::traits<ARCH>::opcode_e::__reserved_cmv},
{16, 0b1001000000000010, 0b1111000000000011, arch::traits<ARCH>::opcode_e::CADD}, {16, 0b1001000000000010, 0b1111000000000011, arch::traits<ARCH>::opcode_e::C__ADD},
{16, 0b1001000000000010, 0b1111000001111111, arch::traits<ARCH>::opcode_e::CJALR}, {16, 0b1001000000000010, 0b1111000001111111, arch::traits<ARCH>::opcode_e::C__JALR},
{16, 0b1001000000000010, 0b1111111111111111, arch::traits<ARCH>::opcode_e::CEBREAK}, {16, 0b1001000000000010, 0b1111111111111111, arch::traits<ARCH>::opcode_e::C__EBREAK},
{16, 0b1100000000000010, 0b1110000000000011, arch::traits<ARCH>::opcode_e::CSWSP}, {16, 0b1100000000000010, 0b1110000000000011, arch::traits<ARCH>::opcode_e::C__SWSP},
{16, 0b0000000000000000, 0b1111111111111111, arch::traits<ARCH>::opcode_e::DII}, {16, 0b0000000000000000, 0b1111111111111111, arch::traits<ARCH>::opcode_e::DII},
}}; }};
@ -2010,13 +2010,13 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
} }
break; break;
}// @suppress("No break at end of case") }// @suppress("No break at end of case")
case arch::traits<ARCH>::opcode_e::CADDI4SPN: { case arch::traits<ARCH>::opcode_e::C__ADDI4SPN: {
uint8_t rd = ((bit_sub<2,3>(instr))); uint8_t rd = ((bit_sub<2,3>(instr)));
uint16_t imm = ((bit_sub<5,1>(instr) << 3) | (bit_sub<6,1>(instr) << 2) | (bit_sub<7,4>(instr) << 6) | (bit_sub<11,2>(instr) << 4)); uint16_t imm = ((bit_sub<5,1>(instr) << 3) | (bit_sub<6,1>(instr) << 2) | (bit_sub<7,4>(instr) << 6) | (bit_sub<11,2>(instr) << 4));
if(this->disass_enabled){ if(this->disass_enabled){
/* generate console output when executing the command */ /* generate console output when executing the command */
auto mnemonic = fmt::format( auto mnemonic = fmt::format(
"{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "caddi4spn"), "{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "c.addi4spn"),
fmt::arg("rd", name(8+rd)), fmt::arg("imm", imm)); fmt::arg("rd", name(8+rd)), fmt::arg("imm", imm));
this->core.disass_output(pc.val, mnemonic); this->core.disass_output(pc.val, mnemonic);
} }
@ -2034,14 +2034,14 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
} }
break; break;
}// @suppress("No break at end of case") }// @suppress("No break at end of case")
case arch::traits<ARCH>::opcode_e::CLW: { case arch::traits<ARCH>::opcode_e::C__LW: {
uint8_t rd = ((bit_sub<2,3>(instr))); uint8_t rd = ((bit_sub<2,3>(instr)));
uint8_t uimm = ((bit_sub<5,1>(instr) << 6) | (bit_sub<6,1>(instr) << 2) | (bit_sub<10,3>(instr) << 3)); uint8_t uimm = ((bit_sub<5,1>(instr) << 6) | (bit_sub<6,1>(instr) << 2) | (bit_sub<10,3>(instr) << 3));
uint8_t rs1 = ((bit_sub<7,3>(instr))); uint8_t rs1 = ((bit_sub<7,3>(instr)));
if(this->disass_enabled){ if(this->disass_enabled){
/* generate console output when executing the command */ /* generate console output when executing the command */
auto mnemonic = fmt::format( auto mnemonic = fmt::format(
"{mnemonic:10} {rd}, {uimm:#05x}({rs1})", fmt::arg("mnemonic", "clw"), "{mnemonic:10} {rd}, {uimm:#05x}({rs1})", fmt::arg("mnemonic", "c.lw"),
fmt::arg("rd", name(8+rd)), fmt::arg("uimm", uimm), fmt::arg("rs1", name(8+rs1))); fmt::arg("rd", name(8+rd)), fmt::arg("uimm", uimm), fmt::arg("rs1", name(8+rs1)));
this->core.disass_output(pc.val, mnemonic); this->core.disass_output(pc.val, mnemonic);
} }
@ -2057,14 +2057,14 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
} }
break; break;
}// @suppress("No break at end of case") }// @suppress("No break at end of case")
case arch::traits<ARCH>::opcode_e::CSW: { case arch::traits<ARCH>::opcode_e::C__SW: {
uint8_t rs2 = ((bit_sub<2,3>(instr))); uint8_t rs2 = ((bit_sub<2,3>(instr)));
uint8_t uimm = ((bit_sub<5,1>(instr) << 6) | (bit_sub<6,1>(instr) << 2) | (bit_sub<10,3>(instr) << 3)); uint8_t uimm = ((bit_sub<5,1>(instr) << 6) | (bit_sub<6,1>(instr) << 2) | (bit_sub<10,3>(instr) << 3));
uint8_t rs1 = ((bit_sub<7,3>(instr))); uint8_t rs1 = ((bit_sub<7,3>(instr)));
if(this->disass_enabled){ if(this->disass_enabled){
/* generate console output when executing the command */ /* generate console output when executing the command */
auto mnemonic = fmt::format( auto mnemonic = fmt::format(
"{mnemonic:10} {rs2}, {uimm:#05x}({rs1})", fmt::arg("mnemonic", "csw"), "{mnemonic:10} {rs2}, {uimm:#05x}({rs1})", fmt::arg("mnemonic", "c.sw"),
fmt::arg("rs2", name(8+rs2)), fmt::arg("uimm", uimm), fmt::arg("rs1", name(8+rs1))); fmt::arg("rs2", name(8+rs2)), fmt::arg("uimm", uimm), fmt::arg("rs1", name(8+rs1)));
this->core.disass_output(pc.val, mnemonic); this->core.disass_output(pc.val, mnemonic);
} }
@ -2079,13 +2079,13 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
} }
break; break;
}// @suppress("No break at end of case") }// @suppress("No break at end of case")
case arch::traits<ARCH>::opcode_e::CADDI: { case arch::traits<ARCH>::opcode_e::C__ADDI: {
uint8_t imm = ((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5)); uint8_t imm = ((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5));
uint8_t rs1 = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<7,5>(instr)));
if(this->disass_enabled){ if(this->disass_enabled){
/* generate console output when executing the command */ /* generate console output when executing the command */
auto mnemonic = fmt::format( auto mnemonic = fmt::format(
"{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "caddi"), "{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c.addi"),
fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm));
this->core.disass_output(pc.val, mnemonic); this->core.disass_output(pc.val, mnemonic);
} }
@ -2105,11 +2105,11 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
} }
break; break;
}// @suppress("No break at end of case") }// @suppress("No break at end of case")
case arch::traits<ARCH>::opcode_e::CNOP: { case arch::traits<ARCH>::opcode_e::C__NOP: {
uint8_t nzimm = ((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5)); uint8_t nzimm = ((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5));
if(this->disass_enabled){ if(this->disass_enabled){
/* generate console output when executing the command */ /* generate console output when executing the command */
this->core.disass_output(pc.val, "cnop"); this->core.disass_output(pc.val, "c__nop");
} }
// used registers// calculate next pc value // used registers// calculate next pc value
*NEXT_PC = *PC + 2; *NEXT_PC = *PC + 2;
@ -2118,12 +2118,12 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
} }
break; break;
}// @suppress("No break at end of case") }// @suppress("No break at end of case")
case arch::traits<ARCH>::opcode_e::CJAL: { case arch::traits<ARCH>::opcode_e::C__JAL: {
uint16_t imm = ((bit_sub<2,1>(instr) << 5) | (bit_sub<3,3>(instr) << 1) | (bit_sub<6,1>(instr) << 7) | (bit_sub<7,1>(instr) << 6) | (bit_sub<8,1>(instr) << 10) | (bit_sub<9,2>(instr) << 8) | (bit_sub<11,1>(instr) << 4) | (bit_sub<12,1>(instr) << 11)); uint16_t imm = ((bit_sub<2,1>(instr) << 5) | (bit_sub<3,3>(instr) << 1) | (bit_sub<6,1>(instr) << 7) | (bit_sub<7,1>(instr) << 6) | (bit_sub<8,1>(instr) << 10) | (bit_sub<9,2>(instr) << 8) | (bit_sub<11,1>(instr) << 4) | (bit_sub<12,1>(instr) << 11));
if(this->disass_enabled){ if(this->disass_enabled){
/* generate console output when executing the command */ /* generate console output when executing the command */
auto mnemonic = fmt::format( auto mnemonic = fmt::format(
"{mnemonic:10} {imm:#05x}", fmt::arg("mnemonic", "cjal"), "{mnemonic:10} {imm:#05x}", fmt::arg("mnemonic", "c.jal"),
fmt::arg("imm", imm)); fmt::arg("imm", imm));
this->core.disass_output(pc.val, mnemonic); this->core.disass_output(pc.val, mnemonic);
} }
@ -2138,13 +2138,13 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
} }
break; break;
}// @suppress("No break at end of case") }// @suppress("No break at end of case")
case arch::traits<ARCH>::opcode_e::CLI: { case arch::traits<ARCH>::opcode_e::C__LI: {
uint8_t imm = ((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5)); uint8_t imm = ((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5));
uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rd = ((bit_sub<7,5>(instr)));
if(this->disass_enabled){ if(this->disass_enabled){
/* generate console output when executing the command */ /* generate console output when executing the command */
auto mnemonic = fmt::format( auto mnemonic = fmt::format(
"{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "cli"), "{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "c.li"),
fmt::arg("rd", name(rd)), fmt::arg("imm", imm)); fmt::arg("rd", name(rd)), fmt::arg("imm", imm));
this->core.disass_output(pc.val, mnemonic); this->core.disass_output(pc.val, mnemonic);
} }
@ -2164,13 +2164,13 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
} }
break; break;
}// @suppress("No break at end of case") }// @suppress("No break at end of case")
case arch::traits<ARCH>::opcode_e::CLUI: { case arch::traits<ARCH>::opcode_e::C__LUI: {
uint32_t imm = ((bit_sub<2,5>(instr) << 12) | (bit_sub<12,1>(instr) << 17)); uint32_t imm = ((bit_sub<2,5>(instr) << 12) | (bit_sub<12,1>(instr) << 17));
uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rd = ((bit_sub<7,5>(instr)));
if(this->disass_enabled){ if(this->disass_enabled){
/* generate console output when executing the command */ /* generate console output when executing the command */
auto mnemonic = fmt::format( auto mnemonic = fmt::format(
"{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "clui"), "{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "c.lui"),
fmt::arg("rd", name(rd)), fmt::arg("imm", imm)); fmt::arg("rd", name(rd)), fmt::arg("imm", imm));
this->core.disass_output(pc.val, mnemonic); this->core.disass_output(pc.val, mnemonic);
} }
@ -2188,12 +2188,12 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
} }
break; break;
}// @suppress("No break at end of case") }// @suppress("No break at end of case")
case arch::traits<ARCH>::opcode_e::CADDI16SP: { case arch::traits<ARCH>::opcode_e::C__ADDI16SP: {
uint16_t nzimm = ((bit_sub<2,1>(instr) << 5) | (bit_sub<3,2>(instr) << 7) | (bit_sub<5,1>(instr) << 6) | (bit_sub<6,1>(instr) << 4) | (bit_sub<12,1>(instr) << 9)); uint16_t nzimm = ((bit_sub<2,1>(instr) << 5) | (bit_sub<3,2>(instr) << 7) | (bit_sub<5,1>(instr) << 6) | (bit_sub<6,1>(instr) << 4) | (bit_sub<12,1>(instr) << 9));
if(this->disass_enabled){ if(this->disass_enabled){
/* generate console output when executing the command */ /* generate console output when executing the command */
auto mnemonic = fmt::format( auto mnemonic = fmt::format(
"{mnemonic:10} {nzimm:#05x}", fmt::arg("mnemonic", "caddi16sp"), "{mnemonic:10} {nzimm:#05x}", fmt::arg("mnemonic", "c.addi16sp"),
fmt::arg("nzimm", nzimm)); fmt::arg("nzimm", nzimm));
this->core.disass_output(pc.val, mnemonic); this->core.disass_output(pc.val, mnemonic);
} }
@ -2225,13 +2225,13 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
} }
break; break;
}// @suppress("No break at end of case") }// @suppress("No break at end of case")
case arch::traits<ARCH>::opcode_e::CSRLI: { case arch::traits<ARCH>::opcode_e::C__SRLI: {
uint8_t shamt = ((bit_sub<2,5>(instr))); uint8_t shamt = ((bit_sub<2,5>(instr)));
uint8_t rs1 = ((bit_sub<7,3>(instr))); uint8_t rs1 = ((bit_sub<7,3>(instr)));
if(this->disass_enabled){ if(this->disass_enabled){
/* generate console output when executing the command */ /* generate console output when executing the command */
auto mnemonic = fmt::format( auto mnemonic = fmt::format(
"{mnemonic:10} {rs1}, {shamt}", fmt::arg("mnemonic", "csrli"), "{mnemonic:10} {rs1}, {shamt}", fmt::arg("mnemonic", "c.srli"),
fmt::arg("rs1", name(8+rs1)), fmt::arg("shamt", shamt)); fmt::arg("rs1", name(8+rs1)), fmt::arg("shamt", shamt));
this->core.disass_output(pc.val, mnemonic); this->core.disass_output(pc.val, mnemonic);
} }
@ -2244,13 +2244,13 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
} }
break; break;
}// @suppress("No break at end of case") }// @suppress("No break at end of case")
case arch::traits<ARCH>::opcode_e::CSRAI: { case arch::traits<ARCH>::opcode_e::C__SRAI: {
uint8_t shamt = ((bit_sub<2,5>(instr))); uint8_t shamt = ((bit_sub<2,5>(instr)));
uint8_t rs1 = ((bit_sub<7,3>(instr))); uint8_t rs1 = ((bit_sub<7,3>(instr)));
if(this->disass_enabled){ if(this->disass_enabled){
/* generate console output when executing the command */ /* generate console output when executing the command */
auto mnemonic = fmt::format( auto mnemonic = fmt::format(
"{mnemonic:10} {rs1}, {shamt}", fmt::arg("mnemonic", "csrai"), "{mnemonic:10} {rs1}, {shamt}", fmt::arg("mnemonic", "c.srai"),
fmt::arg("rs1", name(8+rs1)), fmt::arg("shamt", shamt)); fmt::arg("rs1", name(8+rs1)), fmt::arg("shamt", shamt));
this->core.disass_output(pc.val, mnemonic); this->core.disass_output(pc.val, mnemonic);
} }
@ -2270,13 +2270,13 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
} }
break; break;
}// @suppress("No break at end of case") }// @suppress("No break at end of case")
case arch::traits<ARCH>::opcode_e::CANDI: { case arch::traits<ARCH>::opcode_e::C__ANDI: {
uint8_t imm = ((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5)); uint8_t imm = ((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5));
uint8_t rs1 = ((bit_sub<7,3>(instr))); uint8_t rs1 = ((bit_sub<7,3>(instr)));
if(this->disass_enabled){ if(this->disass_enabled){
/* generate console output when executing the command */ /* generate console output when executing the command */
auto mnemonic = fmt::format( auto mnemonic = fmt::format(
"{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "candi"), "{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c.andi"),
fmt::arg("rs1", name(8+rs1)), fmt::arg("imm", imm)); fmt::arg("rs1", name(8+rs1)), fmt::arg("imm", imm));
this->core.disass_output(pc.val, mnemonic); this->core.disass_output(pc.val, mnemonic);
} }
@ -2289,13 +2289,13 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
} }
break; break;
}// @suppress("No break at end of case") }// @suppress("No break at end of case")
case arch::traits<ARCH>::opcode_e::CSUB: { case arch::traits<ARCH>::opcode_e::C__SUB: {
uint8_t rs2 = ((bit_sub<2,3>(instr))); uint8_t rs2 = ((bit_sub<2,3>(instr)));
uint8_t rd = ((bit_sub<7,3>(instr))); uint8_t rd = ((bit_sub<7,3>(instr)));
if(this->disass_enabled){ if(this->disass_enabled){
/* generate console output when executing the command */ /* generate console output when executing the command */
auto mnemonic = fmt::format( auto mnemonic = fmt::format(
"{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "csub"), "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c.sub"),
fmt::arg("rd", name(8+rd)), fmt::arg("rs2", name(8+rs2))); fmt::arg("rd", name(8+rd)), fmt::arg("rs2", name(8+rs2)));
this->core.disass_output(pc.val, mnemonic); this->core.disass_output(pc.val, mnemonic);
} }
@ -2308,13 +2308,13 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
} }
break; break;
}// @suppress("No break at end of case") }// @suppress("No break at end of case")
case arch::traits<ARCH>::opcode_e::CXOR: { case arch::traits<ARCH>::opcode_e::C__XOR: {
uint8_t rs2 = ((bit_sub<2,3>(instr))); uint8_t rs2 = ((bit_sub<2,3>(instr)));
uint8_t rd = ((bit_sub<7,3>(instr))); uint8_t rd = ((bit_sub<7,3>(instr)));
if(this->disass_enabled){ if(this->disass_enabled){
/* generate console output when executing the command */ /* generate console output when executing the command */
auto mnemonic = fmt::format( auto mnemonic = fmt::format(
"{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "cxor"), "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c.xor"),
fmt::arg("rd", name(8+rd)), fmt::arg("rs2", name(8+rs2))); fmt::arg("rd", name(8+rd)), fmt::arg("rs2", name(8+rs2)));
this->core.disass_output(pc.val, mnemonic); this->core.disass_output(pc.val, mnemonic);
} }
@ -2327,13 +2327,13 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
} }
break; break;
}// @suppress("No break at end of case") }// @suppress("No break at end of case")
case arch::traits<ARCH>::opcode_e::COR: { case arch::traits<ARCH>::opcode_e::C__OR: {
uint8_t rs2 = ((bit_sub<2,3>(instr))); uint8_t rs2 = ((bit_sub<2,3>(instr)));
uint8_t rd = ((bit_sub<7,3>(instr))); uint8_t rd = ((bit_sub<7,3>(instr)));
if(this->disass_enabled){ if(this->disass_enabled){
/* generate console output when executing the command */ /* generate console output when executing the command */
auto mnemonic = fmt::format( auto mnemonic = fmt::format(
"{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "cor"), "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c.or"),
fmt::arg("rd", name(8+rd)), fmt::arg("rs2", name(8+rs2))); fmt::arg("rd", name(8+rd)), fmt::arg("rs2", name(8+rs2)));
this->core.disass_output(pc.val, mnemonic); this->core.disass_output(pc.val, mnemonic);
} }
@ -2346,13 +2346,13 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
} }
break; break;
}// @suppress("No break at end of case") }// @suppress("No break at end of case")
case arch::traits<ARCH>::opcode_e::CAND: { case arch::traits<ARCH>::opcode_e::C__AND: {
uint8_t rs2 = ((bit_sub<2,3>(instr))); uint8_t rs2 = ((bit_sub<2,3>(instr)));
uint8_t rd = ((bit_sub<7,3>(instr))); uint8_t rd = ((bit_sub<7,3>(instr)));
if(this->disass_enabled){ if(this->disass_enabled){
/* generate console output when executing the command */ /* generate console output when executing the command */
auto mnemonic = fmt::format( auto mnemonic = fmt::format(
"{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "cand"), "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c.and"),
fmt::arg("rd", name(8+rd)), fmt::arg("rs2", name(8+rs2))); fmt::arg("rd", name(8+rd)), fmt::arg("rs2", name(8+rs2)));
this->core.disass_output(pc.val, mnemonic); this->core.disass_output(pc.val, mnemonic);
} }
@ -2365,12 +2365,12 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
} }
break; break;
}// @suppress("No break at end of case") }// @suppress("No break at end of case")
case arch::traits<ARCH>::opcode_e::CJ: { case arch::traits<ARCH>::opcode_e::C__J: {
uint16_t imm = ((bit_sub<2,1>(instr) << 5) | (bit_sub<3,3>(instr) << 1) | (bit_sub<6,1>(instr) << 7) | (bit_sub<7,1>(instr) << 6) | (bit_sub<8,1>(instr) << 10) | (bit_sub<9,2>(instr) << 8) | (bit_sub<11,1>(instr) << 4) | (bit_sub<12,1>(instr) << 11)); uint16_t imm = ((bit_sub<2,1>(instr) << 5) | (bit_sub<3,3>(instr) << 1) | (bit_sub<6,1>(instr) << 7) | (bit_sub<7,1>(instr) << 6) | (bit_sub<8,1>(instr) << 10) | (bit_sub<9,2>(instr) << 8) | (bit_sub<11,1>(instr) << 4) | (bit_sub<12,1>(instr) << 11));
if(this->disass_enabled){ if(this->disass_enabled){
/* generate console output when executing the command */ /* generate console output when executing the command */
auto mnemonic = fmt::format( auto mnemonic = fmt::format(
"{mnemonic:10} {imm:#05x}", fmt::arg("mnemonic", "cj"), "{mnemonic:10} {imm:#05x}", fmt::arg("mnemonic", "c.j"),
fmt::arg("imm", imm)); fmt::arg("imm", imm));
this->core.disass_output(pc.val, mnemonic); this->core.disass_output(pc.val, mnemonic);
} }
@ -2383,13 +2383,13 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
} }
break; break;
}// @suppress("No break at end of case") }// @suppress("No break at end of case")
case arch::traits<ARCH>::opcode_e::CBEQZ: { case arch::traits<ARCH>::opcode_e::C__BEQZ: {
uint16_t imm = ((bit_sub<2,1>(instr) << 5) | (bit_sub<3,2>(instr) << 1) | (bit_sub<5,2>(instr) << 6) | (bit_sub<10,2>(instr) << 3) | (bit_sub<12,1>(instr) << 8)); uint16_t imm = ((bit_sub<2,1>(instr) << 5) | (bit_sub<3,2>(instr) << 1) | (bit_sub<5,2>(instr) << 6) | (bit_sub<10,2>(instr) << 3) | (bit_sub<12,1>(instr) << 8));
uint8_t rs1 = ((bit_sub<7,3>(instr))); uint8_t rs1 = ((bit_sub<7,3>(instr)));
if(this->disass_enabled){ if(this->disass_enabled){
/* generate console output when executing the command */ /* generate console output when executing the command */
auto mnemonic = fmt::format( auto mnemonic = fmt::format(
"{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "cbeqz"), "{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c.beqz"),
fmt::arg("rs1", name(8+rs1)), fmt::arg("imm", imm)); fmt::arg("rs1", name(8+rs1)), fmt::arg("imm", imm));
this->core.disass_output(pc.val, mnemonic); this->core.disass_output(pc.val, mnemonic);
} }
@ -2405,13 +2405,13 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
} }
break; break;
}// @suppress("No break at end of case") }// @suppress("No break at end of case")
case arch::traits<ARCH>::opcode_e::CBNEZ: { case arch::traits<ARCH>::opcode_e::C__BNEZ: {
uint16_t imm = ((bit_sub<2,1>(instr) << 5) | (bit_sub<3,2>(instr) << 1) | (bit_sub<5,2>(instr) << 6) | (bit_sub<10,2>(instr) << 3) | (bit_sub<12,1>(instr) << 8)); uint16_t imm = ((bit_sub<2,1>(instr) << 5) | (bit_sub<3,2>(instr) << 1) | (bit_sub<5,2>(instr) << 6) | (bit_sub<10,2>(instr) << 3) | (bit_sub<12,1>(instr) << 8));
uint8_t rs1 = ((bit_sub<7,3>(instr))); uint8_t rs1 = ((bit_sub<7,3>(instr)));
if(this->disass_enabled){ if(this->disass_enabled){
/* generate console output when executing the command */ /* generate console output when executing the command */
auto mnemonic = fmt::format( auto mnemonic = fmt::format(
"{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "cbnez"), "{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c.bnez"),
fmt::arg("rs1", name(8+rs1)), fmt::arg("imm", imm)); fmt::arg("rs1", name(8+rs1)), fmt::arg("imm", imm));
this->core.disass_output(pc.val, mnemonic); this->core.disass_output(pc.val, mnemonic);
} }
@ -2427,13 +2427,13 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
} }
break; break;
}// @suppress("No break at end of case") }// @suppress("No break at end of case")
case arch::traits<ARCH>::opcode_e::CSLLI: { case arch::traits<ARCH>::opcode_e::C__SLLI: {
uint8_t nzuimm = ((bit_sub<2,5>(instr))); uint8_t nzuimm = ((bit_sub<2,5>(instr)));
uint8_t rs1 = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<7,5>(instr)));
if(this->disass_enabled){ if(this->disass_enabled){
/* generate console output when executing the command */ /* generate console output when executing the command */
auto mnemonic = fmt::format( auto mnemonic = fmt::format(
"{mnemonic:10} {rs1}, {nzuimm}", fmt::arg("mnemonic", "cslli"), "{mnemonic:10} {rs1}, {nzuimm}", fmt::arg("mnemonic", "c.slli"),
fmt::arg("rs1", name(rs1)), fmt::arg("nzuimm", nzuimm)); fmt::arg("rs1", name(rs1)), fmt::arg("nzuimm", nzuimm));
this->core.disass_output(pc.val, mnemonic); this->core.disass_output(pc.val, mnemonic);
} }
@ -2453,13 +2453,13 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
} }
break; break;
}// @suppress("No break at end of case") }// @suppress("No break at end of case")
case arch::traits<ARCH>::opcode_e::CLWSP: { case arch::traits<ARCH>::opcode_e::C__LWSP: {
uint8_t uimm = ((bit_sub<2,2>(instr) << 6) | (bit_sub<4,3>(instr) << 2) | (bit_sub<12,1>(instr) << 5)); uint8_t uimm = ((bit_sub<2,2>(instr) << 6) | (bit_sub<4,3>(instr) << 2) | (bit_sub<12,1>(instr) << 5));
uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rd = ((bit_sub<7,5>(instr)));
if(this->disass_enabled){ if(this->disass_enabled){
/* generate console output when executing the command */ /* generate console output when executing the command */
auto mnemonic = fmt::format( auto mnemonic = fmt::format(
"{mnemonic:10} {rd}, sp, {uimm:#05x}", fmt::arg("mnemonic", "clwsp"), "{mnemonic:10} {rd}, sp, {uimm:#05x}", fmt::arg("mnemonic", "c.lwsp"),
fmt::arg("rd", name(rd)), fmt::arg("uimm", uimm)); fmt::arg("rd", name(rd)), fmt::arg("uimm", uimm));
this->core.disass_output(pc.val, mnemonic); this->core.disass_output(pc.val, mnemonic);
} }
@ -2480,13 +2480,13 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
} }
break; break;
}// @suppress("No break at end of case") }// @suppress("No break at end of case")
case arch::traits<ARCH>::opcode_e::CMV: { case arch::traits<ARCH>::opcode_e::C__MV: {
uint8_t rs2 = ((bit_sub<2,5>(instr))); uint8_t rs2 = ((bit_sub<2,5>(instr)));
uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rd = ((bit_sub<7,5>(instr)));
if(this->disass_enabled){ if(this->disass_enabled){
/* generate console output when executing the command */ /* generate console output when executing the command */
auto mnemonic = fmt::format( auto mnemonic = fmt::format(
"{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "cmv"), "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c.mv"),
fmt::arg("rd", name(rd)), fmt::arg("rs2", name(rs2))); fmt::arg("rd", name(rd)), fmt::arg("rs2", name(rs2)));
this->core.disass_output(pc.val, mnemonic); this->core.disass_output(pc.val, mnemonic);
} }
@ -2506,12 +2506,12 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
} }
break; break;
}// @suppress("No break at end of case") }// @suppress("No break at end of case")
case arch::traits<ARCH>::opcode_e::CJR: { case arch::traits<ARCH>::opcode_e::C__JR: {
uint8_t rs1 = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<7,5>(instr)));
if(this->disass_enabled){ if(this->disass_enabled){
/* generate console output when executing the command */ /* generate console output when executing the command */
auto mnemonic = fmt::format( auto mnemonic = fmt::format(
"{mnemonic:10} {rs1}", fmt::arg("mnemonic", "cjr"), "{mnemonic:10} {rs1}", fmt::arg("mnemonic", "c.jr"),
fmt::arg("rs1", name(rs1))); fmt::arg("rs1", name(rs1)));
this->core.disass_output(pc.val, mnemonic); this->core.disass_output(pc.val, mnemonic);
} }
@ -2543,13 +2543,13 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
} }
break; break;
}// @suppress("No break at end of case") }// @suppress("No break at end of case")
case arch::traits<ARCH>::opcode_e::CADD: { case arch::traits<ARCH>::opcode_e::C__ADD: {
uint8_t rs2 = ((bit_sub<2,5>(instr))); uint8_t rs2 = ((bit_sub<2,5>(instr)));
uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rd = ((bit_sub<7,5>(instr)));
if(this->disass_enabled){ if(this->disass_enabled){
/* generate console output when executing the command */ /* generate console output when executing the command */
auto mnemonic = fmt::format( auto mnemonic = fmt::format(
"{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "cadd"), "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c.add"),
fmt::arg("rd", name(rd)), fmt::arg("rs2", name(rs2))); fmt::arg("rd", name(rd)), fmt::arg("rs2", name(rs2)));
this->core.disass_output(pc.val, mnemonic); this->core.disass_output(pc.val, mnemonic);
} }
@ -2569,12 +2569,12 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
} }
break; break;
}// @suppress("No break at end of case") }// @suppress("No break at end of case")
case arch::traits<ARCH>::opcode_e::CJALR: { case arch::traits<ARCH>::opcode_e::C__JALR: {
uint8_t rs1 = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<7,5>(instr)));
if(this->disass_enabled){ if(this->disass_enabled){
/* generate console output when executing the command */ /* generate console output when executing the command */
auto mnemonic = fmt::format( auto mnemonic = fmt::format(
"{mnemonic:10} {rs1}", fmt::arg("mnemonic", "cjalr"), "{mnemonic:10} {rs1}", fmt::arg("mnemonic", "c.jalr"),
fmt::arg("rs1", name(rs1))); fmt::arg("rs1", name(rs1)));
this->core.disass_output(pc.val, mnemonic); this->core.disass_output(pc.val, mnemonic);
} }
@ -2595,10 +2595,10 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
} }
break; break;
}// @suppress("No break at end of case") }// @suppress("No break at end of case")
case arch::traits<ARCH>::opcode_e::CEBREAK: { case arch::traits<ARCH>::opcode_e::C__EBREAK: {
if(this->disass_enabled){ if(this->disass_enabled){
/* generate console output when executing the command */ /* generate console output when executing the command */
this->core.disass_output(pc.val, "cebreak"); this->core.disass_output(pc.val, "c__ebreak");
} }
// used registers// calculate next pc value // used registers// calculate next pc value
*NEXT_PC = *PC + 2; *NEXT_PC = *PC + 2;
@ -2608,13 +2608,13 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
} }
break; break;
}// @suppress("No break at end of case") }// @suppress("No break at end of case")
case arch::traits<ARCH>::opcode_e::CSWSP: { case arch::traits<ARCH>::opcode_e::C__SWSP: {
uint8_t rs2 = ((bit_sub<2,5>(instr))); uint8_t rs2 = ((bit_sub<2,5>(instr)));
uint8_t uimm = ((bit_sub<7,2>(instr) << 6) | (bit_sub<9,4>(instr) << 2)); uint8_t uimm = ((bit_sub<7,2>(instr) << 6) | (bit_sub<9,4>(instr) << 2));
if(this->disass_enabled){ if(this->disass_enabled){
/* generate console output when executing the command */ /* generate console output when executing the command */
auto mnemonic = fmt::format( auto mnemonic = fmt::format(
"{mnemonic:10} {rs2}, {uimm:#05x}(sp)", fmt::arg("mnemonic", "cswsp"), "{mnemonic:10} {rs2}, {uimm:#05x}(sp)", fmt::arg("mnemonic", "c.swsp"),
fmt::arg("rs2", name(rs2)), fmt::arg("uimm", uimm)); fmt::arg("rs2", name(rs2)), fmt::arg("uimm", uimm));
this->core.disass_output(pc.val, mnemonic); this->core.disass_output(pc.val, mnemonic);
} }