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fix mepc mask

This commit is contained in:
Eyck Jentzsch 2021-07-09 13:01:22 +02:00
parent e68918c2e8
commit c592a26346
1 changed files with 3 additions and 4 deletions
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7
incl/iss/arch/riscv_hart_m_p.h
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@ -747,8 +747,7 @@ template <typename BASE> iss::status riscv_hart_m_p<BASE>::write_ip(unsigned add
} }
template <typename BASE> iss::status riscv_hart_m_p<BASE>::write_mepc(unsigned addr, reg_t val) { template <typename BASE> iss::status riscv_hart_m_p<BASE>::write_mepc(unsigned addr, reg_t val) {
auto mask = get_pc_mask(); csr[addr] = val & get_pc_mask();
csr[addr] = val;//(csr[addr] & ~mask) | (val & mask);
return iss::Ok; return iss::Ok;
} }
@ -891,11 +890,11 @@ template <typename BASE> uint64_t riscv_hart_m_p<BASE>::enter_trap(uint64_t flag
// calculate effective privilege level // calculate effective privilege level
if (trap_id == 0) { // exception if (trap_id == 0) { // exception
// store ret addr in xepc register // store ret addr in xepc register
csr[mepc] = static_cast<reg_t>(addr); // store actual address instruction of exception csr[mepc] = static_cast<reg_t>(addr) & get_pc_mask(); // store actual address instruction of exception
csr[mtval] = cause==2?((instr & 0x3)==3?instr:instr&0xffff):fault_data; csr[mtval] = cause==2?((instr & 0x3)==3?instr:instr&0xffff):fault_data;
fault_data = 0; fault_data = 0;
} else { } else {
csr[mepc] = this->reg.NEXT_PC; // store next address if interrupt csr[mepc] = this->reg.NEXT_PC & get_pc_mask(); // store next address if interrupt
this->reg.pending_trap = 0; this->reg.pending_trap = 0;
} }
csr[mcause] = (trap_id << 31) + cause; csr[mcause] = (trap_id << 31) + cause;