fix desscriptions to conform to ISA spec version 20191213 and TGF-C
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@ -0,0 +1,76 @@
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/*******************************************************************************
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* Copyright (C) 2017 - 2020 MINRES Technologies GmbH
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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*******************************************************************************/
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<%
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def getRegisterSizes(){
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def regs = registers.collect{it.size}
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regs[-1]=64 // correct for NEXT_PC
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regs+=[32, 32, 64] // append TRAP_STATE, PENDING_TRAP, ICOUNT
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return regs
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}
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%>
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#include "util/ities.h"
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#include <util/logging.h>
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#include <iss/arch/${coreDef.name.toLowerCase()}.h>
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#include <cstdio>
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#include <cstring>
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#include <fstream>
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using namespace iss::arch;
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constexpr std::array<const char*, ${registers.size}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_names;
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constexpr std::array<const char*, ${registers.size}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_aliases;
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constexpr std::array<const uint32_t, ${getRegisterSizes().size}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_bit_widths;
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constexpr std::array<const uint32_t, ${getRegisterSizes().size}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_byte_offsets;
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${coreDef.name.toLowerCase()}::${coreDef.name.toLowerCase()}() {
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reg.icount = 0;
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}
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${coreDef.name.toLowerCase()}::~${coreDef.name.toLowerCase()}() = default;
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void ${coreDef.name.toLowerCase()}::reset(uint64_t address) {
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for(size_t i=0; i<traits<${coreDef.name.toLowerCase()}>::NUM_REGS; ++i) set_reg(i, std::vector<uint8_t>(sizeof(traits<${coreDef.name.toLowerCase()}>::reg_t),0));
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reg.PC=address;
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reg.NEXT_PC=reg.PC;
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reg.PRIV=0x3;
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reg.trap_state=0;
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reg.icount=0;
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}
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uint8_t *${coreDef.name.toLowerCase()}::get_regs_base_ptr() {
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return reinterpret_cast<uint8_t*>(®);
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}
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${coreDef.name.toLowerCase()}::phys_addr_t ${coreDef.name.toLowerCase()}::virt2phys(const iss::addr_t &pc) {
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return phys_addr_t(pc); // change logical address to physical address
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}
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@ -168,14 +168,16 @@ struct ${coreDef.name.toLowerCase()}: public arch_if {
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inline uint32_t get_last_branch() { return reg.last_branch; }
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inline uint32_t get_last_branch() { return reg.last_branch; }
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protected:
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protected:
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#pragma pack(push, 1)
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struct ${coreDef.name}_regs {<%
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struct ${coreDef.name}_regs {<%
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registers.each { reg -> if(reg.size>0) {%>
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registers.each { reg -> if(reg.size>0) {%>
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uint${byteSize(reg.size)}_t ${reg.name} = 0;<%
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uint${byteSize(reg.size)}_t ${reg.name} = 0;<%
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}}%>
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}}%>
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uint32_t trap_state = 0, pending_trap = 0, machine_state = 0, last_branch = 0;
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uint32_t trap_state = 0, pending_trap = 0;
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uint64_t icount = 0;
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uint64_t icount = 0;
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uint32_t last_branch;
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} reg;
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} reg;
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#pragma pack(pop)
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std::array<address_type, 4> addr_mode;
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std::array<address_type, 4> addr_mode;
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uint64_t interrupt_sim=0;
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uint64_t interrupt_sim=0;
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@ -1,5 +1,5 @@
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/*******************************************************************************
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/*******************************************************************************
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* Copyright (C) 2017 - 2020 MINRES Technologies GmbH
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* Copyright (C) 2021 MINRES Technologies GmbH
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* All rights reserved.
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* All rights reserved.
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*
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*
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* Redistribution and use in source and binary forms, with or without
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* Redistribution and use in source and binary forms, with or without
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@ -29,48 +29,273 @@
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* POSSIBILITY OF SUCH DAMAGE.
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* POSSIBILITY OF SUCH DAMAGE.
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*
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*
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*******************************************************************************/
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*******************************************************************************/
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<%
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def getRegisterSizes(){
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#include "../fp_functions.h"
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def regs = registers.collect{it.size}
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regs[-1]=64 // correct for NEXT_PC
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regs+=[32, 32, 64] // append TRAP_STATE, PENDING_TRAP, ICOUNT
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return regs
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}
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%>
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#include "util/ities.h"
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#include <util/logging.h>
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#include <iss/arch/${coreDef.name.toLowerCase()}.h>
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#include <iss/arch/${coreDef.name.toLowerCase()}.h>
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#include <cstdio>
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#include <iss/arch/riscv_hart_m_p.h>
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#include <cstring>
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#include <iss/debugger/gdb_session.h>
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#include <fstream>
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#include <iss/debugger/server.h>
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#include <iss/iss.h>
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#include <iss/interp/vm_base.h>
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#include <util/logging.h>
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#include <sstream>
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#ifndef FMT_HEADER_ONLY
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#define FMT_HEADER_ONLY
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#endif
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#include <fmt/format.h>
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#include <array>
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#include <iss/debugger/riscv_target_adapter.h>
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namespace iss {
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namespace interp {
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namespace ${coreDef.name.toLowerCase()} {
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using namespace iss::arch;
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using namespace iss::arch;
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using namespace iss::debugger;
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constexpr std::array<const char*, ${registers.size}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_names;
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template <typename ARCH> class vm_impl : public iss::interp::vm_base<ARCH> {
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constexpr std::array<const char*, ${registers.size}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_aliases;
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public:
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constexpr std::array<const uint32_t, ${getRegisterSizes().size}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_bit_widths;
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using traits = arch::traits<ARCH>;
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constexpr std::array<const uint32_t, ${getRegisterSizes().size}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_byte_offsets;
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using super = typename iss::interp::vm_base<ARCH>;
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using virt_addr_t = typename super::virt_addr_t;
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using phys_addr_t = typename super::phys_addr_t;
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using code_word_t = typename super::code_word_t;
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using addr_t = typename super::addr_t;
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using reg_t = typename traits::reg_t;
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using mem_type_e = typename traits::mem_type_e;
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${coreDef.name.toLowerCase()}::${coreDef.name.toLowerCase()}() {
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vm_impl();
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reg.icount = 0;
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vm_impl(ARCH &core, unsigned core_id = 0, unsigned cluster_id = 0);
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void enableDebug(bool enable) { super::sync_exec = super::ALL_SYNC; }
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target_adapter_if *accquire_target_adapter(server_if *srv) override {
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debugger_if::dbg_enabled = true;
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if (super::tgt_adapter == nullptr)
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super::tgt_adapter = new riscv_target_adapter<ARCH>(srv, this->get_arch());
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return super::tgt_adapter;
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}
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protected:
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using this_class = vm_impl<ARCH>;
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using compile_ret_t = virt_addr_t;
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using compile_func = compile_ret_t (this_class::*)(virt_addr_t &pc, code_word_t instr);
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inline const char *name(size_t index){return traits::reg_aliases.at(index);}
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virt_addr_t execute_inst(virt_addr_t start, std::function<bool(virt_addr_t&)> pred) override;
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// some compile time constants
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// enum { MASK16 = 0b1111110001100011, MASK32 = 0b11111111111100000111000001111111 };
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enum { MASK16 = 0b1111111111111111, MASK32 = 0b11111111111100000111000001111111 };
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enum { EXTR_MASK16 = MASK16 >> 2, EXTR_MASK32 = MASK32 >> 2 };
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enum { LUT_SIZE = 1 << util::bit_count(EXTR_MASK32), LUT_SIZE_C = 1 << util::bit_count(EXTR_MASK16) };
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std::array<compile_func, LUT_SIZE> lut;
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std::array<compile_func, LUT_SIZE_C> lut_00, lut_01, lut_10;
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std::array<compile_func, LUT_SIZE> lut_11;
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std::array<compile_func *, 4> qlut;
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std::array<const uint32_t, 4> lutmasks = {{EXTR_MASK16, EXTR_MASK16, EXTR_MASK16, EXTR_MASK32}};
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void expand_bit_mask(int pos, uint32_t mask, uint32_t value, uint32_t valid, uint32_t idx, compile_func lut[],
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compile_func f) {
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if (pos < 0) {
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lut[idx] = f;
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} else {
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auto bitmask = 1UL << pos;
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if ((mask & bitmask) == 0) {
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expand_bit_mask(pos - 1, mask, value, valid, idx, lut, f);
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} else {
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if ((valid & bitmask) == 0) {
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expand_bit_mask(pos - 1, mask, value, valid, (idx << 1), lut, f);
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expand_bit_mask(pos - 1, mask, value, valid, (idx << 1) + 1, lut, f);
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} else {
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auto new_val = idx << 1;
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if ((value & bitmask) != 0) new_val++;
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expand_bit_mask(pos - 1, mask, value, valid, new_val, lut, f);
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}
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}
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}
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}
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inline uint32_t extract_fields(uint32_t val) { return extract_fields(29, val >> 2, lutmasks[val & 0x3], 0); }
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uint32_t extract_fields(int pos, uint32_t val, uint32_t mask, uint32_t lut_val) {
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if (pos >= 0) {
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auto bitmask = 1UL << pos;
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if ((mask & bitmask) == 0) {
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lut_val = extract_fields(pos - 1, val, mask, lut_val);
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} else {
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auto new_val = lut_val << 1;
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if ((val & bitmask) != 0) new_val++;
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lut_val = extract_fields(pos - 1, val, mask, new_val);
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}
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}
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return lut_val;
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}
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inline void raise(uint16_t trap_id, uint16_t cause){
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auto trap_val = 0x80ULL << 24 | (cause << 16) | trap_id;
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this->template get_reg<uint32_t>(traits::TRAP_STATE) = trap_val;
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this->template get_reg<uint32_t>(traits::NEXT_PC) = std::numeric_limits<uint32_t>::max();
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}
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inline void leave(unsigned lvl){
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this->core.leave_trap(lvl);
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auto pc_val = super::template read_mem<reg_t>(traits::CSR, (lvl << 8) + 0x41);
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this->template get_reg<reg_t>(traits::NEXT_PC) = pc_val;
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}
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inline void wait(unsigned type){
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this->core.wait_until(type);
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}
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template<typename T>
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T& pc_assign(T& val){super::ex_info.branch_taken=true; return val;}
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inline uint8_t readSpace1(typename super::mem_type_e space, uint64_t addr){return super::template read_mem<uint8_t>(space, addr);}
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inline uint16_t readSpace2(typename super::mem_type_e space, uint64_t addr){return super::template read_mem<uint16_t>(space, addr);}
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inline uint32_t readSpace4(typename super::mem_type_e space, uint64_t addr){return super::template read_mem<uint32_t>(space, addr);}
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inline uint64_t readSpace8(typename super::mem_type_e space, uint64_t addr){return super::template read_mem<uint64_t>(space, addr);}
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inline void writeSpace1(typename super::mem_type_e space, uint64_t addr, uint8_t data){super::write_mem(space, addr, data);}
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inline void writeSpace2(typename super::mem_type_e space, uint64_t addr, uint16_t data){super::write_mem(space, addr, data);}
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inline void writeSpace4(typename super::mem_type_e space, uint64_t addr, uint32_t data){super::write_mem(space, addr, data);}
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inline void writeSpace8(typename super::mem_type_e space, uint64_t addr, uint64_t data){super::write_mem(space, addr, data);}
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private:
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/****************************************************************************
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* start opcode definitions
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****************************************************************************/
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struct InstructionDesriptor {
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size_t length;
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uint32_t value;
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uint32_t mask;
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compile_func op;
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};
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const std::array<InstructionDesriptor, ${instructions.size}> instr_descr = {{
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/* entries are: size, valid value, valid mask, function ptr */<%instructions.each{instr -> %>
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/* instruction ${instr.instruction.name} */
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{${instr.length}, ${instr.encoding}, ${instr.mask}, &this_class::__${generator.functionName(instr.name)}},<%}%>
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}};
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/* instruction definitions */<%instructions.eachWithIndex{instr, idx -> %>
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/* instruction ${idx}: ${instr.name} */
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compile_ret_t __${generator.functionName(instr.name)}(virt_addr_t& pc, code_word_t instr){
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// pre execution stuff
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this->do_sync(PRE_SYNC, ${idx});
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<%instr.fields.eachLine{%>${it}
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<%}%>if(this->disass_enabled){
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/* generate console output when executing the command */
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<%instr.disass.eachLine{%>${it}
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<%}%>
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}
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// prepare execution
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uint${addrDataWidth}_t* X = reinterpret_cast<uint${addrDataWidth}_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
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uint${addrDataWidth}_t* PC = reinterpret_cast<uint${addrDataWidth}_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
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uint${addrDataWidth}_t* NEXT_PC = reinterpret_cast<uint${addrDataWidth}_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
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*NEXT_PC = *PC + ${instr.length/8};
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// execute instruction
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<%instr.behavior.eachLine{%>${it}
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<%}%>// post execution stuff
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if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, ${idx});
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auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
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// trap check
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if(*trap_state!=0){
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super::core.enter_trap(*trap_state, pc.val);
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}
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pc.val=*NEXT_PC;
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return pc;
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}
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<%}%>
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/****************************************************************************
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* end opcode definitions
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****************************************************************************/
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compile_ret_t illegal_intruction(virt_addr_t &pc, code_word_t instr) {
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this->do_sync(PRE_SYNC, static_cast<unsigned>(arch::traits<ARCH>::opcode_e::MAX_OPCODE));
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uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
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||||||
|
uint32_t* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
|
||||||
|
*NEXT_PC = *PC + ((instr & 3) == 3 ? 4 : 2);
|
||||||
|
raise(0, 11);
|
||||||
|
// post execution stuff
|
||||||
|
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, static_cast<unsigned>(arch::traits<ARCH>::opcode_e::MAX_OPCODE));
|
||||||
|
auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
|
||||||
|
// trap check
|
||||||
|
if(*trap_state!=0){
|
||||||
|
super::core.enter_trap(*trap_state, pc.val);
|
||||||
|
}
|
||||||
|
pc.val=*NEXT_PC;
|
||||||
|
return pc;
|
||||||
|
}
|
||||||
|
|
||||||
|
static constexpr typename traits::addr_t upper_bits = ~traits::PGMASK;
|
||||||
|
iss::status fetch_ins(virt_addr_t pc, uint8_t * data){
|
||||||
|
auto phys_pc = this->core.v2p(pc);
|
||||||
|
if ((pc.val & upper_bits) != ((pc.val + 2) & upper_bits)) { // we may cross a page boundary
|
||||||
|
if (this->core.read(phys_pc, 2, data) != iss::Ok) return iss::Err;
|
||||||
|
if ((data[0] & 0x3) == 0x3) // this is a 32bit instruction
|
||||||
|
if (this->core.read(this->core.v2p(pc + 2), 2, data + 2) != iss::Ok) return iss::Err;
|
||||||
|
} else {
|
||||||
|
if (this->core.read(phys_pc, 4, data) != iss::Ok) return iss::Err;
|
||||||
|
}
|
||||||
|
return iss::Ok;
|
||||||
|
}
|
||||||
|
};
|
||||||
|
|
||||||
|
template <typename CODE_WORD> void debug_fn(CODE_WORD insn) {
|
||||||
|
volatile CODE_WORD x = insn;
|
||||||
|
insn = 2 * x;
|
||||||
}
|
}
|
||||||
|
|
||||||
${coreDef.name.toLowerCase()}::~${coreDef.name.toLowerCase()}() = default;
|
template <typename ARCH> vm_impl<ARCH>::vm_impl() { this(new ARCH()); }
|
||||||
|
|
||||||
void ${coreDef.name.toLowerCase()}::reset(uint64_t address) {
|
template <typename ARCH>
|
||||||
for(size_t i=0; i<traits<${coreDef.name.toLowerCase()}>::NUM_REGS; ++i) set_reg(i, std::vector<uint8_t>(sizeof(traits<${coreDef.name.toLowerCase()}>::reg_t),0));
|
vm_impl<ARCH>::vm_impl(ARCH &core, unsigned core_id, unsigned cluster_id)
|
||||||
reg.PC=address;
|
: vm_base<ARCH>(core, core_id, cluster_id) {
|
||||||
reg.NEXT_PC=reg.PC;
|
qlut[0] = lut_00.data();
|
||||||
reg.trap_state=0;
|
qlut[1] = lut_01.data();
|
||||||
reg.machine_state=0x3;
|
qlut[2] = lut_10.data();
|
||||||
reg.icount=0;
|
qlut[3] = lut_11.data();
|
||||||
|
for (auto instr : instr_descr) {
|
||||||
|
auto quantrant = instr.value & 0x3;
|
||||||
|
expand_bit_mask(29, lutmasks[quantrant], instr.value >> 2, instr.mask >> 2, 0, qlut[quantrant], instr.op);
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
uint8_t *${coreDef.name.toLowerCase()}::get_regs_base_ptr() {
|
template <typename ARCH>
|
||||||
return reinterpret_cast<uint8_t*>(®);
|
typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(virt_addr_t start, std::function<bool(virt_addr_t&)> pred) {
|
||||||
|
// we fetch at max 4 byte, alignment is 2
|
||||||
|
enum {TRAP_ID=1<<16};
|
||||||
|
code_word_t insn = 0;
|
||||||
|
auto *const data = (uint8_t *)&insn;
|
||||||
|
auto pc=start;
|
||||||
|
while(pred(pc)){
|
||||||
|
auto res = fetch_ins(pc, data);
|
||||||
|
if(res!=iss::Ok){
|
||||||
|
auto new_pc = super::core.enter_trap(TRAP_ID, pc.val);
|
||||||
|
res = fetch_ins(virt_addr_t{access_type::FETCH, new_pc}, data);
|
||||||
|
if(res!=iss::Ok) throw simulation_stopped(0);
|
||||||
|
}
|
||||||
|
auto lut_val = extract_fields(insn);
|
||||||
|
auto f = qlut[insn & 0x3][lut_val];
|
||||||
|
if (!f)
|
||||||
|
f = &this_class::illegal_intruction;
|
||||||
|
pc = (this->*f)(pc, insn);
|
||||||
|
}
|
||||||
|
return pc;
|
||||||
}
|
}
|
||||||
|
|
||||||
${coreDef.name.toLowerCase()}::phys_addr_t ${coreDef.name.toLowerCase()}::virt2phys(const iss::addr_t &pc) {
|
} // namespace mnrv32
|
||||||
return phys_addr_t(pc); // change logical address to physical address
|
|
||||||
}
|
|
||||||
|
|
||||||
|
template <>
|
||||||
|
std::unique_ptr<vm_if> create<arch::${coreDef.name.toLowerCase()}>(arch::${coreDef.name.toLowerCase()} *core, unsigned short port, bool dump) {
|
||||||
|
auto ret = new ${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*core, dump);
|
||||||
|
if (port != 0) debugger::server<debugger::gdb_session>::run_server(ret, port);
|
||||||
|
return std::unique_ptr<vm_if>(ret);
|
||||||
|
}
|
||||||
|
} // namespace interp
|
||||||
|
} // namespace iss
|
||||||
|
|
|
||||||
|
|
@ -1,280 +0,0 @@
|
||||||
/*******************************************************************************
|
|
||||||
* Copyright (C) 2021 MINRES Technologies GmbH
|
|
||||||
* All rights reserved.
|
|
||||||
*
|
|
||||||
* Redistribution and use in source and binary forms, with or without
|
|
||||||
* modification, are permitted provided that the following conditions are met:
|
|
||||||
*
|
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer.
|
|
||||||
*
|
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
*
|
|
||||||
* 3. Neither the name of the copyright holder nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
|
||||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
|
|
||||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
|
||||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
|
||||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
|
||||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
|
||||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
|
||||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
|
||||||
* POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
|
||||||
*******************************************************************************/
|
|
||||||
|
|
||||||
#include "../fp_functions.h"
|
|
||||||
#include <iss/arch/${coreDef.name.toLowerCase()}.h>
|
|
||||||
#include <iss/arch/riscv_hart_m_p.h>
|
|
||||||
#include <iss/debugger/gdb_session.h>
|
|
||||||
#include <iss/debugger/server.h>
|
|
||||||
#include <iss/iss.h>
|
|
||||||
#include <iss/interp/vm_base.h>
|
|
||||||
#include <util/logging.h>
|
|
||||||
#include <sstream>
|
|
||||||
|
|
||||||
#ifndef FMT_HEADER_ONLY
|
|
||||||
#define FMT_HEADER_ONLY
|
|
||||||
#endif
|
|
||||||
#include <fmt/format.h>
|
|
||||||
|
|
||||||
#include <array>
|
|
||||||
#include <iss/debugger/riscv_target_adapter.h>
|
|
||||||
|
|
||||||
namespace iss {
|
|
||||||
namespace interp {
|
|
||||||
namespace ${coreDef.name.toLowerCase()} {
|
|
||||||
using namespace iss::arch;
|
|
||||||
using namespace iss::debugger;
|
|
||||||
|
|
||||||
template <typename ARCH> class vm_impl : public iss::interp::vm_base<ARCH> {
|
|
||||||
public:
|
|
||||||
using traits = arch::traits<ARCH>;
|
|
||||||
using super = typename iss::interp::vm_base<ARCH>;
|
|
||||||
using virt_addr_t = typename super::virt_addr_t;
|
|
||||||
using phys_addr_t = typename super::phys_addr_t;
|
|
||||||
using code_word_t = typename super::code_word_t;
|
|
||||||
using addr_t = typename super::addr_t;
|
|
||||||
using reg_t = typename traits::reg_t;
|
|
||||||
using mem_type_e = typename traits::mem_type_e;
|
|
||||||
|
|
||||||
vm_impl();
|
|
||||||
|
|
||||||
vm_impl(ARCH &core, unsigned core_id = 0, unsigned cluster_id = 0);
|
|
||||||
|
|
||||||
void enableDebug(bool enable) { super::sync_exec = super::ALL_SYNC; }
|
|
||||||
|
|
||||||
target_adapter_if *accquire_target_adapter(server_if *srv) override {
|
|
||||||
debugger_if::dbg_enabled = true;
|
|
||||||
if (super::tgt_adapter == nullptr)
|
|
||||||
super::tgt_adapter = new riscv_target_adapter<ARCH>(srv, this->get_arch());
|
|
||||||
return super::tgt_adapter;
|
|
||||||
}
|
|
||||||
|
|
||||||
protected:
|
|
||||||
using this_class = vm_impl<ARCH>;
|
|
||||||
using compile_ret_t = virt_addr_t;
|
|
||||||
using compile_func = compile_ret_t (this_class::*)(virt_addr_t &pc, code_word_t instr);
|
|
||||||
|
|
||||||
inline const char *name(size_t index){return traits::reg_aliases.at(index);}
|
|
||||||
|
|
||||||
virt_addr_t execute_inst(virt_addr_t start, std::function<bool(void)> pred) override;
|
|
||||||
|
|
||||||
// some compile time constants
|
|
||||||
// enum { MASK16 = 0b1111110001100011, MASK32 = 0b11111111111100000111000001111111 };
|
|
||||||
enum { MASK16 = 0b1111111111111111, MASK32 = 0b11111111111100000111000001111111 };
|
|
||||||
enum { EXTR_MASK16 = MASK16 >> 2, EXTR_MASK32 = MASK32 >> 2 };
|
|
||||||
enum { LUT_SIZE = 1 << util::bit_count(EXTR_MASK32), LUT_SIZE_C = 1 << util::bit_count(EXTR_MASK16) };
|
|
||||||
|
|
||||||
std::array<compile_func, LUT_SIZE> lut;
|
|
||||||
|
|
||||||
std::array<compile_func, LUT_SIZE_C> lut_00, lut_01, lut_10;
|
|
||||||
std::array<compile_func, LUT_SIZE> lut_11;
|
|
||||||
|
|
||||||
std::array<compile_func *, 4> qlut;
|
|
||||||
|
|
||||||
std::array<const uint32_t, 4> lutmasks = {{EXTR_MASK16, EXTR_MASK16, EXTR_MASK16, EXTR_MASK32}};
|
|
||||||
|
|
||||||
void expand_bit_mask(int pos, uint32_t mask, uint32_t value, uint32_t valid, uint32_t idx, compile_func lut[],
|
|
||||||
compile_func f) {
|
|
||||||
if (pos < 0) {
|
|
||||||
lut[idx] = f;
|
|
||||||
} else {
|
|
||||||
auto bitmask = 1UL << pos;
|
|
||||||
if ((mask & bitmask) == 0) {
|
|
||||||
expand_bit_mask(pos - 1, mask, value, valid, idx, lut, f);
|
|
||||||
} else {
|
|
||||||
if ((valid & bitmask) == 0) {
|
|
||||||
expand_bit_mask(pos - 1, mask, value, valid, (idx << 1), lut, f);
|
|
||||||
expand_bit_mask(pos - 1, mask, value, valid, (idx << 1) + 1, lut, f);
|
|
||||||
} else {
|
|
||||||
auto new_val = idx << 1;
|
|
||||||
if ((value & bitmask) != 0) new_val++;
|
|
||||||
expand_bit_mask(pos - 1, mask, value, valid, new_val, lut, f);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
inline uint32_t extract_fields(uint32_t val) { return extract_fields(29, val >> 2, lutmasks[val & 0x3], 0); }
|
|
||||||
|
|
||||||
uint32_t extract_fields(int pos, uint32_t val, uint32_t mask, uint32_t lut_val) {
|
|
||||||
if (pos >= 0) {
|
|
||||||
auto bitmask = 1UL << pos;
|
|
||||||
if ((mask & bitmask) == 0) {
|
|
||||||
lut_val = extract_fields(pos - 1, val, mask, lut_val);
|
|
||||||
} else {
|
|
||||||
auto new_val = lut_val << 1;
|
|
||||||
if ((val & bitmask) != 0) new_val++;
|
|
||||||
lut_val = extract_fields(pos - 1, val, mask, new_val);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
return lut_val;
|
|
||||||
}
|
|
||||||
|
|
||||||
void raise(uint16_t trap_id, uint16_t cause){
|
|
||||||
auto trap_val = 0x80ULL << 24 | (cause << 16) | trap_id;
|
|
||||||
this->template get_reg<uint32_t>(traits::TRAP_STATE) = trap_val;
|
|
||||||
this->template get_reg<uint32_t>(traits::NEXT_PC) = std::numeric_limits<uint32_t>::max();
|
|
||||||
}
|
|
||||||
|
|
||||||
void leave(unsigned lvl){
|
|
||||||
this->core.leave_trap(lvl);
|
|
||||||
auto pc_val = super::template read_mem<reg_t>(traits::CSR, (lvl << 8) + 0x41);
|
|
||||||
this->template get_reg<reg_t>(traits::NEXT_PC) = pc_val;
|
|
||||||
}
|
|
||||||
|
|
||||||
void wait(unsigned type){
|
|
||||||
this->core.wait_until(type);
|
|
||||||
}
|
|
||||||
|
|
||||||
template<typename T>
|
|
||||||
T& pc_assign(T& val){super::ex_info.branch_taken=true; return val;}
|
|
||||||
inline uint8_t readSpace1(typename super::mem_type_e space, uint64_t addr){return super::template read_mem<uint8_t>(space, addr);}
|
|
||||||
inline uint16_t readSpace2(typename super::mem_type_e space, uint64_t addr){return super::template read_mem<uint16_t>(space, addr);}
|
|
||||||
inline uint32_t readSpace4(typename super::mem_type_e space, uint64_t addr){return super::template read_mem<uint32_t>(space, addr);}
|
|
||||||
inline uint64_t readSpace8(typename super::mem_type_e space, uint64_t addr){return super::template read_mem<uint64_t>(space, addr);}
|
|
||||||
inline void writeSpace1(typename super::mem_type_e space, uint64_t addr, uint8_t data){super::write_mem(space, addr, data);}
|
|
||||||
inline void writeSpace2(typename super::mem_type_e space, uint64_t addr, uint16_t data){super::write_mem(space, addr, data);}
|
|
||||||
inline void writeSpace4(typename super::mem_type_e space, uint64_t addr, uint32_t data){super::write_mem(space, addr, data);}
|
|
||||||
inline void writeSpace8(typename super::mem_type_e space, uint64_t addr, uint64_t data){super::write_mem(space, addr, data);}
|
|
||||||
|
|
||||||
private:
|
|
||||||
/****************************************************************************
|
|
||||||
* start opcode definitions
|
|
||||||
****************************************************************************/
|
|
||||||
struct InstructionDesriptor {
|
|
||||||
size_t length;
|
|
||||||
uint32_t value;
|
|
||||||
uint32_t mask;
|
|
||||||
compile_func op;
|
|
||||||
};
|
|
||||||
|
|
||||||
const std::array<InstructionDesriptor, ${instructions.size}> instr_descr = {{
|
|
||||||
/* entries are: size, valid value, valid mask, function ptr */<%instructions.each{instr -> %>
|
|
||||||
/* instruction ${instr.instruction.name} */
|
|
||||||
{${instr.length}, ${instr.encoding}, ${instr.mask}, &this_class::__${generator.functionName(instr.name)}},<%}%>
|
|
||||||
}};
|
|
||||||
|
|
||||||
/* instruction definitions */<%instructions.eachWithIndex{instr, idx -> %>
|
|
||||||
/* instruction ${idx}: ${instr.name} */
|
|
||||||
compile_ret_t __${generator.functionName(instr.name)}(virt_addr_t& pc, code_word_t instr){
|
|
||||||
// pre execution stuff
|
|
||||||
this->do_sync(PRE_SYNC, ${idx});
|
|
||||||
<%instr.fields.eachLine{%>${it}
|
|
||||||
<%}%>if(this->disass_enabled){
|
|
||||||
/* generate console output when executing the command */
|
|
||||||
<%instr.disass.eachLine{%>${it}
|
|
||||||
<%}%>
|
|
||||||
}
|
|
||||||
// prepare execution
|
|
||||||
uint${addrDataWidth}_t* X = reinterpret_cast<uint${addrDataWidth}_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
|
|
||||||
uint${addrDataWidth}_t* PC = reinterpret_cast<uint${addrDataWidth}_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
|
|
||||||
uint${addrDataWidth}_t* NEXT_PC = reinterpret_cast<uint${addrDataWidth}_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
|
|
||||||
*NEXT_PC = *PC + ${instr.length/8};
|
|
||||||
// execute instruction
|
|
||||||
<%instr.behavior.eachLine{%>${it}
|
|
||||||
<%}%>// post execution stuff
|
|
||||||
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, ${idx});
|
|
||||||
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
|
|
||||||
// trap check
|
|
||||||
if(trap_state!=0){
|
|
||||||
super::core.enter_trap(trap_state, pc.val);
|
|
||||||
}
|
|
||||||
pc.val=super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC);
|
|
||||||
return pc;
|
|
||||||
}
|
|
||||||
<%}%>
|
|
||||||
/****************************************************************************
|
|
||||||
* end opcode definitions
|
|
||||||
****************************************************************************/
|
|
||||||
compile_ret_t illegal_intruction(virt_addr_t &pc, code_word_t instr) {
|
|
||||||
pc = pc + ((instr & 3) == 3 ? 4 : 2);
|
|
||||||
return pc;
|
|
||||||
}
|
|
||||||
};
|
|
||||||
|
|
||||||
template <typename CODE_WORD> void debug_fn(CODE_WORD insn) {
|
|
||||||
volatile CODE_WORD x = insn;
|
|
||||||
insn = 2 * x;
|
|
||||||
}
|
|
||||||
|
|
||||||
template <typename ARCH> vm_impl<ARCH>::vm_impl() { this(new ARCH()); }
|
|
||||||
|
|
||||||
template <typename ARCH>
|
|
||||||
vm_impl<ARCH>::vm_impl(ARCH &core, unsigned core_id, unsigned cluster_id)
|
|
||||||
: vm_base<ARCH>(core, core_id, cluster_id) {
|
|
||||||
qlut[0] = lut_00.data();
|
|
||||||
qlut[1] = lut_01.data();
|
|
||||||
qlut[2] = lut_10.data();
|
|
||||||
qlut[3] = lut_11.data();
|
|
||||||
for (auto instr : instr_descr) {
|
|
||||||
auto quantrant = instr.value & 0x3;
|
|
||||||
expand_bit_mask(29, lutmasks[quantrant], instr.value >> 2, instr.mask >> 2, 0, qlut[quantrant], instr.op);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
template <typename ARCH>
|
|
||||||
typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(virt_addr_t start, std::function<bool(void)> pred) {
|
|
||||||
// we fetch at max 4 byte, alignment is 2
|
|
||||||
enum {TRAP_ID=1<<16};
|
|
||||||
const typename traits::addr_t upper_bits = ~traits::PGMASK;
|
|
||||||
code_word_t insn = 0;
|
|
||||||
auto *const data = (uint8_t *)&insn;
|
|
||||||
auto pc=start;
|
|
||||||
while(pred){
|
|
||||||
auto paddr = this->core.v2p(pc);
|
|
||||||
if ((pc.val & upper_bits) != ((pc.val + 2) & upper_bits)) { // we may cross a page boundary
|
|
||||||
if (this->core.read(paddr, 2, data) != iss::Ok) throw trap_access(TRAP_ID, pc.val);
|
|
||||||
if ((insn & 0x3) == 0x3) // this is a 32bit instruction
|
|
||||||
if (this->core.read(this->core.v2p(pc + 2), 2, data + 2) != iss::Ok) throw trap_access(TRAP_ID, pc.val);
|
|
||||||
} else {
|
|
||||||
if (this->core.read(paddr, 4, data) != iss::Ok) throw trap_access(TRAP_ID, pc.val);
|
|
||||||
}
|
|
||||||
if (insn == 0x0000006f || (insn&0xffff)==0xa001) throw simulation_stopped(0); // 'J 0' or 'C.J 0'
|
|
||||||
auto lut_val = extract_fields(insn);
|
|
||||||
auto f = qlut[insn & 0x3][lut_val];
|
|
||||||
if (!f)
|
|
||||||
f = &this_class::illegal_intruction;
|
|
||||||
pc = (this->*f)(pc, insn);
|
|
||||||
}
|
|
||||||
return pc;
|
|
||||||
}
|
|
||||||
|
|
||||||
} // namespace mnrv32
|
|
||||||
|
|
||||||
template <>
|
|
||||||
std::unique_ptr<vm_if> create<arch::${coreDef.name.toLowerCase()}>(arch::${coreDef.name.toLowerCase()} *core, unsigned short port, bool dump) {
|
|
||||||
auto ret = new ${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*core, dump);
|
|
||||||
if (port != 0) debugger::server<debugger::gdb_session>::run_server(ret, port);
|
|
||||||
return std::unique_ptr<vm_if>(ret);
|
|
||||||
}
|
|
||||||
} // namespace interp
|
|
||||||
} // namespace iss
|
|
||||||
|
|
@ -354,6 +354,10 @@ public:
|
||||||
mem_write_cb = memWriteCb;
|
mem_write_cb = memWriteCb;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
void set_csr(unsigned addr, reg_t val){
|
||||||
|
csr[addr & csr.page_addr_mask] = val;
|
||||||
|
}
|
||||||
|
|
||||||
protected:
|
protected:
|
||||||
struct riscv_instrumentation_if : public iss::instrumentation_if {
|
struct riscv_instrumentation_if : public iss::instrumentation_if {
|
||||||
|
|
||||||
|
|
@ -405,6 +409,8 @@ protected:
|
||||||
std::unordered_map<unsigned, wr_csr_f> csr_wr_cb;
|
std::unordered_map<unsigned, wr_csr_f> csr_wr_cb;
|
||||||
|
|
||||||
private:
|
private:
|
||||||
|
iss::status read_reg(unsigned addr, reg_t &val);
|
||||||
|
iss::status write_reg(unsigned addr, reg_t val);
|
||||||
iss::status read_cycle(unsigned addr, reg_t &val);
|
iss::status read_cycle(unsigned addr, reg_t &val);
|
||||||
iss::status read_time(unsigned addr, reg_t &val);
|
iss::status read_time(unsigned addr, reg_t &val);
|
||||||
iss::status read_status(unsigned addr, reg_t &val);
|
iss::status read_status(unsigned addr, reg_t &val);
|
||||||
|
|
@ -450,6 +456,12 @@ riscv_hart_m_p<BASE>::riscv_hart_m_p()
|
||||||
csr_rd_cb[mie] = &riscv_hart_m_p<BASE>::read_ie;
|
csr_rd_cb[mie] = &riscv_hart_m_p<BASE>::read_ie;
|
||||||
csr_wr_cb[mie] = &riscv_hart_m_p<BASE>::write_ie;
|
csr_wr_cb[mie] = &riscv_hart_m_p<BASE>::write_ie;
|
||||||
csr_rd_cb[mhartid] = &riscv_hart_m_p<BASE>::read_hartid;
|
csr_rd_cb[mhartid] = &riscv_hart_m_p<BASE>::read_hartid;
|
||||||
|
// common regs
|
||||||
|
const std::array<unsigned, 6> addrs{{mepc, mtvec, mscratch, mcause, mtval, mscratch}};
|
||||||
|
for(auto addr: addrs) {
|
||||||
|
csr_rd_cb[addr] = &riscv_hart_m_p<BASE>::read_reg;
|
||||||
|
csr_wr_cb[addr] = &riscv_hart_m_p<BASE>::write_reg;
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
template <typename BASE> std::pair<uint64_t, bool> riscv_hart_m_p<BASE>::load_file(std::string name, int type) {
|
template <typename BASE> std::pair<uint64_t, bool> riscv_hart_m_p<BASE>::load_file(std::string name, int type) {
|
||||||
|
|
@ -664,32 +676,35 @@ iss::status riscv_hart_m_p<BASE>::write(const address_type type, const access_ty
|
||||||
template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_csr(unsigned addr, reg_t &val) {
|
template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_csr(unsigned addr, reg_t &val) {
|
||||||
if (addr >= csr.size()) return iss::Err;
|
if (addr >= csr.size()) return iss::Err;
|
||||||
auto req_priv_lvl = (addr >> 8) & 0x3;
|
auto req_priv_lvl = (addr >> 8) & 0x3;
|
||||||
if (this->reg.PRIV < req_priv_lvl) throw illegal_instruction_fault(this->fault_data);
|
if (this->reg.PRIV < req_priv_lvl) // not having required privileges
|
||||||
|
throw illegal_instruction_fault(this->fault_data);
|
||||||
auto it = csr_rd_cb.find(addr);
|
auto it = csr_rd_cb.find(addr);
|
||||||
if (it == csr_rd_cb.end()) {
|
if (it == csr_rd_cb.end() || !it->second) // non existent register
|
||||||
val = csr[addr & csr.page_addr_mask];
|
throw illegal_instruction_fault(this->fault_data);
|
||||||
return iss::Ok;
|
return (this->*(it->second))(addr, val);
|
||||||
}
|
|
||||||
rd_csr_f f = it->second;
|
|
||||||
if (f == nullptr) throw illegal_instruction_fault(this->fault_data);
|
|
||||||
return (this->*f)(addr, val);
|
|
||||||
}
|
}
|
||||||
|
|
||||||
template <typename BASE> iss::status riscv_hart_m_p<BASE>::write_csr(unsigned addr, reg_t val) {
|
template <typename BASE> iss::status riscv_hart_m_p<BASE>::write_csr(unsigned addr, reg_t val) {
|
||||||
if (addr >= csr.size()) return iss::Err;
|
if (addr >= csr.size()) return iss::Err;
|
||||||
auto req_priv_lvl = (addr >> 8) & 0x3;
|
auto req_priv_lvl = (addr >> 8) & 0x3;
|
||||||
if (this->reg.PRIV < req_priv_lvl)
|
if (this->reg.PRIV < req_priv_lvl) // not having required privileges
|
||||||
throw illegal_instruction_fault(this->fault_data);
|
throw illegal_instruction_fault(this->fault_data);
|
||||||
if((addr&0xc00)==0xc00)
|
if((addr&0xc00)==0xc00) // writing to read-only region
|
||||||
throw illegal_instruction_fault(this->fault_data);
|
throw illegal_instruction_fault(this->fault_data);
|
||||||
auto it = csr_wr_cb.find(addr);
|
auto it = csr_wr_cb.find(addr);
|
||||||
if (it == csr_wr_cb.end()) {
|
if (it == csr_wr_cb.end() || !it->second) // non existent register
|
||||||
csr[addr & csr.page_addr_mask] = val;
|
throw illegal_instruction_fault(this->fault_data);
|
||||||
|
return (this->*(it->second))(addr, val);
|
||||||
|
}
|
||||||
|
|
||||||
|
template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_reg(unsigned addr, reg_t &val) {
|
||||||
|
val = csr[addr];
|
||||||
|
return iss::Ok;
|
||||||
|
}
|
||||||
|
|
||||||
|
template <typename BASE> iss::status riscv_hart_m_p<BASE>::write_reg(unsigned addr, reg_t val) {
|
||||||
|
csr[addr] = val;
|
||||||
return iss::Ok;
|
return iss::Ok;
|
||||||
}
|
|
||||||
wr_csr_f f = it->second;
|
|
||||||
if (f == nullptr) throw illegal_instruction_fault(this->fault_data);
|
|
||||||
return (this->*f)(addr, val);
|
|
||||||
}
|
}
|
||||||
|
|
||||||
template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_cycle(unsigned addr, reg_t &val) {
|
template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_cycle(unsigned addr, reg_t &val) {
|
||||||
|
|
@ -931,6 +946,7 @@ template <typename BASE> uint64_t riscv_hart_m_p<BASE>::enter_trap(uint64_t flag
|
||||||
}
|
}
|
||||||
|
|
||||||
template <typename BASE> uint64_t riscv_hart_m_p<BASE>::leave_trap(uint64_t flags) {
|
template <typename BASE> uint64_t riscv_hart_m_p<BASE>::leave_trap(uint64_t flags) {
|
||||||
|
/* TODO: configurable support of User mode
|
||||||
auto cur_priv = this->reg.PRIV;
|
auto cur_priv = this->reg.PRIV;
|
||||||
auto inst_priv = flags & 0x3;
|
auto inst_priv = flags & 0x3;
|
||||||
auto status = state.mstatus;
|
auto status = state.mstatus;
|
||||||
|
|
@ -943,8 +959,7 @@ template <typename BASE> uint64_t riscv_hart_m_p<BASE>::leave_trap(uint64_t flag
|
||||||
state.mstatus.MIE = state.mstatus.MPIE;
|
state.mstatus.MIE = state.mstatus.MPIE;
|
||||||
} else {
|
} else {
|
||||||
CLOG(ERROR, disass) << "Unsupported mode:" << inst_priv;
|
CLOG(ERROR, disass) << "Unsupported mode:" << inst_priv;
|
||||||
}
|
}*/
|
||||||
|
|
||||||
// sets the pc to the value stored in the x epc register.
|
// sets the pc to the value stored in the x epc register.
|
||||||
this->reg.NEXT_PC = csr[mepc];
|
this->reg.NEXT_PC = csr[mepc];
|
||||||
CLOG(INFO, disass) << "Executing xRET";
|
CLOG(INFO, disass) << "Executing xRET";
|
||||||
|
|
|
||||||
|
|
@ -53,7 +53,7 @@ template <> struct traits<tgf_c> {
|
||||||
static constexpr std::array<const char*, 35> reg_aliases{
|
static constexpr std::array<const char*, 35> reg_aliases{
|
||||||
{"X0", "X1", "X2", "X3", "X4", "X5", "X6", "X7", "X8", "X9", "X10", "X11", "X12", "X13", "X14", "X15", "X16", "X17", "X18", "X19", "X20", "X21", "X22", "X23", "X24", "X25", "X26", "X27", "X28", "X29", "X30", "X31", "PC", "NEXT_PC", "PRIV"}};
|
{"X0", "X1", "X2", "X3", "X4", "X5", "X6", "X7", "X8", "X9", "X10", "X11", "X12", "X13", "X14", "X15", "X16", "X17", "X18", "X19", "X20", "X21", "X22", "X23", "X24", "X25", "X26", "X27", "X28", "X29", "X30", "X31", "PC", "NEXT_PC", "PRIV"}};
|
||||||
|
|
||||||
enum constants {XLEN=32, PCLEN=32, MISA_VAL=0b1000000000000000001000100000100, PGSIZE=0x1000, PGMASK=0b111111111111, CSR_SIZE=4096, fence=0, fencei=1, fencevmal=2, fencevmau=3, MUL_LEN=64};
|
enum constants {XLEN=32, PCLEN=32, MISA_VAL=0b01000000000000000001000100000100, PGSIZE=0x1000, PGMASK=0b111111111111, CSR_SIZE=4096, fence=0, fencei=1, fencevmal=2, fencevmau=3, eei_aligned_addresses=1, MUL_LEN=64};
|
||||||
|
|
||||||
constexpr static unsigned FP_REGS_SIZE = 0;
|
constexpr static unsigned FP_REGS_SIZE = 0;
|
||||||
|
|
||||||
|
|
@ -78,8 +78,7 @@ template <> struct traits<tgf_c> {
|
||||||
{32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,8,32,32,64}};
|
{32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,8,32,32,64}};
|
||||||
|
|
||||||
static constexpr std::array<const uint32_t, 38> reg_byte_offsets{
|
static constexpr std::array<const uint32_t, 38> reg_byte_offsets{
|
||||||
{0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,
|
{0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,137,141,145}};
|
||||||
128,132,136,137,141,145}};
|
|
||||||
|
|
||||||
static const uint64_t addr_mask = (reg_t(1) << (XLEN - 1)) | ((reg_t(1) << (XLEN - 1)) - 1);
|
static const uint64_t addr_mask = (reg_t(1) << (XLEN - 1)) | ((reg_t(1) << (XLEN - 1)) - 1);
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -85,7 +85,7 @@ protected:
|
||||||
|
|
||||||
inline const char *name(size_t index){return traits::reg_aliases.at(index);}
|
inline const char *name(size_t index){return traits::reg_aliases.at(index);}
|
||||||
|
|
||||||
virt_addr_t execute_inst(virt_addr_t start, std::function<bool(void)> pred) override;
|
virt_addr_t execute_inst(virt_addr_t start, std::function<bool(virt_addr_t&)> pred) override;
|
||||||
|
|
||||||
// some compile time constants
|
// some compile time constants
|
||||||
// enum { MASK16 = 0b1111110001100011, MASK32 = 0b11111111111100000111000001111111 };
|
// enum { MASK16 = 0b1111110001100011, MASK32 = 0b11111111111100000111000001111111 };
|
||||||
|
|
@ -2055,14 +2055,14 @@ vm_impl<ARCH>::vm_impl(ARCH &core, unsigned core_id, unsigned cluster_id)
|
||||||
}
|
}
|
||||||
|
|
||||||
template <typename ARCH>
|
template <typename ARCH>
|
||||||
typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(virt_addr_t start, std::function<bool(void)> pred) {
|
typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(virt_addr_t start, std::function<bool(virt_addr_t&)> pred) {
|
||||||
// we fetch at max 4 byte, alignment is 2
|
// we fetch at max 4 byte, alignment is 2
|
||||||
enum {TRAP_ID=1<<16};
|
enum {TRAP_ID=1<<16};
|
||||||
const typename traits::addr_t upper_bits = ~traits::PGMASK;
|
const typename traits::addr_t upper_bits = ~traits::PGMASK;
|
||||||
code_word_t insn = 0;
|
code_word_t insn = 0;
|
||||||
auto *const data = (uint8_t *)&insn;
|
auto *const data = (uint8_t *)&insn;
|
||||||
auto pc=start;
|
auto pc=start;
|
||||||
while(pred){
|
while(pred(pc)){
|
||||||
auto paddr = this->core.v2p(pc);
|
auto paddr = this->core.v2p(pc);
|
||||||
if ((pc.val & upper_bits) != ((pc.val + 2) & upper_bits)) { // we may cross a page boundary
|
if ((pc.val & upper_bits) != ((pc.val + 2) & upper_bits)) { // we may cross a page boundary
|
||||||
if (this->core.read(paddr, 2, data) != iss::Ok) throw trap_access(TRAP_ID, pc.val);
|
if (this->core.read(paddr, 2, data) != iss::Ok) throw trap_access(TRAP_ID, pc.val);
|
||||||
|
|
|
||||||
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue