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fix desscriptions to conform to ISA spec version 20191213 and TGF-C

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This commit is contained in:
Eyck Jentzsch
2021-03-07 10:51:00 +00:00
parent dae8acb8a3
commit c251fe15d5
9 changed files with 905 additions and 815 deletions
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53
incl/iss/arch/riscv_hart_m_p.h
View File

@ -354,6 +354,10 @@ public:
mem_write_cb = memWriteCb;
}
void set_csr(unsigned addr, reg_t val){
csr[addr & csr.page_addr_mask] = val;
}
protected:
struct riscv_instrumentation_if : public iss::instrumentation_if {
@ -405,6 +409,8 @@ protected:
std::unordered_map<unsigned, wr_csr_f> csr_wr_cb;
private:
iss::status read_reg(unsigned addr, reg_t &val);
iss::status write_reg(unsigned addr, reg_t val);
iss::status read_cycle(unsigned addr, reg_t &val);
iss::status read_time(unsigned addr, reg_t &val);
iss::status read_status(unsigned addr, reg_t &val);
@ -450,6 +456,12 @@ riscv_hart_m_p<BASE>::riscv_hart_m_p()
csr_rd_cb[mie] = &riscv_hart_m_p<BASE>::read_ie;
csr_wr_cb[mie] = &riscv_hart_m_p<BASE>::write_ie;
csr_rd_cb[mhartid] = &riscv_hart_m_p<BASE>::read_hartid;
// common regs
const std::array<unsigned, 6> addrs{{mepc, mtvec, mscratch, mcause, mtval, mscratch}};
for(auto addr: addrs) {
csr_rd_cb[addr] = &riscv_hart_m_p<BASE>::read_reg;
csr_wr_cb[addr] = &riscv_hart_m_p<BASE>::write_reg;
}
}
template <typename BASE> std::pair<uint64_t, bool> riscv_hart_m_p<BASE>::load_file(std::string name, int type) {
@ -664,32 +676,35 @@ iss::status riscv_hart_m_p<BASE>::write(const address_type type, const access_ty
template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_csr(unsigned addr, reg_t &val) {
if (addr >= csr.size()) return iss::Err;
auto req_priv_lvl = (addr >> 8) & 0x3;
if (this->reg.PRIV < req_priv_lvl) throw illegal_instruction_fault(this->fault_data);
if (this->reg.PRIV < req_priv_lvl) // not having required privileges
throw illegal_instruction_fault(this->fault_data);
auto it = csr_rd_cb.find(addr);
if (it == csr_rd_cb.end()) {
val = csr[addr & csr.page_addr_mask];
return iss::Ok;
}
rd_csr_f f = it->second;
if (f == nullptr) throw illegal_instruction_fault(this->fault_data);
return (this->*f)(addr, val);
if (it == csr_rd_cb.end() || !it->second) // non existent register
throw illegal_instruction_fault(this->fault_data);
return (this->*(it->second))(addr, val);
}
template <typename BASE> iss::status riscv_hart_m_p<BASE>::write_csr(unsigned addr, reg_t val) {
if (addr >= csr.size()) return iss::Err;
auto req_priv_lvl = (addr >> 8) & 0x3;
if (this->reg.PRIV < req_priv_lvl)
if (this->reg.PRIV < req_priv_lvl) // not having required privileges
throw illegal_instruction_fault(this->fault_data);
if((addr&0xc00)==0xc00)
if((addr&0xc00)==0xc00) // writing to read-only region
throw illegal_instruction_fault(this->fault_data);
auto it = csr_wr_cb.find(addr);
if (it == csr_wr_cb.end()) {
csr[addr & csr.page_addr_mask] = val;
return iss::Ok;
}
wr_csr_f f = it->second;
if (f == nullptr) throw illegal_instruction_fault(this->fault_data);
return (this->*f)(addr, val);
if (it == csr_wr_cb.end() || !it->second) // non existent register
throw illegal_instruction_fault(this->fault_data);
return (this->*(it->second))(addr, val);
}
template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_reg(unsigned addr, reg_t &val) {
val = csr[addr];
return iss::Ok;
}
template <typename BASE> iss::status riscv_hart_m_p<BASE>::write_reg(unsigned addr, reg_t val) {
csr[addr] = val;
return iss::Ok;
}
template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_cycle(unsigned addr, reg_t &val) {
@ -931,6 +946,7 @@ template <typename BASE> uint64_t riscv_hart_m_p<BASE>::enter_trap(uint64_t flag
}
template <typename BASE> uint64_t riscv_hart_m_p<BASE>::leave_trap(uint64_t flags) {
/* TODO: configurable support of User mode
auto cur_priv = this->reg.PRIV;
auto inst_priv = flags & 0x3;
auto status = state.mstatus;
@ -943,8 +959,7 @@ template <typename BASE> uint64_t riscv_hart_m_p<BASE>::leave_trap(uint64_t flag
state.mstatus.MIE = state.mstatus.MPIE;
} else {
CLOG(ERROR, disass) << "Unsupported mode:" << inst_priv;
}
}*/
// sets the pc to the value stored in the x epc register.
this->reg.NEXT_PC = csr[mepc];
CLOG(INFO, disass) << "Executing xRET";

5
incl/iss/arch/tgf_c.h
View File

@ -53,7 +53,7 @@ template <> struct traits<tgf_c> {
static constexpr std::array<const char*, 35> reg_aliases{
{"X0", "X1", "X2", "X3", "X4", "X5", "X6", "X7", "X8", "X9", "X10", "X11", "X12", "X13", "X14", "X15", "X16", "X17", "X18", "X19", "X20", "X21", "X22", "X23", "X24", "X25", "X26", "X27", "X28", "X29", "X30", "X31", "PC", "NEXT_PC", "PRIV"}};
enum constants {XLEN=32, PCLEN=32, MISA_VAL=0b1000000000000000001000100000100, PGSIZE=0x1000, PGMASK=0b111111111111, CSR_SIZE=4096, fence=0, fencei=1, fencevmal=2, fencevmau=3, MUL_LEN=64};
enum constants {XLEN=32, PCLEN=32, MISA_VAL=0b01000000000000000001000100000100, PGSIZE=0x1000, PGMASK=0b111111111111, CSR_SIZE=4096, fence=0, fencei=1, fencevmal=2, fencevmau=3, eei_aligned_addresses=1, MUL_LEN=64};
constexpr static unsigned FP_REGS_SIZE = 0;
@ -78,8 +78,7 @@ template <> struct traits<tgf_c> {
{32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,8,32,32,64}};
static constexpr std::array<const uint32_t, 38> reg_byte_offsets{
{0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,
128,132,136,137,141,145}};
{0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,137,141,145}};
static const uint64_t addr_mask = (reg_t(1) << (XLEN - 1)) | ((reg_t(1) << (XLEN - 1)) - 1);