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fix for #2

This commit is contained in:
Eyck Jentzsch 2021-07-28 09:09:08 +02:00
parent 4ddf50162c
commit af887c286f
3 changed files with 30 additions and 1 deletions
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7
incl/iss/arch/riscv_hart_m_p.h
View File

@ -284,6 +284,7 @@ private:
iss::status read_time(unsigned addr, reg_t &val); iss::status read_time(unsigned addr, reg_t &val);
iss::status read_status(unsigned addr, reg_t &val); iss::status read_status(unsigned addr, reg_t &val);
iss::status write_status(unsigned addr, reg_t val); iss::status write_status(unsigned addr, reg_t val);
iss::status write_cause(unsigned addr, reg_t val);
iss::status read_ie(unsigned addr, reg_t &val); iss::status read_ie(unsigned addr, reg_t &val);
iss::status write_ie(unsigned addr, reg_t val); iss::status write_ie(unsigned addr, reg_t val);
iss::status read_ip(unsigned addr, reg_t &val); iss::status read_ip(unsigned addr, reg_t &val);
@ -353,6 +354,7 @@ riscv_hart_m_p<BASE>::riscv_hart_m_p()
csr_wr_cb[minstreth] = &this_class::write_instret; csr_wr_cb[minstreth] = &this_class::write_instret;
csr_rd_cb[mstatus] = &this_class::read_status; csr_rd_cb[mstatus] = &this_class::read_status;
csr_wr_cb[mstatus] = &this_class::write_status; csr_wr_cb[mstatus] = &this_class::write_status;
csr_wr_cb[mcause] = &this_class::write_cause;
csr_rd_cb[mip] = &this_class::read_ip; csr_rd_cb[mip] = &this_class::read_ip;
csr_wr_cb[mip] = &this_class::write_ip; csr_wr_cb[mip] = &this_class::write_ip;
csr_rd_cb[mie] = &this_class::read_ie; csr_rd_cb[mie] = &this_class::read_ie;
@ -716,6 +718,11 @@ template <typename BASE> iss::status riscv_hart_m_p<BASE>::write_status(unsigned
return iss::Ok; return iss::Ok;
} }
template <typename BASE> iss::status riscv_hart_m_p<BASE>::write_cause(unsigned addr, reg_t val) {
csr[mcause] = val & ((1UL<<(traits<BASE>::XLEN-1))|0xf); //TODO: make exception code size configurable
return iss::Ok;
}
template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_ie(unsigned addr, reg_t &val) { template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_ie(unsigned addr, reg_t &val) {
val = csr[mie]; val = csr[mie];
return iss::Ok; return iss::Ok;

16
incl/iss/arch/riscv_hart_msu_vp.h
View File

@ -392,6 +392,7 @@ private:
iss::status read_time(unsigned addr, reg_t &val); iss::status read_time(unsigned addr, reg_t &val);
iss::status read_status(unsigned addr, reg_t &val); iss::status read_status(unsigned addr, reg_t &val);
iss::status write_status(unsigned addr, reg_t val); iss::status write_status(unsigned addr, reg_t val);
iss::status write_cause(unsigned addr, reg_t val);
iss::status read_ie(unsigned addr, reg_t &val); iss::status read_ie(unsigned addr, reg_t &val);
iss::status write_ie(unsigned addr, reg_t val); iss::status write_ie(unsigned addr, reg_t val);
iss::status read_ip(unsigned addr, reg_t &val); iss::status read_ip(unsigned addr, reg_t &val);
@ -442,7 +443,12 @@ riscv_hart_msu_vp<BASE>::riscv_hart_msu_vp()
//csr_wr_cb[addr] = &this_class::write_reg; //csr_wr_cb[addr] = &this_class::write_reg;
} }
// common regs // common regs
const std::array<unsigned, 10> addrs{{misa, mvendorid, marchid, mimpid, mepc, mtvec, mscratch, mcause, mtval, mscratch}}; const std::array<unsigned, 22> addrs{{
misa, mvendorid, marchid, mimpid,
mepc, mtvec, mscratch, mcause, mtval, mscratch,
sepc, stvec, sscratch, scause, stval, sscratch,
uepc, utvec, uscratch, ucause, utval, uscratch
}};
for(auto addr: addrs) { for(auto addr: addrs) {
csr_rd_cb[addr] = &this_class::read_reg; csr_rd_cb[addr] = &this_class::read_reg;
csr_wr_cb[addr] = &this_class::write_reg; csr_wr_cb[addr] = &this_class::write_reg;
@ -465,10 +471,13 @@ riscv_hart_msu_vp<BASE>::riscv_hart_msu_vp()
csr_wr_cb[minstreth] = &this_class::write_instret; csr_wr_cb[minstreth] = &this_class::write_instret;
csr_rd_cb[mstatus] = &this_class::read_status; csr_rd_cb[mstatus] = &this_class::read_status;
csr_wr_cb[mstatus] = &this_class::write_status; csr_wr_cb[mstatus] = &this_class::write_status;
csr_wr_cb[mcause] = &this_class::write_cause;
csr_rd_cb[sstatus] = &this_class::read_status; csr_rd_cb[sstatus] = &this_class::read_status;
csr_wr_cb[sstatus] = &this_class::write_status; csr_wr_cb[sstatus] = &this_class::write_status;
csr_wr_cb[scause] = &this_class::write_cause;
csr_rd_cb[ustatus] = &this_class::read_status; csr_rd_cb[ustatus] = &this_class::read_status;
csr_wr_cb[ustatus] = &this_class::write_status; csr_wr_cb[ustatus] = &this_class::write_status;
csr_wr_cb[ucause] = &this_class::write_cause;
csr_rd_cb[mip] = &this_class::read_ip; csr_rd_cb[mip] = &this_class::read_ip;
csr_wr_cb[mip] = &this_class::write_ip; csr_wr_cb[mip] = &this_class::write_ip;
csr_rd_cb[sip] = &this_class::read_ip; csr_rd_cb[sip] = &this_class::read_ip;
@ -878,6 +887,11 @@ template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::write_status(unsig
return iss::Ok; return iss::Ok;
} }
template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::write_cause(unsigned addr, reg_t val) {
csr[addr] = val & ((1UL<<(traits<BASE>::XLEN-1))|0xf); //TODO: make exception code size configurable
return iss::Ok;
}
template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::read_ie(unsigned addr, reg_t &val) { template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::read_ie(unsigned addr, reg_t &val) {
val = csr[mie]; val = csr[mie];
if (addr < mie) val &= csr[mideleg]; if (addr < mie) val &= csr[mideleg];

8
incl/iss/arch/riscv_hart_mu_p.h
View File

@ -301,6 +301,7 @@ private:
iss::status read_time(unsigned addr, reg_t &val); iss::status read_time(unsigned addr, reg_t &val);
iss::status read_status(unsigned addr, reg_t &val); iss::status read_status(unsigned addr, reg_t &val);
iss::status write_status(unsigned addr, reg_t val); iss::status write_status(unsigned addr, reg_t val);
iss::status write_cause(unsigned addr, reg_t val);
iss::status read_ie(unsigned addr, reg_t &val); iss::status read_ie(unsigned addr, reg_t &val);
iss::status write_ie(unsigned addr, reg_t val); iss::status write_ie(unsigned addr, reg_t val);
iss::status read_ip(unsigned addr, reg_t &val); iss::status read_ip(unsigned addr, reg_t &val);
@ -370,8 +371,10 @@ riscv_hart_mu_p<BASE, FEAT>::riscv_hart_mu_p()
csr_wr_cb[minstreth] = &this_class::write_instret; csr_wr_cb[minstreth] = &this_class::write_instret;
csr_rd_cb[mstatus] = &this_class::read_status; csr_rd_cb[mstatus] = &this_class::read_status;
csr_wr_cb[mstatus] = &this_class::write_status; csr_wr_cb[mstatus] = &this_class::write_status;
csr_wr_cb[mcause] = &this_class::write_cause;
csr_rd_cb[ustatus] = &this_class::read_status; csr_rd_cb[ustatus] = &this_class::read_status;
csr_wr_cb[ustatus] = &this_class::write_status; csr_wr_cb[ustatus] = &this_class::write_status;
csr_wr_cb[ucause] = &this_class::write_cause;
csr_rd_cb[mip] = &this_class::read_ip; csr_rd_cb[mip] = &this_class::read_ip;
csr_wr_cb[mip] = &this_class::write_ip; csr_wr_cb[mip] = &this_class::write_ip;
csr_rd_cb[uip] = &this_class::read_ip; csr_rd_cb[uip] = &this_class::read_ip;
@ -773,6 +776,11 @@ template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT
return iss::Ok; return iss::Ok;
} }
template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT>::write_cause(unsigned addr, reg_t val) {
csr[addr] = val & ((1UL<<(traits<BASE>::XLEN-1))|0xf); //TODO: make exception code size configurable
return iss::Ok;
}
template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT>::read_ie(unsigned addr, reg_t &val) { template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT>::read_ie(unsigned addr, reg_t &val) {
val = csr[mie]; val = csr[mie];
val &= csr[mideleg]; val &= csr[mideleg];