[WIP] basic infrastructure working

2020-04-13 17:03:50 +02:00
parent 8cdf50d69e
commit ae1c0b99fe
3 changed files with 2550 additions and 109 deletions
--- a/gen_input/RVC.core_desc
+++ b/gen_input/RVC.core_desc
@ -164,7 +164,7 @@ InsructionSet RV32IC extends RISCVBase{
            val offs[XLEN] <= X[2] + uimm;
            MEM[offs]{32} <= X[rs2];
        }
-        DII {
+        DII(no_cont) { // Defined Illegal Instruction
            encoding:b000 | b0 | b00000 | b00000 | b00;
            raise(0, 2);
        }