first version of tgf_c based on CoreDSL 2.0
This commit is contained in:
parent
d43b35949e
commit
ab554539e3
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@ -1 +1 @@
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Subproject commit 3bb3763e9277642333b42f0f5bd4bd15c1546bb7
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Subproject commit 378618192944debf5a5dee759aa1a517aec0941b
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@ -4,25 +4,25 @@ import "CoreDSL-Instruction-Set-Description/RVC.core_desc"
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Core TGF_B provides RV32I {
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constants {
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XLEN:=32;
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PCLEN:=32;
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unsigned XLEN=32;
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unsigned PCLEN=32;
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// definitions for the architecture wrapper
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// XL ZYXWVUTSRQPONMLKJIHGFEDCBA
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MISA_VAL:=0b01000000000000000000000100000000;
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PGSIZE := 0x1000; //1 << 12;
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PGMASK := 0xfff; //PGSIZE-1
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unsigned MISA_VAL=0b01000000000000000000000100000000;
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unsigned PGSIZE = 0x1000; //1 << 12;
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unsigned PGMASK = 0xfff; //PGSIZE-1
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}
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}
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Core TGF_C provides RV32I, RV32M, RV32IC {
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constants {
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XLEN:=32;
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PCLEN:=32;
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MUL_LEN:=64;
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unsigned XLEN=32;
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unsigned PCLEN=32;
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unsigned MUL_LEN=64;
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// definitions for the architecture wrapper
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// XL ZYXWVUTSRQPONMLKJIHGFEDCBA
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MISA_VAL:=0b01000000000000000001000100000100;
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PGSIZE := 0x1000; //1 << 12;
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PGMASK := 0xfff; //PGSIZE-1
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unsigned MISA_VAL=0b01000000000000000001000100000100;
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unsigned PGSIZE = 0x1000; //1 << 12;
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unsigned PGMASK = 0xfff; //PGSIZE-1
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}
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}
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@ -1,74 +0,0 @@
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import "RV32I.core_desc"
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import "RV64I.core_desc"
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import "RVM.core_desc"
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import "RVA.core_desc"
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import "RVC.core_desc"
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import "RVF.core_desc"
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import "RVD.core_desc"
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Core MNRV32 provides RV32I, RV32IC {
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constants {
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XLEN:=32;
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PCLEN:=32;
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// definitions for the architecture wrapper
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// XL ZYXWVUTSRQPONMLKJIHGFEDCBA
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MISA_VAL:=0b01000000000101000001000100000101;
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PGSIZE := 0x1000; //1 << 12;
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PGMASK := 0xfff; //PGSIZE-1
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}
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}
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Core RV32IMAC provides RV32I, RV32M, RV32A, RV32IC {
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constants {
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XLEN:=32;
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PCLEN:=32;
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MUL_LEN:=64;
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// definitions for the architecture wrapper
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// XL ZYXWVUTSRQPONMLKJIHGFEDCBA
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MISA_VAL:=0b01000000000101000001000100000101;
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PGSIZE := 0x1000; //1 << 12;
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PGMASK := 0xfff; //PGSIZE-1
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}
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}
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Core RV32GC provides RV32I, RV32M, RV32A, RV32F, RV32D, RV32IC, RV32FC, RV32DC {
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constants {
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XLEN:=32;
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FLEN:=64;
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PCLEN:=32;
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MUL_LEN:=64;
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// definitions for the architecture wrapper
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// XL ZYXWVUTSRQPONMLKJIHGFEDCBA
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MISA_VAL:=0b01000000000101000001000100101101;
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PGSIZE := 0x1000; //1 << 12;
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PGMASK := 0xfff; //PGSIZE-1
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}
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}
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Core RV64I provides RV64I {
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constants {
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XLEN:=64;
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PCLEN:=64;
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// definitions for the architecture wrapper
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// XL ZYXWVUTSRQPONMLKJIHGFEDCBA
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MISA_VAL:=0b10000000000001000000000100000000;
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PGSIZE := 0x1000; //1 << 12;
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PGMASK := 0xfff; //PGSIZE-1
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}
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}
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Core RV64GC provides RV64I, RV64M, RV64A, RV64F, RV64D, RV32FC, RV32DC, RV64IC {
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constants {
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XLEN:=64;
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FLEN:=64;
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PCLEN:=64;
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MUL_LEN:=128;
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// definitions for the architecture wrapper
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// XL ZYXWVUTSRQPONMLKJIHGFEDCBA
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MISA_VAL:=0b01000000000101000001000100101101;
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PGSIZE := 0x1000; //1 << 12;
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PGMASK := 0xfff; //PGSIZE-1
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}
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}
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@ -30,48 +30,6 @@
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*
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*******************************************************************************/
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<%
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import com.minres.coredsl.coreDsl.Register
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import com.minres.coredsl.coreDsl.RegisterFile
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import com.minres.coredsl.coreDsl.RegisterAlias
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def getTypeSize(size){
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if(size > 32) 64 else if(size > 16) 32 else if(size > 8) 16 else 8
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}
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def getOriginalName(reg){
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if( reg.original instanceof RegisterFile) {
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if( reg.index != null ) {
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return reg.original.name+generator.generateHostCode(reg.index)
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} else {
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return reg.original.name
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}
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} else if(reg.original instanceof Register){
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return reg.original.name
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}
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}
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def getRegisterNames(){
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def regNames = []
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allRegs.each { reg ->
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if( reg instanceof RegisterFile) {
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(reg.range.right..reg.range.left).each{
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regNames+=reg.name.toLowerCase()+it
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}
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} else if(reg instanceof Register){
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regNames+=reg.name.toLowerCase()
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}
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}
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return regNames
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}
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def getRegisterAliasNames(){
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def regMap = allRegs.findAll{it instanceof RegisterAlias }.collectEntries {[getOriginalName(it), it.name]}
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return allRegs.findAll{it instanceof Register || it instanceof RegisterFile}.collect{reg ->
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if( reg instanceof RegisterFile) {
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return (reg.range.right..reg.range.left).collect{ (regMap[reg.name]?:regMap[reg.name+it]?:reg.name.toLowerCase()+it).toLowerCase() }
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} else if(reg instanceof Register){
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regMap[reg.name]?:reg.name.toLowerCase()
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}
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}.flatten()
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}
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%>
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#ifndef _${coreDef.name.toUpperCase()}_H_
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#define _${coreDef.name.toUpperCase()}_H_
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@ -89,25 +47,19 @@ template <> struct traits<${coreDef.name.toLowerCase()}> {
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constexpr static char const* const core_type = "${coreDef.name}";
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static constexpr std::array<const char*, ${getRegisterNames().size}> reg_names{
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{"${getRegisterNames().join("\", \"")}"}};
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static constexpr std::array<const char*, ${registers.size}> reg_names{
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{"${registers.collect{it.name}.join('", "')}"}};
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static constexpr std::array<const char*, ${getRegisterAliasNames().size}> reg_aliases{
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{"${getRegisterAliasNames().join("\", \"")}"}};
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static constexpr std::array<const char*, ${registers.size}> reg_aliases{
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{"${registers.collect{it.alias}.join('", "')}"}};
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enum constants {${coreDef.constants.collect{c -> c.name+"="+c.value}.join(', ')}};
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enum constants {${constants.collect{c -> c.name+"="+c.value}.join(', ')}};
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constexpr static unsigned FP_REGS_SIZE = ${coreDef.constants.find {it.name=='FLEN'}?.value?:0};
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constexpr static unsigned FP_REGS_SIZE = ${constants.find {it.name=='FLEN'}?.value?:0};
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enum reg_e {<%
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allRegs.each { reg ->
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if( reg instanceof RegisterFile) {
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(reg.range.right..reg.range.left).each{%>
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${reg.name}${it},<%
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}
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} else if(reg instanceof Register){ %>
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registers.each { reg -> %>
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${reg.name},<%
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}
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}%>
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NUM_REGS,
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NEXT_${pc.name}=NUM_REGS,
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@ -115,15 +67,10 @@ template <> struct traits<${coreDef.name.toLowerCase()}> {
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PENDING_TRAP,
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MACHINE_STATE,
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LAST_BRANCH,
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ICOUNT<%
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allRegs.each { reg ->
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if(reg instanceof RegisterAlias){ def aliasname=getOriginalName(reg)%>,
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${reg.name} = ${aliasname}<%
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}
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}%>
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ICOUNT
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};
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using reg_t = uint${regDataWidth}_t;
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using reg_t = uint${addrDataWidth}_t;
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using addr_t = uint${addrDataWidth}_t;
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@ -133,17 +80,17 @@ template <> struct traits<${coreDef.name.toLowerCase()}> {
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using phys_addr_t = iss::typed_addr_t<iss::address_type::PHYSICAL>;
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static constexpr std::array<const uint32_t, ${regSizes.size}> reg_bit_widths{
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{${regSizes.join(",")}}};
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static constexpr std::array<const uint32_t, ${registers.size}> reg_bit_widths{
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{${registers.collect{it.size}.join(',')}}};
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static constexpr std::array<const uint32_t, ${regOffsets.size}> reg_byte_offsets{
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{${regOffsets.join(",")}}};
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static constexpr std::array<const uint32_t, ${registers.size}> reg_byte_offsets{
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{${registers.collect{it.offset}.join(',')}}};
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static const uint64_t addr_mask = (reg_t(1) << (XLEN - 1)) | ((reg_t(1) << (XLEN - 1)) - 1);
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enum sreg_flag_e { FLAGS };
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enum mem_type_e { ${allSpaces.collect{s -> s.name}.join(', ')} };
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enum mem_type_e { ${spaces.collect{it.name}.join(', ')} };
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};
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struct ${coreDef.name.toLowerCase()}: public arch_if {
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@ -190,16 +137,10 @@ struct ${coreDef.name.toLowerCase()}: public arch_if {
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protected:
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struct ${coreDef.name}_regs {<%
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allRegs.each { reg ->
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if( reg instanceof RegisterFile) {
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(reg.range.right..reg.range.left).each{%>
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uint${generator.getSize(reg)}_t ${reg.name}${it} = 0;<%
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}
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} else if(reg instanceof Register){ %>
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uint${generator.getSize(reg)}_t ${reg.name} = 0;<%
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}
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registers.each { reg ->%>
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uint${reg.size}_t ${reg.name} = 0;<%
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}%>
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uint${generator.getSize(pc)}_t NEXT_${pc.name} = 0;
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uint${pc.size}_t NEXT_${pc.name} = 0;
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uint32_t trap_state = 0, pending_trap = 0, machine_state = 0, last_branch = 0;
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uint64_t icount = 0;
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} reg;
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@ -208,10 +149,10 @@ protected:
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uint64_t interrupt_sim=0;
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<%
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def fcsr = allRegs.find {it.name=='FCSR'}
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def fcsr = registers.find {it.name=='FCSR'}
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if(fcsr != null) {%>
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uint${generator.getSize(fcsr)}_t get_fcsr(){return reg.FCSR;}
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void set_fcsr(uint${generator.getSize(fcsr)}_t val){reg.FCSR = val;}
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uint${fcsr.size}_t get_fcsr(){return reg.FCSR;}
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void set_fcsr(uint${fcsr.size}_t val){reg.FCSR = val;}
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<%} else { %>
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uint32_t get_fcsr(){return 0;}
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void set_fcsr(uint32_t val){}
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@ -29,45 +29,7 @@
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* POSSIBILITY OF SUCH DAMAGE.
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*
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*******************************************************************************/
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<%
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import com.minres.coredsl.coreDsl.Register
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import com.minres.coredsl.coreDsl.RegisterFile
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import com.minres.coredsl.coreDsl.RegisterAlias
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def getOriginalName(reg){
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if( reg.original instanceof RegisterFile) {
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if( reg.index != null ) {
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return reg.original.name+generator.generateHostCode(reg.index)
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} else {
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return reg.original.name
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}
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} else if(reg.original instanceof Register){
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return reg.original.name
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}
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}
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def getRegisterNames(){
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def regNames = []
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allRegs.each { reg ->
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if( reg instanceof RegisterFile) {
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(reg.range.right..reg.range.left).each{
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regNames+=reg.name.toLowerCase()+it
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}
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} else if(reg instanceof Register){
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regNames+=reg.name.toLowerCase()
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}
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}
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return regNames
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}
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def getRegisterAliasNames(){
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def regMap = allRegs.findAll{it instanceof RegisterAlias }.collectEntries {[getOriginalName(it), it.name]}
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return allRegs.findAll{it instanceof Register || it instanceof RegisterFile}.collect{reg ->
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if( reg instanceof RegisterFile) {
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return (reg.range.right..reg.range.left).collect{ (regMap[reg.name]?:regMap[reg.name+it]?:reg.name.toLowerCase()+it).toLowerCase() }
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} else if(reg instanceof Register){
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regMap[reg.name]?:reg.name.toLowerCase()
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}
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}.flatten()
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}
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%>
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#include "util/ities.h"
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#include <util/logging.h>
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#include <iss/arch/${coreDef.name.toLowerCase()}.h>
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@ -77,10 +39,10 @@ def getRegisterAliasNames(){
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using namespace iss::arch;
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constexpr std::array<const char*, ${getRegisterNames().size}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_names;
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constexpr std::array<const char*, ${getRegisterAliasNames().size}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_aliases;
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constexpr std::array<const uint32_t, ${regSizes.size}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_bit_widths;
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constexpr std::array<const uint32_t, ${regOffsets.size}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_byte_offsets;
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constexpr std::array<const char*, ${registers.size}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_names;
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constexpr std::array<const char*, ${registers.size}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_aliases;
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constexpr std::array<const uint32_t, ${registers.size}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_bit_widths;
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constexpr std::array<const uint32_t, ${registers.size}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_byte_offsets;
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${coreDef.name.toLowerCase()}::${coreDef.name.toLowerCase()}() {
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reg.icount = 0;
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@ -56,13 +56,14 @@ using namespace iss::debugger;
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template <typename ARCH> class vm_impl : public iss::interp::vm_base<ARCH> {
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public:
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using super = typename iss::interp::vm_base<ARCH>;
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using traits = arch::traits<ARCH>;
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using super = typename iss::interp::vm_base<ARCH>;
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using virt_addr_t = typename super::virt_addr_t;
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using phys_addr_t = typename super::phys_addr_t;
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using code_word_t = typename super::code_word_t;
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using addr_t = typename super::addr_t;
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using reg_t = typename traits<ARCH>::reg_t;
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using iss::interp::vm_base<ARCH>::get_reg;
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using addr_t = typename super::addr_t;
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using reg_t = typename traits::reg_t;
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using mem_type_e = typename traits::mem_type_e;
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vm_impl();
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@ -82,7 +83,7 @@ protected:
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using compile_ret_t = virt_addr_t;
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using compile_func = compile_ret_t (this_class::*)(virt_addr_t &pc, code_word_t instr);
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inline const char *name(size_t index){return traits<ARCH>::reg_aliases.at(index);}
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inline const char *name(size_t index){return traits::reg_aliases.at(index);}
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virt_addr_t execute_inst(virt_addr_t start, std::function<bool(void)> pred) override;
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@ -138,23 +139,31 @@ protected:
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return lut_val;
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}
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void raise_trap(uint16_t trap_id, uint16_t cause){
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void raise(uint16_t trap_id, uint16_t cause){
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auto trap_val = 0x80ULL << 24 | (cause << 16) | trap_id;
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this->template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE) = trap_val;
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this->template get_reg<uint32_t>(arch::traits<ARCH>::NEXT_PC) = std::numeric_limits<uint32_t>::max();
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this->template get_reg<uint32_t>(traits::TRAP_STATE) = trap_val;
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this->template get_reg<uint32_t>(traits::NEXT_PC) = std::numeric_limits<uint32_t>::max();
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}
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void leave_trap(unsigned lvl){
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void leave(unsigned lvl){
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this->core.leave_trap(lvl);
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auto pc_val = super::template read_mem<reg_t>(traits<ARCH>::CSR, (lvl << 8) + 0x41);
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this->template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = pc_val;
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this->template get_reg<uint32_t>(arch::traits<ARCH>::LAST_BRANCH) = std::numeric_limits<uint32_t>::max();
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auto pc_val = super::template read_mem<reg_t>(traits::CSR, (lvl << 8) + 0x41);
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this->template get_reg<reg_t>(traits::NEXT_PC) = pc_val;
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this->template get_reg<uint32_t>(traits::LAST_BRANCH) = std::numeric_limits<uint32_t>::max();
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}
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void wait(unsigned type){
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this->core.wait_until(type);
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}
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inline uint8_t readSpace1(typename super::mem_type_e space, uint64_t addr){return super::template read_mem<uint8_t>(space, addr);}
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inline uint16_t readSpace2(typename super::mem_type_e space, uint64_t addr){return super::template read_mem<uint16_t>(space, addr);}
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inline uint32_t readSpace4(typename super::mem_type_e space, uint64_t addr){return super::template read_mem<uint32_t>(space, addr);}
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inline uint64_t readSpace8(typename super::mem_type_e space, uint64_t addr){return super::template read_mem<uint64_t>(space, addr);}
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inline void writeSpace1(typename super::mem_type_e space, uint64_t addr, uint8_t data){super::write_mem(space, addr, data);}
|
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inline void writeSpace2(typename super::mem_type_e space, uint64_t addr, uint16_t data){super::write_mem(space, addr, data);}
|
||||
inline void writeSpace4(typename super::mem_type_e space, uint64_t addr, uint32_t data){super::write_mem(space, addr, data);}
|
||||
inline void writeSpace8(typename super::mem_type_e space, uint64_t addr, uint64_t data){super::write_mem(space, addr, data);}
|
||||
|
||||
private:
|
||||
/****************************************************************************
|
||||
|
|
@ -170,13 +179,33 @@ private:
|
|||
const std::array<InstructionDesriptor, ${instructions.size}> instr_descr = {{
|
||||
/* entries are: size, valid value, valid mask, function ptr */<%instructions.each{instr -> %>
|
||||
/* instruction ${instr.instruction.name} */
|
||||
{${instr.length}, ${instr.value}, ${instr.mask}, &this_class::__${generator.functionName(instr.name)}},<%}%>
|
||||
{${instr.length}, ${instr.encoding}, ${instr.mask}, &this_class::__${generator.functionName(instr.name)}},<%}%>
|
||||
}};
|
||||
|
||||
/* instruction definitions */<%instructions.eachWithIndex{instr, idx -> %>
|
||||
/* instruction ${idx}: ${instr.name} */
|
||||
compile_ret_t __${generator.functionName(instr.name)}(virt_addr_t& pc, code_word_t instr){<%instr.code.eachLine{%>
|
||||
${it}<%}%>
|
||||
compile_ret_t __${generator.functionName(instr.name)}(virt_addr_t& pc, code_word_t instr){
|
||||
this->do_sync(PRE_SYNC, ${idx});
|
||||
<%instr.fields.eachLine{%>${it}
|
||||
<%}%>if(this->disass_enabled){
|
||||
/* generate console output when executing the command */
|
||||
<%instr.disass.eachLine{%>${it}
|
||||
<%}%>}
|
||||
auto cur_pc_val = pc.val;
|
||||
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = cur_pc_val + ${instr.length/8};
|
||||
uint${addrDataWidth}_t* X = reinterpret_cast<uint${addrDataWidth}_t*>(this->regs_base_ptr+arch::traits<ARCH>::X0);
|
||||
uint${addrDataWidth}_t* PC = reinterpret_cast<uint${addrDataWidth}_t*>(this->regs_base_ptr+arch::traits<ARCH>::PC);
|
||||
<%instr.behavior.eachLine{%>${it}
|
||||
<%}%>this->do_sync(POST_SYNC, ${idx});
|
||||
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
|
||||
// trap check
|
||||
if(trap_state!=0){
|
||||
auto& last_br = super::template get_reg<uint32_t>(arch::traits<ARCH>::LAST_BRANCH);
|
||||
last_br = std::numeric_limits<uint32_t>::max();
|
||||
super::core.enter_trap(trap_state, cur_pc_val);
|
||||
}
|
||||
pc.val=super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC);
|
||||
return pc;
|
||||
}
|
||||
<%}%>
|
||||
/****************************************************************************
|
||||
|
|
@ -212,7 +241,7 @@ template <typename ARCH>
|
|||
typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(virt_addr_t start, std::function<bool(void)> pred) {
|
||||
// we fetch at max 4 byte, alignment is 2
|
||||
enum {TRAP_ID=1<<16};
|
||||
const typename traits<ARCH>::addr_t upper_bits = ~traits<ARCH>::PGMASK;
|
||||
const typename traits::addr_t upper_bits = ~traits::PGMASK;
|
||||
code_word_t insn = 0;
|
||||
auto *const data = (uint8_t *)&insn;
|
||||
auto pc=start;
|
||||
|
|
|
|||
|
|
@ -30,7 +30,6 @@
|
|||
*
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
#ifndef _TGF_C_H_
|
||||
#define _TGF_C_H_
|
||||
|
||||
|
|
@ -49,12 +48,12 @@ template <> struct traits<tgf_c> {
|
|||
constexpr static char const* const core_type = "TGF_C";
|
||||
|
||||
static constexpr std::array<const char*, 33> reg_names{
|
||||
{"x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28", "x29", "x30", "x31", "pc"}};
|
||||
{"X0", "X1", "X2", "X3", "X4", "X5", "X6", "X7", "X8", "X9", "X10", "X11", "X12", "X13", "X14", "X15", "X16", "X17", "X18", "X19", "X20", "X21", "X22", "X23", "X24", "X25", "X26", "X27", "X28", "X29", "X30", "X31", "PC"}};
|
||||
|
||||
static constexpr std::array<const char*, 33> reg_aliases{
|
||||
{"zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", "s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5", "a6", "a7", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6", "pc"}};
|
||||
{"ZERO", "RA", "SP", "GP", "TP", "T0", "T1", "T2", "S0", "S1", "A0", "A1", "A2", "A3", "A4", "A5", "A6", "A7", "S2", "S3", "S4", "S5", "S6", "S7", "S8", "S9", "S10", "S11", "T3", "T4", "T5", "T6", "PC"}};
|
||||
|
||||
enum constants {XLEN=32, PCLEN=32, MUL_LEN=64, MISA_VAL=0b1000000000000000001000100000100, PGSIZE=0x1000, PGMASK=0xfff};
|
||||
enum constants {XLEN=32, PCLEN=32, MUL_LEN=64, MISA_VAL=0b1000000000000000001000100000100, PGSIZE=0x1000, PGMASK=0xfff, CSR_SIZE=4096, fence=0, fencei=1, fencevmal=2, fencevmau=3};
|
||||
|
||||
constexpr static unsigned FP_REGS_SIZE = 0;
|
||||
|
||||
|
|
@ -98,39 +97,7 @@ template <> struct traits<tgf_c> {
|
|||
PENDING_TRAP,
|
||||
MACHINE_STATE,
|
||||
LAST_BRANCH,
|
||||
ICOUNT,
|
||||
ZERO = X0,
|
||||
RA = X1,
|
||||
SP = X2,
|
||||
GP = X3,
|
||||
TP = X4,
|
||||
T0 = X5,
|
||||
T1 = X6,
|
||||
T2 = X7,
|
||||
S0 = X8,
|
||||
S1 = X9,
|
||||
A0 = X10,
|
||||
A1 = X11,
|
||||
A2 = X12,
|
||||
A3 = X13,
|
||||
A4 = X14,
|
||||
A5 = X15,
|
||||
A6 = X16,
|
||||
A7 = X17,
|
||||
S2 = X18,
|
||||
S3 = X19,
|
||||
S4 = X20,
|
||||
S5 = X21,
|
||||
S6 = X22,
|
||||
S7 = X23,
|
||||
S8 = X24,
|
||||
S9 = X25,
|
||||
S10 = X26,
|
||||
S11 = X27,
|
||||
T3 = X28,
|
||||
T4 = X29,
|
||||
T5 = X30,
|
||||
T6 = X31
|
||||
ICOUNT
|
||||
};
|
||||
|
||||
using reg_t = uint32_t;
|
||||
|
|
@ -143,11 +110,11 @@ template <> struct traits<tgf_c> {
|
|||
|
||||
using phys_addr_t = iss::typed_addr_t<iss::address_type::PHYSICAL>;
|
||||
|
||||
static constexpr std::array<const uint32_t, 39> reg_bit_widths{
|
||||
{32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,64}};
|
||||
static constexpr std::array<const uint32_t, 33> reg_bit_widths{
|
||||
{32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32}};
|
||||
|
||||
static constexpr std::array<const uint32_t, 40> reg_byte_offsets{
|
||||
{0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148,152,160}};
|
||||
static constexpr std::array<const uint32_t, 33> reg_byte_offsets{
|
||||
{0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128}};
|
||||
|
||||
static const uint64_t addr_mask = (reg_t(1) << (XLEN - 1)) | ((reg_t(1) << (XLEN - 1)) - 1);
|
||||
|
||||
|
|
|
|||
|
|
@ -41,8 +41,8 @@ using namespace iss::arch;
|
|||
|
||||
constexpr std::array<const char*, 33> iss::arch::traits<iss::arch::tgf_c>::reg_names;
|
||||
constexpr std::array<const char*, 33> iss::arch::traits<iss::arch::tgf_c>::reg_aliases;
|
||||
constexpr std::array<const uint32_t, 39> iss::arch::traits<iss::arch::tgf_c>::reg_bit_widths;
|
||||
constexpr std::array<const uint32_t, 40> iss::arch::traits<iss::arch::tgf_c>::reg_byte_offsets;
|
||||
constexpr std::array<const uint32_t, 33> iss::arch::traits<iss::arch::tgf_c>::reg_bit_widths;
|
||||
constexpr std::array<const uint32_t, 33> iss::arch::traits<iss::arch::tgf_c>::reg_byte_offsets;
|
||||
|
||||
tgf_c::tgf_c() {
|
||||
reg.icount = 0;
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
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Reference in New Issue