DBT-RISE/DBT-RISE-TGC
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add code word access for ISS plugins

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This commit is contained in:
Eyck Jentzsch
2022-04-25 14:18:19 +02:00
parent 477c530847
commit a92b84bef4
9 changed files with 42 additions and 33 deletions
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23
src/vm/interp/vm_tgc_c.cpp
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@ -358,9 +358,6 @@ typename arch::traits<ARCH>::opcode_e vm_impl<ARCH>::decode_inst_id(code_word_t
template <typename ARCH>
typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e cond, virt_addr_t start, uint64_t icount_limit){
// we fetch at max 4 byte, alignment is 2
code_word_t instr = 0;
auto *const data = (uint8_t *)&instr;
auto pc=start;
auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
@ -368,6 +365,10 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
auto* icount = reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::ICOUNT]);
auto* instret = reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::INSTRET]);
auto *const instruction = reinterpret_cast<code_word_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::INSTRUCTION]);
// we fetch at max 4 byte, alignment is 2
auto *const data = reinterpret_cast<uint8_t*>(instruction);
auto& instr = *instruction;
while(!this->core.should_stop() &&
!(is_count_limit_enabled(cond) && this->core.get_icount() >= icount_limit)){
@ -2001,7 +2002,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
try {
{
uint8_t rs1_idx = rs1 + 8;
uint32_t rs1_idx = rs1 + 8;
*(X+rs1_idx) = *(X+rs1_idx) >> shamt;
}
} catch(...){}
@ -2024,11 +2025,11 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
try {
if(shamt) {
uint8_t rs1_idx = rs1 + 8;
uint32_t rs1_idx = rs1 + 8;
*(X+rs1_idx) = ((int32_t)*(X+rs1_idx)) >> shamt;
}
else if(traits::XLEN == 128) {
uint8_t rs1_idx = rs1 + 8;
uint32_t rs1_idx = rs1 + 8;
*(X+rs1_idx) = ((int32_t)*(X+rs1_idx)) >> 64;
}
} catch(...){}
@ -2051,7 +2052,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
try {
{
uint8_t rs1_idx = rs1 + 8;
uint32_t rs1_idx = rs1 + 8;
*(X+rs1_idx) = *(X+rs1_idx) & (int8_t)sext<6>(imm);
}
} catch(...){}
@ -2074,7 +2075,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
try {
{
uint8_t rd_idx = rd + 8;
uint32_t rd_idx = rd + 8;
*(X+rd_idx) = *(X+rd_idx) - *(X+rs2 + 8);
}
} catch(...){}
@ -2097,7 +2098,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
try {
{
uint8_t rd_idx = rd + 8;
uint32_t rd_idx = rd + 8;
*(X+rd_idx) = *(X+rd_idx) ^ *(X+rs2 + 8);
}
} catch(...){}
@ -2120,7 +2121,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
try {
{
uint8_t rd_idx = rd + 8;
uint32_t rd_idx = rd + 8;
*(X+rd_idx) = *(X+rd_idx) | *(X+rs2 + 8);
}
} catch(...){}
@ -2143,7 +2144,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
try {
{
uint8_t rd_idx = rd + 8;
uint32_t rd_idx = rd + 8;
*(X+rd_idx) = *(X+rd_idx) & *(X+rs2 + 8);
}
} catch(...){}