fixes CSR/CLIC implementation
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ec55efd322
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a83928fd8c
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@ -114,7 +114,7 @@ enum riscv_csr {
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mtval = 0x343,
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mip = 0x344,
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mxnti = 0x345, //CLIC
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mintstatus = 0x346, // MRW Current interrupt levels (CLIC) - addr subject to change
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mintstatus = 0xFB1, // MRW Current interrupt levels (CLIC) - addr subject to change
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mintthresh = 0x347, // MRW Interrupt-level threshold (CLIC) - addr subject to change
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mscratchcsw = 0x348, // MRW Conditional scratch swap on priv mode change (CLIC)
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mscratchcswl = 0x349, // MRW Conditional scratch swap on level change (CLIC)
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@ -212,9 +212,9 @@ public:
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csr[addr & csr.page_addr_mask] = val;
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}
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void set_irq_num(unsigned i) {
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mcause_max_irq=1<<util::ilog2(i);
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}
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// void set_irq_num(unsigned i) {
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// mcause_max_irq=1<<util::ilog2(i);
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// }
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protected:
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struct riscv_instrumentation_if : public iss::instrumentation_if {
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@ -337,7 +337,7 @@ protected:
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std::vector<std::function<mem_write_f>> memfn_write;
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void insert_mem_range(uint64_t, uint64_t, std::function<mem_read_f>, std::function<mem_write_f>);
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feature_config cfg;
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unsigned mcause_max_irq{16};
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unsigned mcause_max_irq{(FEAT&features_e::FEAT_CLIC)?4096:16};
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inline bool debug_mode_active() {return this->reg.PRIV&0x4;}
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};
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@ -428,7 +428,6 @@ riscv_hart_m_p<BASE, FEAT>::riscv_hart_m_p(feature_config cfg)
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clic_int_reg.resize(cfg.clic_num_irq, clic_int_reg_t{.raw=0});
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clic_cfg_reg=0x20;
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clic_info_reg = (/*CLICINTCTLBITS*/ 4U<<21) + cfg.clic_num_irq;
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mcause_max_irq=cfg.clic_num_irq+16;
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insert_mem_range(cfg.clic_base, 0x5000UL,
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[this](phys_addr_t addr, unsigned length, uint8_t * const data) { return read_clic(addr.val, length, data);},
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[this](phys_addr_t addr, unsigned length, uint8_t const * const data) {return write_clic(addr.val, length, data);});
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@ -850,7 +849,7 @@ template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>
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}
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template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::read_tvec(unsigned addr, reg_t &val) {
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val = csr[addr] & ~2;
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val = FEAT & features_e::FEAT_CLIC? csr[addr] : csr[addr] & ~2;
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return iss::Ok;
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}
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@ -866,7 +865,7 @@ template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>
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}
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template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::write_cause(unsigned addr, reg_t val) {
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csr[addr] = val & ((1UL<<(traits<BASE>::XLEN-1))| (mcause_max_irq-1));
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csr[addr] = val & ((1UL<<(traits<BASE>::XLEN-1)) | (mcause_max_irq-1));
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return iss::Ok;
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}
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@ -1111,7 +1110,7 @@ template <typename BASE, features_e FEAT> void riscv_hart_m_p<BASE, FEAT>::check
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template <typename BASE, features_e FEAT> uint64_t riscv_hart_m_p<BASE, FEAT>::enter_trap(uint64_t flags, uint64_t addr, uint64_t instr) {
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// flags are ACTIVE[31:31], CAUSE[30:16], TRAPID[15:0]
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// calculate and write mcause val
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auto trap_id = bit_sub<0, 16>(flags);
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auto const trap_id = bit_sub<0, 16>(flags);
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auto cause = bit_sub<16, 15>(flags);
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// calculate effective privilege level
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unsigned new_priv = PRIV_M;
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@ -1167,11 +1166,19 @@ template <typename BASE, features_e FEAT> uint64_t riscv_hart_m_p<BASE, FEAT>::e
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state.mstatus.MIE = false;
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// get trap vector
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auto ivec = csr[mtvec];
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// calculate addr// set NEXT_PC to trap addressess to jump to based on MODE
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auto xtvec = csr[mtvec];
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// calculate adds// set NEXT_PC to trap addressess to jump to based on MODE
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if((FEAT & features_e::FEAT_CLIC) && trap_id!=0 && (xtvec & 0x3UL)==3UL) {
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reg_t data;
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auto ret = read(address_type::LOGICAL, access_type::READ, 0, csr[mtvt], sizeof(reg_t), reinterpret_cast<uint8_t*>(&data));
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if(ret == iss::Err)
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return this->reg.PC;
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this->reg.NEXT_PC = data;
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} else {
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// bits in mtvec
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this->reg.NEXT_PC = ivec & ~0x3UL;
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if ((ivec & 0x1) == 1 && trap_id != 0) this->reg.NEXT_PC += 4 * cause;
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this->reg.NEXT_PC = xtvec & ~0x3UL;
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if ((xtvec & 0x1) == 1 && trap_id != 0) this->reg.NEXT_PC += 4 * cause;
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}
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// reset trap state
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this->reg.PRIV = new_priv;
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this->trap_state = 0;
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@ -227,9 +227,9 @@ public:
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csr[addr & csr.page_addr_mask] = val;
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}
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void set_irq_num(unsigned i) {
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mcause_max_irq=1<<util::ilog2(i);
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}
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// void set_irq_num(unsigned i) {
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// mcause_max_irq=1<<util::ilog2(i);
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// }
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protected:
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struct riscv_instrumentation_if : public iss::instrumentation_if {
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@ -355,7 +355,7 @@ protected:
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std::vector<std::function<mem_write_f>> memfn_write;
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void insert_mem_range(uint64_t, uint64_t, std::function<mem_read_f>, std::function<mem_write_f>);
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feature_config cfg;
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unsigned mcause_max_irq{16};
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unsigned mcause_max_irq{(FEAT&features_e::FEAT_CLIC)?4096:16};
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inline bool debug_mode_active() {return this->reg.PRIV&0x4;}
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};
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@ -475,7 +475,6 @@ riscv_hart_mu_p<BASE, FEAT>::riscv_hart_mu_p(feature_config cfg)
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clic_int_reg.resize(cfg.clic_num_irq, clic_int_reg_t{.raw=0});
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clic_cfg_reg=0x20;
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clic_info_reg = (/*CLICINTCTLBITS*/ 4U<<21) + cfg.clic_num_irq;
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mcause_max_irq=cfg.clic_num_irq+16;
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insert_mem_range(cfg.clic_base, 0x5000UL,
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[this](phys_addr_t addr, unsigned length, uint8_t * const data) { return read_clic(addr.val, length, data);},
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[this](phys_addr_t addr, unsigned length, uint8_t const * const data) {return write_clic(addr.val, length, data);});
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@ -1001,7 +1000,7 @@ template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT
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}
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template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT>::read_tvec(unsigned addr, reg_t &val) {
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val = csr[addr] & ~2;
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val = FEAT & features_e::FEAT_CLIC? csr[addr] : csr[addr] & ~2;
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return iss::Ok;
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}
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template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT>::read_status(unsigned addr, reg_t &val) {
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@ -1350,13 +1349,26 @@ template <typename BASE, features_e FEAT> uint64_t riscv_hart_mu_p<BASE, FEAT>::
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}
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// get trap vector
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auto ivec = csr[utvec | (new_priv << 8)];
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auto xtvec = csr[utvec | (new_priv << 8)];
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// calculate addr// set NEXT_PC to trap addressess to jump to based on MODE
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// bits in mtvec
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this->reg.NEXT_PC = ivec & ~0x3UL;
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if ((ivec & 0x1) == 1 && trap_id != 0) this->reg.NEXT_PC += 4 * cause;
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if((FEAT & features_e::FEAT_CLIC) && trap_id!=0 && (xtvec & 0x3UL)==3UL) {
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reg_t data;
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auto ret = read(address_type::LOGICAL, access_type::READ, 0, csr[mtvt], sizeof(reg_t), reinterpret_cast<uint8_t*>(&data));
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if(ret == iss::Err)
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return this->reg.PC;
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this->reg.NEXT_PC = data;
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} else {
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this->reg.NEXT_PC = xtvec & ~0x3UL;
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if ((xtvec & 0x1) == 1 && trap_id != 0)
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this->reg.NEXT_PC += 4 * cause;
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}
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std::array<char, 32> buffer;
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#if defined(_MSC_VER)
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sprintf(buffer.data(), "0x%016llx", addr);
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#else
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sprintf(buffer.data(), "0x%016lx", addr);
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#endif
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if((flags&0xffffffff) != 0xffffffff)
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CLOG(INFO, disass) << (trap_id ? "Interrupt" : "Trap") << " with cause '"
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<< (trap_id ? irq_str[cause] : trap_str[cause]) << "' (" << cause << ")"
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