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DBT-RISE-TGC
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updates TGC_C according to CoreDSL description update

This commit is contained in:
Eyck Jentzsch 2022-07-12 22:34:22 +02:00
parent 12ccfc055a
commit a53ee42e13
1 changed files with 4 additions and 5 deletions
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7
src/vm/interp/vm_tgc_c.cpp
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@ -2187,12 +2187,11 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
*NEXT_PC = *PC + 2; *NEXT_PC = *PC + 2;
// execute instruction // execute instruction
{ {
uint32_t offs = *(X+2) + uimm; if(rd % traits::RFS) {
int32_t read_res = super::template read_mem<int32_t>(traits::MEM, offs); int32_t read_res = super::template read_mem<int32_t>(traits::MEM, *(X+2) + uimm);
if(this->core.trap_state) goto TRAP_CLWSP; if(this->core.trap_state) goto TRAP_CLWSP;
int32_t res = read_res; int32_t res = read_res;
if(rd % traits::RFS) { *(X+rd % traits::RFS) = (int32_t)res;
*(X+rd % traits::RFS) = res;
} }
else { else {
raise(0, 2); raise(0, 2);