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DBT-RISE-TGC
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fix format

This commit is contained in:
Stanislaw Kaushanski 2024-07-30 13:34:23 +02:00
parent d2efb23ff7
commit a365110054
1 changed files with 1 additions and 1 deletions
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2
src/iss/arch/wt_cache.h
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@ -119,7 +119,7 @@ template <typename BASE> iss::status iss::arch::wt_cache<BASE>::read_cache(phys_
icache_ptr.reset(new cache::cache(size, line_sz, ways)); icache_ptr.reset(new cache::cache(size, line_sz, ways));
dcache_ptr.reset(new cache::cache(size, line_sz, ways)); dcache_ptr.reset(new cache::cache(size, line_sz, ways));
} }
if((a.access & iss::access_type::FETCH)== iss::access_type::FETCH || (a.val & io_addr_mask) != io_address) { if((a.access & iss::access_type::FETCH) == iss::access_type::FETCH || (a.val & io_addr_mask) != io_address) {
auto set_addr = (a.val & (size - 1)) >> util::ilog2(line_sz * ways); auto set_addr = (a.val & (size - 1)) >> util::ilog2(line_sz * ways);
auto tag_addr = a.val >> util::ilog2(line_sz); auto tag_addr = a.val >> util::ilog2(line_sz);
auto& set = (is_fetch(a.access) ? icache_ptr : dcache_ptr)->sets[set_addr]; auto& set = (is_fetch(a.access) ? icache_ptr : dcache_ptr)->sets[set_addr];