rework core definitions

2021-09-04 12:46:56 +02:00
parent 09b01af3fa
commit a3084456fd
5 changed files with 117 additions and 37 deletions
--- a/gen_input/TGC_B.core_desc
+++ b/gen_input/TGC_B.core_desc
@ -0,0 +1,16 @@
+import "CoreDSL-Instruction-Set-Description/RV32I.core_desc"
+import "CoreDSL-Instruction-Set-Description/RVM.core_desc"
+import "CoreDSL-Instruction-Set-Description/RVC.core_desc"
+
+Core TGC_B provides RV32I {
+	architectural_state {
+        unsigned XLEN=32;
+        unsigned PCLEN=32;
+        // definitions for the architecture wrapper
+        //                    XL    ZYXWVUTSRQPONMLKJIHGFEDCBA
+        unsigned MISA_VAL = 0b01000000000000000000000100000000;
+        unsigned PGSIZE = 0x1000; //1 << 12;
+        unsigned PGMASK = 0xfff; //PGSIZE-1
+	}
+}
+