DBT-RISE/DBT-RISE-TGC
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fixes duplicate variable declaration and templates

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Eyck Jentzsch
2023-05-27 10:20:49 +02:00
parent ee6218279e
commit a123beb301
17 changed files with 380 additions and 808 deletions
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10
gen_input/TGC_C.core_desc
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@ -1,13 +1,13 @@
import "RV32I.core_desc"
import "RVM.core_desc"
import "RVC.core_desc"
import "ISA/RV32I.core_desc"
import "ISA/RVM.core_desc"
import "ISA/RVC.core_desc"
Core TGC_C provides RV32I, Zicsr, Zifencei, RV32M, RV32IC {
architectural_state {
XLEN=32;
// definitions for the architecture wrapper
// XL ZYXWVUTSRQPONMLKJIHGFEDCBA
unsigned MISA_VAL = 0b01000000000000000001000100000100;
unsigned MARCHID_VAL = 0x80000003;
unsigned int MISA_VAL = 0b01000000000000000001000100000100;
unsigned int MARCHID_VAL = 0x80000003;
}
}