DBT-RISE/DBT-RISE-TGC
9
0
Fork 0
Code Issues 1 Pull Requests 1 Projects Releases Wiki Activity

initial version of MU hart

Browse Source
This commit is contained in:
Eyck Jentzsch
2021-05-14 13:29:39 +02:00
parent c57884caee
commit 9c456ba8f2
2 changed files with 970 additions and 7 deletions
Download Patch File Download Diff File Expand all files Collapse all files

16
src/sysc/core_complex.cpp
View File

@@ -31,14 +31,17 @@
*******************************************************************************/
#include "sysc/core_complex.h"
#include "iss/arch/riscv_hart_m_p.h"
#ifdef CORE_TGC_C
#include "iss/arch/riscv_hart_m_p.h"
#include "iss/arch/tgc_c.h"
using core_type = iss::arch::tgc_c;
using plat_type = iss::arch::riscv_hart_m_p<core_type>;
#endif
#ifdef CORE_TGC_D
#include "iss/arch/riscv_hart_mu_p.h"
#include "iss/arch/tgc_d.h"
using core_type = iss::arch::tgc_d;
using plat_type = iss::arch::riscv_hart_mu_p<core_type>;
#endif
#include "iss/debugger/encoderdecoder.h"
#include "iss/debugger/gdb_session.h"
@@ -95,9 +98,8 @@ std::array<const char*, 12> irq_str = { {
"User external interrupt", "Supervisor external interrupt", "Reserved", "Machine external interrupt" } };
}
class core_wrapper : public iss::arch::riscv_hart_m_p<core_type> {
class core_wrapper : public plat_type {
public:
using base_type = arch::riscv_hart_m_p<core_type>;
using phys_addr_t = typename arch::traits<core_type>::phys_addr_t;
core_wrapper(core_complex *owner)
: owner(owner) { }
@@ -108,7 +110,7 @@ public:
inline bool get_interrupt_execution() { return this->interrupt_sim; }
base_type::hart_state<base_type::reg_t> &get_state() { return this->state; }
plat_type::hart_state<plat_type::reg_t> &get_state() { return this->state; }
void notify_phase(exec_phase p) override {
if (p == ISTART) owner->sync(this->reg.icount + cycle_offset);
@@ -163,7 +165,7 @@ public:
}
return ret?Ok:Err;
} else {
return base_type::read_csr(addr, val);
return plat_type::read_csr(addr, val);
}
}
@@ -172,11 +174,11 @@ public:
do {
wait(wfi_evt);
} while (this->reg.pending_trap == 0);
base_type::wait_until(flags);
plat_type::wait_until(flags);
}
void local_irq(short id, bool value) {
base_type::reg_t mask = 0;
plat_type::reg_t mask = 0;
switch (id) {
case 16: // SW
mask = 1 << 3;