DBT-RISE/DBT-RISE-TGC
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Generate and integrate TGF cores in Ecosystem-VP. Remove obsolete cores

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This commit is contained in:
Stanislaw Kaushanski
2020-08-24 15:01:54 +02:00
parent 03172e352d
commit 9754e3953f
39 changed files with 944 additions and 72865 deletions
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6839
src/vm/interp/vm_rv32gc.cpp
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3793
src/vm/interp/vm_rv32imac.cpp
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File diff suppressed because it is too large Load Diff

8694
src/vm/interp/vm_rv64gc.cpp
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File diff suppressed because it is too large Load Diff

622
src/vm/interp/vm_rv64i.cpp → src/vm/interp/vm_tgf01.cpp
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@ -31,8 +31,8 @@
*******************************************************************************/
#include "../fp_functions.h"
#include <iss/arch/rv64i.h>
#include <iss/arch/riscv_hart_msu_vp.h>
#include <iss/arch/tgf01.h>
#include <iss/arch/riscv_hart_m_p.h>
#include <iss/debugger/gdb_session.h>
#include <iss/debugger/server.h>
#include <iss/iss.h>
@ -50,7 +50,7 @@
namespace iss {
namespace interp {
namespace rv64i {
namespace tgf01 {
using namespace iss::arch;
using namespace iss::debugger;
@ -167,7 +167,7 @@ private:
compile_func op;
};
const std::array<InstructionDesriptor, 64> instr_descr = {{
const std::array<InstructionDesriptor, 52> instr_descr = {{
/* entries are: size, valid value, valid mask, function ptr */
/* instruction LUI */
{32, 0b00000000000000000000000000110111, 0b00000000000000000000000001111111, &this_class::__lui},
@ -218,11 +218,11 @@ private:
/* instruction ANDI */
{32, 0b00000000000000000111000000010011, 0b00000000000000000111000001111111, &this_class::__andi},
/* instruction SLLI */
{32, 0b00000000000000000001000000010011, 0b11111100000000000111000001111111, &this_class::__slli},
{32, 0b00000000000000000001000000010011, 0b11111110000000000111000001111111, &this_class::__slli},
/* instruction SRLI */
{32, 0b00000000000000000101000000010011, 0b11111100000000000111000001111111, &this_class::__srli},
{32, 0b00000000000000000101000000010011, 0b11111110000000000111000001111111, &this_class::__srli},
/* instruction SRAI */
{32, 0b01000000000000000101000000010011, 0b11111100000000000111000001111111, &this_class::__srai},
{32, 0b01000000000000000101000000010011, 0b11111110000000000111000001111111, &this_class::__srai},
/* instruction ADD */
{32, 0b00000000000000000000000000110011, 0b11111110000000000111000001111111, &this_class::__add},
/* instruction SUB */
@ -273,30 +273,6 @@ private:
{32, 0b00000000000000000110000001110011, 0b00000000000000000111000001111111, &this_class::__csrrsi},
/* instruction CSRRCI */
{32, 0b00000000000000000111000001110011, 0b00000000000000000111000001111111, &this_class::__csrrci},
/* instruction LWU */
{32, 0b00000000000000000110000000000011, 0b00000000000000000111000001111111, &this_class::__lwu},
/* instruction LD */
{32, 0b00000000000000000011000000000011, 0b00000000000000000111000001111111, &this_class::__ld},
/* instruction SD */
{32, 0b00000000000000000011000000100011, 0b00000000000000000111000001111111, &this_class::__sd},
/* instruction ADDIW */
{32, 0b00000000000000000000000000011011, 0b00000000000000000111000001111111, &this_class::__addiw},
/* instruction SLLIW */
{32, 0b00000000000000000001000000011011, 0b11111110000000000111000001111111, &this_class::__slliw},
/* instruction SRLIW */
{32, 0b00000000000000000101000000011011, 0b11111110000000000111000001111111, &this_class::__srliw},
/* instruction SRAIW */
{32, 0b01000000000000000101000000011011, 0b11111110000000000111000001111111, &this_class::__sraiw},
/* instruction ADDW */
{32, 0b00000000000000000000000000111011, 0b11111110000000000111000001111111, &this_class::__addw},
/* instruction SUBW */
{32, 0b01000000000000000000000000111011, 0b11111110000000000111000001111111, &this_class::__subw},
/* instruction SLLW */
{32, 0b00000000000000000001000000111011, 0b11111110000000000111000001111111, &this_class::__sllw},
/* instruction SRLW */
{32, 0b00000000000000000101000000111011, 0b11111110000000000111000001111111, &this_class::__srlw},
/* instruction SRAW */
{32, 0b01000000000000000101000000111011, 0b11111110000000000111000001111111, &this_class::__sraw},
}};
/* instruction definitions */
@ -349,7 +325,7 @@ private:
auto cur_pc_val = pc.val;
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = cur_pc_val + 4;
if(rd != 0){
auto Xtmp0_val = (static_cast<int64_t>(cur_pc_val) + (imm));
auto Xtmp0_val = (static_cast<int32_t>(cur_pc_val) + (imm));
super::template get_reg<reg_t>(rd + traits<ARCH>::X0)=Xtmp0_val;
}
this->do_sync(POST_SYNC, 1);
@ -384,7 +360,7 @@ private:
auto Xtmp0_val = (cur_pc_val + 4);
super::template get_reg<reg_t>(rd + traits<ARCH>::X0)=Xtmp0_val;
}
auto PC_val = (static_cast<int64_t>(cur_pc_val) + (imm));
auto PC_val = (static_cast<int32_t>(cur_pc_val) + (imm));
super::template get_reg(traits<ARCH>::NEXT_PC) = PC_val;
auto is_cont_v = PC_val !=pc.val;
super::template get_reg(traits<ARCH>::LAST_BRANCH) = is_cont_v?1:0;
@ -417,7 +393,7 @@ private:
auto cur_pc_val = pc.val;
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = cur_pc_val + 4;
auto new_pc_val = (static_cast<int64_t>(super::template get_reg<reg_t>(rs1 + traits<ARCH>::X0)) + (imm));
auto new_pc_val = (static_cast<int32_t>(super::template get_reg<reg_t>(rs1 + traits<ARCH>::X0)) + (imm));
auto align_val = (new_pc_val & 0x2);
{
if((align_val != 0)) {
@ -463,7 +439,7 @@ private:
auto cur_pc_val = pc.val;
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = cur_pc_val + 4;
auto PC_val = (super::template get_reg<reg_t>(rs1 + traits<ARCH>::X0) == super::template get_reg<reg_t>(rs2 + traits<ARCH>::X0))?
(static_cast<int64_t>(cur_pc_val) + (imm)):
(static_cast<int32_t>(cur_pc_val) + (imm)):
(cur_pc_val + 4);
super::template get_reg(traits<ARCH>::NEXT_PC) = PC_val;
auto is_cont_v = PC_val !=pc.val;
@ -498,7 +474,7 @@ private:
auto cur_pc_val = pc.val;
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = cur_pc_val + 4;
auto PC_val = (super::template get_reg<reg_t>(rs1 + traits<ARCH>::X0) != super::template get_reg<reg_t>(rs2 + traits<ARCH>::X0))?
(static_cast<int64_t>(cur_pc_val) + (imm)):
(static_cast<int32_t>(cur_pc_val) + (imm)):
(cur_pc_val + 4);
super::template get_reg(traits<ARCH>::NEXT_PC) = PC_val;
auto is_cont_v = PC_val !=pc.val;
@ -532,8 +508,8 @@ private:
auto cur_pc_val = pc.val;
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = cur_pc_val + 4;
auto PC_val = (static_cast<int64_t>(super::template get_reg<reg_t>(rs1 + traits<ARCH>::X0)) < static_cast<int64_t>(super::template get_reg<reg_t>(rs2 + traits<ARCH>::X0)))?
(static_cast<int64_t>(cur_pc_val) + (imm)):
auto PC_val = (static_cast<int32_t>(super::template get_reg<reg_t>(rs1 + traits<ARCH>::X0)) < static_cast<int32_t>(super::template get_reg<reg_t>(rs2 + traits<ARCH>::X0)))?
(static_cast<int32_t>(cur_pc_val) + (imm)):
(cur_pc_val + 4);
super::template get_reg(traits<ARCH>::NEXT_PC) = PC_val;
auto is_cont_v = PC_val !=pc.val;
@ -567,8 +543,8 @@ private:
auto cur_pc_val = pc.val;
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = cur_pc_val + 4;
auto PC_val = (static_cast<int64_t>(super::template get_reg<reg_t>(rs1 + traits<ARCH>::X0)) >= static_cast<int64_t>(super::template get_reg<reg_t>(rs2 + traits<ARCH>::X0)))?
(static_cast<int64_t>(cur_pc_val) + (imm)):
auto PC_val = (static_cast<int32_t>(super::template get_reg<reg_t>(rs1 + traits<ARCH>::X0)) >= static_cast<int32_t>(super::template get_reg<reg_t>(rs2 + traits<ARCH>::X0)))?
(static_cast<int32_t>(cur_pc_val) + (imm)):
(cur_pc_val + 4);
super::template get_reg(traits<ARCH>::NEXT_PC) = PC_val;
auto is_cont_v = PC_val !=pc.val;
@ -603,7 +579,7 @@ private:
auto cur_pc_val = pc.val;
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = cur_pc_val + 4;
auto PC_val = (super::template get_reg<reg_t>(rs1 + traits<ARCH>::X0) < super::template get_reg<reg_t>(rs2 + traits<ARCH>::X0))?
(static_cast<int64_t>(cur_pc_val) + (imm)):
(static_cast<int32_t>(cur_pc_val) + (imm)):
(cur_pc_val + 4);
super::template get_reg(traits<ARCH>::NEXT_PC) = PC_val;
auto is_cont_v = PC_val !=pc.val;
@ -638,7 +614,7 @@ private:
auto cur_pc_val = pc.val;
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = cur_pc_val + 4;
auto PC_val = (super::template get_reg<reg_t>(rs1 + traits<ARCH>::X0) >= super::template get_reg<reg_t>(rs2 + traits<ARCH>::X0))?
(static_cast<int64_t>(cur_pc_val) + (imm)):
(static_cast<int32_t>(cur_pc_val) + (imm)):
(cur_pc_val + 4);
super::template get_reg(traits<ARCH>::NEXT_PC) = PC_val;
auto is_cont_v = PC_val !=pc.val;
@ -672,9 +648,9 @@ private:
auto cur_pc_val = pc.val;
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = cur_pc_val + 4;
auto offs_val = (static_cast<int64_t>(super::template get_reg<reg_t>(rs1 + traits<ARCH>::X0)) + (imm));
auto offs_val = (static_cast<int32_t>(super::template get_reg<reg_t>(rs1 + traits<ARCH>::X0)) + (imm));
if(rd != 0){
auto Xtmp0_val = super::template sext<int64_t>(super::template read_mem<uint8_t>(traits<ARCH>::MEM, offs_val));
auto Xtmp0_val = super::template sext<int32_t>(super::template read_mem<uint8_t>(traits<ARCH>::MEM, offs_val));
super::template get_reg<reg_t>(rd + traits<ARCH>::X0)=Xtmp0_val;
}
this->do_sync(POST_SYNC, 10);
@ -706,9 +682,9 @@ private:
auto cur_pc_val = pc.val;
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = cur_pc_val + 4;
auto offs_val = (static_cast<int64_t>(super::template get_reg<reg_t>(rs1 + traits<ARCH>::X0)) + (imm));
auto offs_val = (static_cast<int32_t>(super::template get_reg<reg_t>(rs1 + traits<ARCH>::X0)) + (imm));
if(rd != 0){
auto Xtmp0_val = super::template sext<int64_t>(super::template read_mem<uint16_t>(traits<ARCH>::MEM, offs_val));
auto Xtmp0_val = super::template sext<int32_t>(super::template read_mem<uint16_t>(traits<ARCH>::MEM, offs_val));
super::template get_reg<reg_t>(rd + traits<ARCH>::X0)=Xtmp0_val;
}
this->do_sync(POST_SYNC, 11);
@ -740,9 +716,9 @@ private:
auto cur_pc_val = pc.val;
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = cur_pc_val + 4;
auto offs_val = (static_cast<int64_t>(super::template get_reg<reg_t>(rs1 + traits<ARCH>::X0)) + (imm));
auto offs_val = (static_cast<int32_t>(super::template get_reg<reg_t>(rs1 + traits<ARCH>::X0)) + (imm));
if(rd != 0){
auto Xtmp0_val = super::template sext<int64_t>(super::template read_mem<uint32_t>(traits<ARCH>::MEM, offs_val));
auto Xtmp0_val = super::template sext<int32_t>(super::template read_mem<uint32_t>(traits<ARCH>::MEM, offs_val));
super::template get_reg<reg_t>(rd + traits<ARCH>::X0)=Xtmp0_val;
}
this->do_sync(POST_SYNC, 12);
@ -774,9 +750,9 @@ private:
auto cur_pc_val = pc.val;
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = cur_pc_val + 4;
auto offs_val = (static_cast<int64_t>(super::template get_reg<reg_t>(rs1 + traits<ARCH>::X0)) + (imm));
auto offs_val = (static_cast<int32_t>(super::template get_reg<reg_t>(rs1 + traits<ARCH>::X0)) + (imm));
if(rd != 0){
auto Xtmp0_val = super::template zext<uint64_t>(super::template read_mem<uint8_t>(traits<ARCH>::MEM, offs_val));
auto Xtmp0_val = super::template zext<uint32_t>(super::template read_mem<uint8_t>(traits<ARCH>::MEM, offs_val));
super::template get_reg<reg_t>(rd + traits<ARCH>::X0)=Xtmp0_val;
}
this->do_sync(POST_SYNC, 13);
@ -808,9 +784,9 @@ private:
auto cur_pc_val = pc.val;
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = cur_pc_val + 4;
auto offs_val = (static_cast<int64_t>(super::template get_reg<reg_t>(rs1 + traits<ARCH>::X0)) + (imm));
auto offs_val = (static_cast<int32_t>(super::template get_reg<reg_t>(rs1 + traits<ARCH>::X0)) + (imm));
if(rd != 0){
auto Xtmp0_val = super::template zext<uint64_t>(super::template read_mem<uint16_t>(traits<ARCH>::MEM, offs_val));
auto Xtmp0_val = super::template zext<uint32_t>(super::template read_mem<uint16_t>(traits<ARCH>::MEM, offs_val));
super::template get_reg<reg_t>(rd + traits<ARCH>::X0)=Xtmp0_val;
}
this->do_sync(POST_SYNC, 14);
@ -842,7 +818,7 @@ private:
auto cur_pc_val = pc.val;
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = cur_pc_val + 4;
auto offs_val = (static_cast<int64_t>(super::template get_reg<reg_t>(rs1 + traits<ARCH>::X0)) + (imm));
auto offs_val = (static_cast<int32_t>(super::template get_reg<reg_t>(rs1 + traits<ARCH>::X0)) + (imm));
auto MEMtmp0_val = super::template get_reg<reg_t>(rs2 + traits<ARCH>::X0);
super::write_mem(traits<ARCH>::MEM, offs_val, static_cast<uint8_t>(MEMtmp0_val));
this->do_sync(POST_SYNC, 15);
@ -874,7 +850,7 @@ private:
auto cur_pc_val = pc.val;
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = cur_pc_val + 4;
auto offs_val = (static_cast<int64_t>(super::template get_reg<reg_t>(rs1 + traits<ARCH>::X0)) + (imm));
auto offs_val = (static_cast<int32_t>(super::template get_reg<reg_t>(rs1 + traits<ARCH>::X0)) + (imm));
auto MEMtmp0_val = super::template get_reg<reg_t>(rs2 + traits<ARCH>::X0);
super::write_mem(traits<ARCH>::MEM, offs_val, static_cast<uint16_t>(MEMtmp0_val));
this->do_sync(POST_SYNC, 16);
@ -906,7 +882,7 @@ private:
auto cur_pc_val = pc.val;
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = cur_pc_val + 4;
auto offs_val = (static_cast<int64_t>(super::template get_reg<reg_t>(rs1 + traits<ARCH>::X0)) + (imm));
auto offs_val = (static_cast<int32_t>(super::template get_reg<reg_t>(rs1 + traits<ARCH>::X0)) + (imm));
auto MEMtmp0_val = super::template get_reg<reg_t>(rs2 + traits<ARCH>::X0);
super::write_mem(traits<ARCH>::MEM, offs_val, static_cast<uint32_t>(MEMtmp0_val));
this->do_sync(POST_SYNC, 17);
@ -939,7 +915,7 @@ private:
auto cur_pc_val = pc.val;
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = cur_pc_val + 4;
if(rd != 0){
auto Xtmp0_val = (static_cast<int64_t>(super::template get_reg<reg_t>(rs1 + traits<ARCH>::X0)) + (imm));
auto Xtmp0_val = (static_cast<int32_t>(super::template get_reg<reg_t>(rs1 + traits<ARCH>::X0)) + (imm));
super::template get_reg<reg_t>(rd + traits<ARCH>::X0)=Xtmp0_val;
}
this->do_sync(POST_SYNC, 18);
@ -972,7 +948,7 @@ private:
auto cur_pc_val = pc.val;
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = cur_pc_val + 4;
if(rd != 0){
auto Xtmp0_val = (static_cast<int64_t>(super::template get_reg<reg_t>(rs1 + traits<ARCH>::X0)) < (imm))?
auto Xtmp0_val = (static_cast<int32_t>(super::template get_reg<reg_t>(rs1 + traits<ARCH>::X0)) < (imm))?
1:
0;
super::template get_reg<reg_t>(rd + traits<ARCH>::X0)=Xtmp0_val;
@ -1006,7 +982,7 @@ private:
auto cur_pc_val = pc.val;
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = cur_pc_val + 4;
int64_t full_imm_val = imm;
int32_t full_imm_val = imm;
if(rd != 0){
auto Xtmp0_val = (super::template get_reg<reg_t>(rs1 + traits<ARCH>::X0) < full_imm_val)?
1:
@ -1043,7 +1019,7 @@ private:
auto cur_pc_val = pc.val;
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = cur_pc_val + 4;
if(rd != 0){
auto Xtmp0_val = (static_cast<int64_t>(super::template get_reg<reg_t>(rs1 + traits<ARCH>::X0)) ^ (imm));
auto Xtmp0_val = (static_cast<int32_t>(super::template get_reg<reg_t>(rs1 + traits<ARCH>::X0)) ^ (imm));
super::template get_reg<reg_t>(rd + traits<ARCH>::X0)=Xtmp0_val;
}
this->do_sync(POST_SYNC, 21);
@ -1076,7 +1052,7 @@ private:
auto cur_pc_val = pc.val;
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = cur_pc_val + 4;
if(rd != 0){
auto Xtmp0_val = (static_cast<int64_t>(super::template get_reg<reg_t>(rs1 + traits<ARCH>::X0)) | (imm));
auto Xtmp0_val = (static_cast<int32_t>(super::template get_reg<reg_t>(rs1 + traits<ARCH>::X0)) | (imm));
super::template get_reg<reg_t>(rd + traits<ARCH>::X0)=Xtmp0_val;
}
this->do_sync(POST_SYNC, 22);
@ -1109,7 +1085,7 @@ private:
auto cur_pc_val = pc.val;
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = cur_pc_val + 4;
if(rd != 0){
auto Xtmp0_val = (static_cast<int64_t>(super::template get_reg<reg_t>(rs1 + traits<ARCH>::X0)) & (imm));
auto Xtmp0_val = (static_cast<int32_t>(super::template get_reg<reg_t>(rs1 + traits<ARCH>::X0)) & (imm));
super::template get_reg<reg_t>(rd + traits<ARCH>::X0)=Xtmp0_val;
}
this->do_sync(POST_SYNC, 23);
@ -1130,7 +1106,7 @@ private:
uint8_t rd = ((bit_sub<7,5>(instr)));
uint8_t rs1 = ((bit_sub<15,5>(instr)));
uint8_t shamt = ((bit_sub<20,6>(instr)));
uint8_t shamt = ((bit_sub<20,5>(instr)));
if(this->disass_enabled){
/* generate console output when executing the command */
auto mnemonic = fmt::format(
@ -1141,9 +1117,13 @@ private:
auto cur_pc_val = pc.val;
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = cur_pc_val + 4;
if(rd != 0){
auto Xtmp0_val = (super::template get_reg<reg_t>(rs1 + traits<ARCH>::X0)<<(shamt));
super::template get_reg<reg_t>(rd + traits<ARCH>::X0)=Xtmp0_val;
if(shamt > 31){
raise_trap(0, 0);
} else {
if(rd != 0){
auto Xtmp0_val = (super::template get_reg<reg_t>(rs1 + traits<ARCH>::X0)<<(shamt));
super::template get_reg<reg_t>(rd + traits<ARCH>::X0)=Xtmp0_val;
}
}
this->do_sync(POST_SYNC, 24);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
@ -1163,7 +1143,7 @@ private:
uint8_t rd = ((bit_sub<7,5>(instr)));
uint8_t rs1 = ((bit_sub<15,5>(instr)));
uint8_t shamt = ((bit_sub<20,6>(instr)));
uint8_t shamt = ((bit_sub<20,5>(instr)));
if(this->disass_enabled){
/* generate console output when executing the command */
auto mnemonic = fmt::format(
@ -1174,9 +1154,13 @@ private:
auto cur_pc_val = pc.val;
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = cur_pc_val + 4;
if(rd != 0){
auto Xtmp0_val = (static_cast<uint64_t>(super::template get_reg<reg_t>(rs1 + traits<ARCH>::X0))>>(shamt));
super::template get_reg<reg_t>(rd + traits<ARCH>::X0)=Xtmp0_val;
if(shamt > 31){
raise_trap(0, 0);
} else {
if(rd != 0){
auto Xtmp0_val = (static_cast<uint32_t>(super::template get_reg<reg_t>(rs1 + traits<ARCH>::X0))>>(shamt));
super::template get_reg<reg_t>(rd + traits<ARCH>::X0)=Xtmp0_val;
}
}
this->do_sync(POST_SYNC, 25);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
@ -1196,7 +1180,7 @@ private:
uint8_t rd = ((bit_sub<7,5>(instr)));
uint8_t rs1 = ((bit_sub<15,5>(instr)));
uint8_t shamt = ((bit_sub<20,6>(instr)));
uint8_t shamt = ((bit_sub<20,5>(instr)));
if(this->disass_enabled){
/* generate console output when executing the command */
auto mnemonic = fmt::format(
@ -1207,9 +1191,13 @@ private:
auto cur_pc_val = pc.val;
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = cur_pc_val + 4;
if(rd != 0){
auto Xtmp0_val = (static_cast<int64_t>(super::template get_reg<reg_t>(rs1 + traits<ARCH>::X0))>>(shamt));
super::template get_reg<reg_t>(rd + traits<ARCH>::X0)=Xtmp0_val;
if(shamt > 31){
raise_trap(0, 0);
} else {
if(rd != 0){
auto Xtmp0_val = (static_cast<int32_t>(super::template get_reg<reg_t>(rs1 + traits<ARCH>::X0))>>(shamt));
super::template get_reg<reg_t>(rd + traits<ARCH>::X0)=Xtmp0_val;
}
}
this->do_sync(POST_SYNC, 26);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
@ -1307,7 +1295,7 @@ private:
auto cur_pc_val = pc.val;
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = cur_pc_val + 4;
if(rd != 0){
auto Xtmp0_val = (super::template get_reg<reg_t>(rs1 + traits<ARCH>::X0)<<(super::template get_reg<reg_t>(rs2 + traits<ARCH>::X0) & ((64) - 1)));
auto Xtmp0_val = (super::template get_reg<reg_t>(rs1 + traits<ARCH>::X0)<<(super::template get_reg<reg_t>(rs2 + traits<ARCH>::X0) & ((32) - 1)));
super::template get_reg<reg_t>(rd + traits<ARCH>::X0)=Xtmp0_val;
}
this->do_sync(POST_SYNC, 29);
@ -1340,7 +1328,7 @@ private:
auto cur_pc_val = pc.val;
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = cur_pc_val + 4;
if(rd != 0){
auto Xtmp0_val = (static_cast<int64_t>(super::template get_reg<reg_t>(rs1 + traits<ARCH>::X0)) < static_cast<int64_t>(super::template get_reg<reg_t>(rs2 + traits<ARCH>::X0)))?
auto Xtmp0_val = (static_cast<int32_t>(super::template get_reg<reg_t>(rs1 + traits<ARCH>::X0)) < static_cast<int32_t>(super::template get_reg<reg_t>(rs2 + traits<ARCH>::X0)))?
1:
0;
super::template get_reg<reg_t>(rd + traits<ARCH>::X0)=Xtmp0_val;
@ -1375,7 +1363,7 @@ private:
auto cur_pc_val = pc.val;
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = cur_pc_val + 4;
if(rd != 0){
auto Xtmp0_val = (super::template zext<uint64_t>(super::template get_reg<reg_t>(rs1 + traits<ARCH>::X0)) < super::template zext<uint64_t>(super::template get_reg<reg_t>(rs2 + traits<ARCH>::X0)))?
auto Xtmp0_val = (super::template zext<uint32_t>(super::template get_reg<reg_t>(rs1 + traits<ARCH>::X0)) < super::template zext<uint32_t>(super::template get_reg<reg_t>(rs2 + traits<ARCH>::X0)))?
1:
0;
super::template get_reg<reg_t>(rd + traits<ARCH>::X0)=Xtmp0_val;
@ -1443,7 +1431,7 @@ private:
auto cur_pc_val = pc.val;
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = cur_pc_val + 4;
if(rd != 0){
auto Xtmp0_val = (static_cast<uint64_t>(super::template get_reg<reg_t>(rs1 + traits<ARCH>::X0))>>(super::template get_reg<reg_t>(rs2 + traits<ARCH>::X0) & ((64) - 1)));
auto Xtmp0_val = (static_cast<uint32_t>(super::template get_reg<reg_t>(rs1 + traits<ARCH>::X0))>>(super::template get_reg<reg_t>(rs2 + traits<ARCH>::X0) & ((32) - 1)));
super::template get_reg<reg_t>(rd + traits<ARCH>::X0)=Xtmp0_val;
}
this->do_sync(POST_SYNC, 33);
@ -1476,7 +1464,7 @@ private:
auto cur_pc_val = pc.val;
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = cur_pc_val + 4;
if(rd != 0){
auto Xtmp0_val = (static_cast<int64_t>(super::template get_reg<reg_t>(rs1 + traits<ARCH>::X0))>>(super::template get_reg<reg_t>(rs2 + traits<ARCH>::X0) & ((64) - 1)));
auto Xtmp0_val = (static_cast<int32_t>(super::template get_reg<reg_t>(rs1 + traits<ARCH>::X0))>>(super::template get_reg<reg_t>(rs2 + traits<ARCH>::X0) & ((32) - 1)));
super::template get_reg<reg_t>(rd + traits<ARCH>::X0)=Xtmp0_val;
}
this->do_sync(POST_SYNC, 34);
@ -1573,7 +1561,7 @@ private:
auto cur_pc_val = pc.val;
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = cur_pc_val + 4;
auto FENCEtmp0_val = (((pred) << 4) | (succ));
super::write_mem(traits<ARCH>::FENCE, (0), static_cast<uint64_t>(FENCEtmp0_val));
super::write_mem(traits<ARCH>::FENCE, (0), static_cast<uint32_t>(FENCEtmp0_val));
this->do_sync(POST_SYNC, 37);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
// trap check
@ -1601,7 +1589,7 @@ private:
auto cur_pc_val = pc.val;
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = cur_pc_val + 4;
auto FENCEtmp0_val = (imm);
super::write_mem(traits<ARCH>::FENCE, (1), static_cast<uint64_t>(FENCEtmp0_val));
super::write_mem(traits<ARCH>::FENCE, (1), static_cast<uint32_t>(FENCEtmp0_val));
this->do_sync(POST_SYNC, 38);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
// trap check
@ -1772,9 +1760,9 @@ private:
auto cur_pc_val = pc.val;
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = cur_pc_val + 4;
auto FENCEtmp0_val = (rs1);
super::write_mem(traits<ARCH>::FENCE, (2), static_cast<uint64_t>(FENCEtmp0_val));
super::write_mem(traits<ARCH>::FENCE, (2), static_cast<uint32_t>(FENCEtmp0_val));
auto FENCEtmp1_val = (rs2);
super::write_mem(traits<ARCH>::FENCE, (3), static_cast<uint64_t>(FENCEtmp1_val));
super::write_mem(traits<ARCH>::FENCE, (3), static_cast<uint32_t>(FENCEtmp1_val));
this->do_sync(POST_SYNC, 45);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
// trap check
@ -1806,14 +1794,14 @@ private:
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = cur_pc_val + 4;
auto rs_val_val = super::template get_reg<reg_t>(rs1 + traits<ARCH>::X0);
if(rd != 0){
auto csr_val_val = super::template read_mem<uint64_t>(traits<ARCH>::CSR, (csr));
auto csr_val_val = super::template read_mem<uint32_t>(traits<ARCH>::CSR, (csr));
auto CSRtmp0_val = rs_val_val;
super::write_mem(traits<ARCH>::CSR, (csr), static_cast<uint64_t>(CSRtmp0_val));
super::write_mem(traits<ARCH>::CSR, (csr), static_cast<uint32_t>(CSRtmp0_val));
auto Xtmp1_val = csr_val_val;
super::template get_reg<reg_t>(rd + traits<ARCH>::X0)=Xtmp1_val;
} else {
auto CSRtmp2_val = rs_val_val;
super::write_mem(traits<ARCH>::CSR, (csr), static_cast<uint64_t>(CSRtmp2_val));
super::write_mem(traits<ARCH>::CSR, (csr), static_cast<uint32_t>(CSRtmp2_val));
}
this->do_sync(POST_SYNC, 46);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
@ -1844,7 +1832,7 @@ private:
auto cur_pc_val = pc.val;
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = cur_pc_val + 4;
auto xrd_val = super::template read_mem<uint64_t>(traits<ARCH>::CSR, (csr));
auto xrd_val = super::template read_mem<uint32_t>(traits<ARCH>::CSR, (csr));
auto xrs1_val = super::template get_reg<reg_t>(rs1 + traits<ARCH>::X0);
if(rd != 0){
auto Xtmp0_val = xrd_val;
@ -1852,7 +1840,7 @@ private:
}
if(rs1 != 0){
auto CSRtmp1_val = (xrd_val | xrs1_val);
super::write_mem(traits<ARCH>::CSR, (csr), static_cast<uint64_t>(CSRtmp1_val));
super::write_mem(traits<ARCH>::CSR, (csr), static_cast<uint32_t>(CSRtmp1_val));
}
this->do_sync(POST_SYNC, 47);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
@ -1883,7 +1871,7 @@ private:
auto cur_pc_val = pc.val;
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = cur_pc_val + 4;
auto xrd_val = super::template read_mem<uint64_t>(traits<ARCH>::CSR, (csr));
auto xrd_val = super::template read_mem<uint32_t>(traits<ARCH>::CSR, (csr));
auto xrs1_val = super::template get_reg<reg_t>(rs1 + traits<ARCH>::X0);
if(rd != 0){
auto Xtmp0_val = xrd_val;
@ -1891,7 +1879,7 @@ private:
}
if(rs1 != 0){
auto CSRtmp1_val = (xrd_val & ~(xrs1_val));
super::write_mem(traits<ARCH>::CSR, (csr), static_cast<uint64_t>(CSRtmp1_val));
super::write_mem(traits<ARCH>::CSR, (csr), static_cast<uint32_t>(CSRtmp1_val));
}
this->do_sync(POST_SYNC, 48);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
@ -1923,11 +1911,11 @@ private:
auto cur_pc_val = pc.val;
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = cur_pc_val + 4;
if(rd != 0){
auto Xtmp0_val = super::template read_mem<uint64_t>(traits<ARCH>::CSR, (csr));
auto Xtmp0_val = super::template read_mem<uint32_t>(traits<ARCH>::CSR, (csr));
super::template get_reg<reg_t>(rd + traits<ARCH>::X0)=Xtmp0_val;
}
auto CSRtmp1_val = super::template zext<uint64_t>((zimm));
super::write_mem(traits<ARCH>::CSR, (csr), static_cast<uint64_t>(CSRtmp1_val));
auto CSRtmp1_val = super::template zext<uint32_t>((zimm));
super::write_mem(traits<ARCH>::CSR, (csr), static_cast<uint32_t>(CSRtmp1_val));
this->do_sync(POST_SYNC, 49);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
// trap check
@ -1957,10 +1945,10 @@ private:
auto cur_pc_val = pc.val;
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = cur_pc_val + 4;
auto res_val = super::template read_mem<uint64_t>(traits<ARCH>::CSR, (csr));
auto res_val = super::template read_mem<uint32_t>(traits<ARCH>::CSR, (csr));
if(zimm != 0){
auto CSRtmp0_val = (res_val | super::template zext<uint64_t>((zimm)));
super::write_mem(traits<ARCH>::CSR, (csr), static_cast<uint64_t>(CSRtmp0_val));
auto CSRtmp0_val = (res_val | super::template zext<uint32_t>((zimm)));
super::write_mem(traits<ARCH>::CSR, (csr), static_cast<uint32_t>(CSRtmp0_val));
}
if(rd != 0){
auto Xtmp1_val = res_val;
@ -1995,14 +1983,14 @@ private:
auto cur_pc_val = pc.val;
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = cur_pc_val + 4;
auto res_val = super::template read_mem<uint64_t>(traits<ARCH>::CSR, (csr));
auto res_val = super::template read_mem<uint32_t>(traits<ARCH>::CSR, (csr));
if(rd != 0){
auto Xtmp0_val = res_val;
super::template get_reg<reg_t>(rd + traits<ARCH>::X0)=Xtmp0_val;
}
if(zimm != 0){
auto CSRtmp1_val = (res_val & ~(super::template zext<uint64_t>((zimm))));
super::write_mem(traits<ARCH>::CSR, (csr), static_cast<uint64_t>(CSRtmp1_val));
auto CSRtmp1_val = (res_val & ~(super::template zext<uint32_t>((zimm))));
super::write_mem(traits<ARCH>::CSR, (csr), static_cast<uint32_t>(CSRtmp1_val));
}
this->do_sync(POST_SYNC, 51);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
@ -2016,440 +2004,6 @@ private:
return pc;
}
/* instruction 52: LWU */
compile_ret_t __lwu(virt_addr_t& pc, code_word_t instr){
this->do_sync(PRE_SYNC, 52);
uint8_t rd = ((bit_sub<7,5>(instr)));
uint8_t rs1 = ((bit_sub<15,5>(instr)));
int16_t imm = signextend<int16_t,12>((bit_sub<20,12>(instr)));
if(this->disass_enabled){
/* generate console output when executing the command */
auto mnemonic = fmt::format(
"{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lwu"),
fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1)));
this->core.disass_output(pc.val, mnemonic);
}
auto cur_pc_val = pc.val;
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = cur_pc_val + 4;
auto offs_val = (static_cast<int64_t>(super::template get_reg<reg_t>(rs1 + traits<ARCH>::X0)) + (imm));
if(rd != 0){
auto Xtmp0_val = super::template zext<uint64_t>(super::template read_mem<uint32_t>(traits<ARCH>::MEM, offs_val));
super::template get_reg<reg_t>(rd + traits<ARCH>::X0)=Xtmp0_val;
}
this->do_sync(POST_SYNC, 52);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
// trap check
if(trap_state!=0){
auto& last_br = super::template get_reg<uint32_t>(arch::traits<ARCH>::LAST_BRANCH);
last_br = std::numeric_limits<uint32_t>::max();
super::core.enter_trap(trap_state, cur_pc_val);
}
pc.val=super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC);
return pc;
}
/* instruction 53: LD */
compile_ret_t __ld(virt_addr_t& pc, code_word_t instr){
this->do_sync(PRE_SYNC, 53);
uint8_t rd = ((bit_sub<7,5>(instr)));
uint8_t rs1 = ((bit_sub<15,5>(instr)));
int16_t imm = signextend<int16_t,12>((bit_sub<20,12>(instr)));
if(this->disass_enabled){
/* generate console output when executing the command */
auto mnemonic = fmt::format(
"{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "ld"),
fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1)));
this->core.disass_output(pc.val, mnemonic);
}
auto cur_pc_val = pc.val;
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = cur_pc_val + 4;
auto offs_val = (static_cast<int64_t>(super::template get_reg<reg_t>(rs1 + traits<ARCH>::X0)) + (imm));
if(rd != 0){
auto Xtmp0_val = super::template sext<int64_t>(super::template read_mem<uint64_t>(traits<ARCH>::MEM, offs_val));
super::template get_reg<reg_t>(rd + traits<ARCH>::X0)=Xtmp0_val;
}
this->do_sync(POST_SYNC, 53);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
// trap check
if(trap_state!=0){
auto& last_br = super::template get_reg<uint32_t>(arch::traits<ARCH>::LAST_BRANCH);
last_br = std::numeric_limits<uint32_t>::max();
super::core.enter_trap(trap_state, cur_pc_val);
}
pc.val=super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC);
return pc;
}
/* instruction 54: SD */
compile_ret_t __sd(virt_addr_t& pc, code_word_t instr){
this->do_sync(PRE_SYNC, 54);
int16_t imm = signextend<int16_t,12>((bit_sub<7,5>(instr)) | (bit_sub<25,7>(instr) << 5));
uint8_t rs1 = ((bit_sub<15,5>(instr)));
uint8_t rs2 = ((bit_sub<20,5>(instr)));
if(this->disass_enabled){
/* generate console output when executing the command */
auto mnemonic = fmt::format(
"{mnemonic:10} {rs2}, {imm}({rs1})", fmt::arg("mnemonic", "sd"),
fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1)));
this->core.disass_output(pc.val, mnemonic);
}
auto cur_pc_val = pc.val;
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = cur_pc_val + 4;
auto offs_val = (static_cast<int64_t>(super::template get_reg<reg_t>(rs1 + traits<ARCH>::X0)) + (imm));
auto MEMtmp0_val = super::template get_reg<reg_t>(rs2 + traits<ARCH>::X0);
super::write_mem(traits<ARCH>::MEM, offs_val, static_cast<uint64_t>(MEMtmp0_val));
this->do_sync(POST_SYNC, 54);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
// trap check
if(trap_state!=0){
auto& last_br = super::template get_reg<uint32_t>(arch::traits<ARCH>::LAST_BRANCH);
last_br = std::numeric_limits<uint32_t>::max();
super::core.enter_trap(trap_state, cur_pc_val);
}
pc.val=super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC);
return pc;
}
/* instruction 55: ADDIW */
compile_ret_t __addiw(virt_addr_t& pc, code_word_t instr){
this->do_sync(PRE_SYNC, 55);
uint8_t rd = ((bit_sub<7,5>(instr)));
uint8_t rs1 = ((bit_sub<15,5>(instr)));
int16_t imm = signextend<int16_t,12>((bit_sub<20,12>(instr)));
if(this->disass_enabled){
/* generate console output when executing the command */
auto mnemonic = fmt::format(
"{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "addiw"),
fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm));
this->core.disass_output(pc.val, mnemonic);
}
auto cur_pc_val = pc.val;
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = cur_pc_val + 4;
if(rd != 0){
auto res_val = (static_cast<int32_t>(static_cast<uint32_t>(
super::template get_reg<reg_t>(rs1 + traits<ARCH>::X0)
)) + (imm));
auto Xtmp0_val = super::template sext<int64_t>(res_val);
super::template get_reg<reg_t>(rd + traits<ARCH>::X0)=Xtmp0_val;
}
this->do_sync(POST_SYNC, 55);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
// trap check
if(trap_state!=0){
auto& last_br = super::template get_reg<uint32_t>(arch::traits<ARCH>::LAST_BRANCH);
last_br = std::numeric_limits<uint32_t>::max();
super::core.enter_trap(trap_state, cur_pc_val);
}
pc.val=super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC);
return pc;
}
/* instruction 56: SLLIW */
compile_ret_t __slliw(virt_addr_t& pc, code_word_t instr){
this->do_sync(PRE_SYNC, 56);
uint8_t rd = ((bit_sub<7,5>(instr)));
uint8_t rs1 = ((bit_sub<15,5>(instr)));
uint8_t shamt = ((bit_sub<20,5>(instr)));
if(this->disass_enabled){
/* generate console output when executing the command */
auto mnemonic = fmt::format(
"{mnemonic:10} {rd}, {rs1}, {shamt}", fmt::arg("mnemonic", "slliw"),
fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("shamt", shamt));
this->core.disass_output(pc.val, mnemonic);
}
auto cur_pc_val = pc.val;
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = cur_pc_val + 4;
if(rd != 0){
auto sh_val_val = (static_cast<uint32_t>(
super::template get_reg<reg_t>(rs1 + traits<ARCH>::X0)
)<<(shamt));
auto Xtmp0_val = super::template sext<int64_t>(sh_val_val);
super::template get_reg<reg_t>(rd + traits<ARCH>::X0)=Xtmp0_val;
}
this->do_sync(POST_SYNC, 56);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
// trap check
if(trap_state!=0){
auto& last_br = super::template get_reg<uint32_t>(arch::traits<ARCH>::LAST_BRANCH);
last_br = std::numeric_limits<uint32_t>::max();
super::core.enter_trap(trap_state, cur_pc_val);
}
pc.val=super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC);
return pc;
}
/* instruction 57: SRLIW */
compile_ret_t __srliw(virt_addr_t& pc, code_word_t instr){
this->do_sync(PRE_SYNC, 57);
uint8_t rd = ((bit_sub<7,5>(instr)));
uint8_t rs1 = ((bit_sub<15,5>(instr)));
uint8_t shamt = ((bit_sub<20,5>(instr)));
if(this->disass_enabled){
/* generate console output when executing the command */
auto mnemonic = fmt::format(
"{mnemonic:10} {rd}, {rs1}, {shamt}", fmt::arg("mnemonic", "srliw"),
fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("shamt", shamt));
this->core.disass_output(pc.val, mnemonic);
}
auto cur_pc_val = pc.val;
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = cur_pc_val + 4;
if(rd != 0){
auto sh_val_val = (static_cast<uint32_t>(static_cast<uint32_t>(
super::template get_reg<reg_t>(rs1 + traits<ARCH>::X0)
))>>(shamt));
auto Xtmp0_val = super::template sext<int64_t>(sh_val_val);
super::template get_reg<reg_t>(rd + traits<ARCH>::X0)=Xtmp0_val;
}
this->do_sync(POST_SYNC, 57);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
// trap check
if(trap_state!=0){
auto& last_br = super::template get_reg<uint32_t>(arch::traits<ARCH>::LAST_BRANCH);
last_br = std::numeric_limits<uint32_t>::max();
super::core.enter_trap(trap_state, cur_pc_val);
}
pc.val=super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC);
return pc;
}
/* instruction 58: SRAIW */
compile_ret_t __sraiw(virt_addr_t& pc, code_word_t instr){
this->do_sync(PRE_SYNC, 58);
uint8_t rd = ((bit_sub<7,5>(instr)));
uint8_t rs1 = ((bit_sub<15,5>(instr)));
uint8_t shamt = ((bit_sub<20,5>(instr)));
if(this->disass_enabled){
/* generate console output when executing the command */
auto mnemonic = fmt::format(
"{mnemonic:10} {rd}, {rs1}, {shamt}", fmt::arg("mnemonic", "sraiw"),
fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("shamt", shamt));
this->core.disass_output(pc.val, mnemonic);
}
auto cur_pc_val = pc.val;
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = cur_pc_val + 4;
if(rd != 0){
auto sh_val_val = (static_cast<int32_t>(static_cast<uint32_t>(
super::template get_reg<reg_t>(rs1 + traits<ARCH>::X0)
))>>(shamt));
auto Xtmp0_val = super::template sext<int64_t>(sh_val_val);
super::template get_reg<reg_t>(rd + traits<ARCH>::X0)=Xtmp0_val;
}
this->do_sync(POST_SYNC, 58);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
// trap check
if(trap_state!=0){
auto& last_br = super::template get_reg<uint32_t>(arch::traits<ARCH>::LAST_BRANCH);
last_br = std::numeric_limits<uint32_t>::max();
super::core.enter_trap(trap_state, cur_pc_val);
}
pc.val=super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC);
return pc;
}
/* instruction 59: ADDW */
compile_ret_t __addw(virt_addr_t& pc, code_word_t instr){
this->do_sync(PRE_SYNC, 59);
uint8_t rd = ((bit_sub<7,5>(instr)));
uint8_t rs1 = ((bit_sub<15,5>(instr)));
uint8_t rs2 = ((bit_sub<20,5>(instr)));
if(this->disass_enabled){
/* generate console output when executing the command */
this->core.disass_output(pc.val, "addw");
}
auto cur_pc_val = pc.val;
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = cur_pc_val + 4;
if(rd != 0){
auto res_val = (static_cast<uint32_t>(
super::template get_reg<reg_t>(rs1 + traits<ARCH>::X0)
) + static_cast<uint32_t>(
super::template get_reg<reg_t>(rs2 + traits<ARCH>::X0)
));
auto Xtmp0_val = super::template sext<int64_t>(res_val);
super::template get_reg<reg_t>(rd + traits<ARCH>::X0)=Xtmp0_val;
}
this->do_sync(POST_SYNC, 59);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
// trap check
if(trap_state!=0){
auto& last_br = super::template get_reg<uint32_t>(arch::traits<ARCH>::LAST_BRANCH);
last_br = std::numeric_limits<uint32_t>::max();
super::core.enter_trap(trap_state, cur_pc_val);
}
pc.val=super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC);
return pc;
}
/* instruction 60: SUBW */
compile_ret_t __subw(virt_addr_t& pc, code_word_t instr){
this->do_sync(PRE_SYNC, 60);
uint8_t rd = ((bit_sub<7,5>(instr)));
uint8_t rs1 = ((bit_sub<15,5>(instr)));
uint8_t rs2 = ((bit_sub<20,5>(instr)));
if(this->disass_enabled){
/* generate console output when executing the command */
this->core.disass_output(pc.val, "subw");
}
auto cur_pc_val = pc.val;
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = cur_pc_val + 4;
if(rd != 0){
auto res_val = (static_cast<uint32_t>(
super::template get_reg<reg_t>(rs1 + traits<ARCH>::X0)
) - static_cast<uint32_t>(
super::template get_reg<reg_t>(rs2 + traits<ARCH>::X0)
));
auto Xtmp0_val = super::template sext<int64_t>(res_val);
super::template get_reg<reg_t>(rd + traits<ARCH>::X0)=Xtmp0_val;
}
this->do_sync(POST_SYNC, 60);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
// trap check
if(trap_state!=0){
auto& last_br = super::template get_reg<uint32_t>(arch::traits<ARCH>::LAST_BRANCH);
last_br = std::numeric_limits<uint32_t>::max();
super::core.enter_trap(trap_state, cur_pc_val);
}
pc.val=super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC);
return pc;
}
/* instruction 61: SLLW */
compile_ret_t __sllw(virt_addr_t& pc, code_word_t instr){
this->do_sync(PRE_SYNC, 61);
uint8_t rd = ((bit_sub<7,5>(instr)));
uint8_t rs1 = ((bit_sub<15,5>(instr)));
uint8_t rs2 = ((bit_sub<20,5>(instr)));
if(this->disass_enabled){
/* generate console output when executing the command */
auto mnemonic = fmt::format(
"{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sllw"),
fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
this->core.disass_output(pc.val, mnemonic);
}
auto cur_pc_val = pc.val;
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = cur_pc_val + 4;
if(rd != 0){
uint32_t mask_val = 0x1f;
auto count_val = (static_cast<uint32_t>(
super::template get_reg<reg_t>(rs2 + traits<ARCH>::X0)
) & mask_val);
auto sh_val_val = (static_cast<uint32_t>(
super::template get_reg<reg_t>(rs1 + traits<ARCH>::X0)
)<<count_val);
auto Xtmp0_val = super::template sext<int64_t>(sh_val_val);
super::template get_reg<reg_t>(rd + traits<ARCH>::X0)=Xtmp0_val;
}
this->do_sync(POST_SYNC, 61);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
// trap check
if(trap_state!=0){
auto& last_br = super::template get_reg<uint32_t>(arch::traits<ARCH>::LAST_BRANCH);
last_br = std::numeric_limits<uint32_t>::max();
super::core.enter_trap(trap_state, cur_pc_val);
}
pc.val=super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC);
return pc;
}
/* instruction 62: SRLW */
compile_ret_t __srlw(virt_addr_t& pc, code_word_t instr){
this->do_sync(PRE_SYNC, 62);
uint8_t rd = ((bit_sub<7,5>(instr)));
uint8_t rs1 = ((bit_sub<15,5>(instr)));
uint8_t rs2 = ((bit_sub<20,5>(instr)));
if(this->disass_enabled){
/* generate console output when executing the command */
auto mnemonic = fmt::format(
"{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "srlw"),
fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
this->core.disass_output(pc.val, mnemonic);
}
auto cur_pc_val = pc.val;
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = cur_pc_val + 4;
if(rd != 0){
uint32_t mask_val = 0x1f;
auto count_val = (static_cast<uint32_t>(
super::template get_reg<reg_t>(rs2 + traits<ARCH>::X0)
) & mask_val);
auto sh_val_val = (static_cast<uint32_t>(static_cast<uint32_t>(
super::template get_reg<reg_t>(rs1 + traits<ARCH>::X0)
))>>count_val);
auto Xtmp0_val = super::template sext<int64_t>(sh_val_val);
super::template get_reg<reg_t>(rd + traits<ARCH>::X0)=Xtmp0_val;
}
this->do_sync(POST_SYNC, 62);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
// trap check
if(trap_state!=0){
auto& last_br = super::template get_reg<uint32_t>(arch::traits<ARCH>::LAST_BRANCH);
last_br = std::numeric_limits<uint32_t>::max();
super::core.enter_trap(trap_state, cur_pc_val);
}
pc.val=super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC);
return pc;
}
/* instruction 63: SRAW */
compile_ret_t __sraw(virt_addr_t& pc, code_word_t instr){
this->do_sync(PRE_SYNC, 63);
uint8_t rd = ((bit_sub<7,5>(instr)));
uint8_t rs1 = ((bit_sub<15,5>(instr)));
uint8_t rs2 = ((bit_sub<20,5>(instr)));
if(this->disass_enabled){
/* generate console output when executing the command */
auto mnemonic = fmt::format(
"{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sraw"),
fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
this->core.disass_output(pc.val, mnemonic);
}
auto cur_pc_val = pc.val;
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = cur_pc_val + 4;
if(rd != 0){
uint32_t mask_val = 0x1f;
auto count_val = (static_cast<uint32_t>(
super::template get_reg<reg_t>(rs2 + traits<ARCH>::X0)
) & mask_val);
auto sh_val_val = (static_cast<int32_t>(static_cast<uint32_t>(
super::template get_reg<reg_t>(rs1 + traits<ARCH>::X0)
))>>count_val);
auto Xtmp0_val = super::template sext<int64_t>(sh_val_val);
super::template get_reg<reg_t>(rd + traits<ARCH>::X0)=Xtmp0_val;
}
this->do_sync(POST_SYNC, 63);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
// trap check
if(trap_state!=0){
auto& last_br = super::template get_reg<uint32_t>(arch::traits<ARCH>::LAST_BRANCH);
last_br = std::numeric_limits<uint32_t>::max();
super::core.enter_trap(trap_state, cur_pc_val);
}
pc.val=super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC);
return pc;
}
/****************************************************************************
* end opcode definitions
****************************************************************************/
@ -2509,8 +2063,8 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(virt_addr_t star
} // namespace mnrv32
template <>
std::unique_ptr<vm_if> create<arch::rv64i>(arch::rv64i *core, unsigned short port, bool dump) {
auto ret = new rv64i::vm_impl<arch::rv64i>(*core, dump);
std::unique_ptr<vm_if> create<arch::tgf01>(arch::tgf01 *core, unsigned short port, bool dump) {
auto ret = new tgf01::vm_impl<arch::tgf01>(*core, dump);
if (port != 0) debugger::server<debugger::gdb_session>::run_server(ret, port);
return std::unique_ptr<vm_if>(ret);
}

520
src/vm/interp/vm_mnrv32.cpp → src/vm/interp/vm_tgf02.cpp
View File

@ -31,8 +31,8 @@
*******************************************************************************/
#include "../fp_functions.h"
#include <iss/arch/mnrv32.h>
#include <iss/arch/riscv_hart_msu_vp.h>
#include <iss/arch/tgf02.h>
#include <iss/arch/riscv_hart_m_p.h>
#include <iss/debugger/gdb_session.h>
#include <iss/debugger/server.h>
#include <iss/iss.h>
@ -50,7 +50,7 @@
namespace iss {
namespace interp {
namespace mnrv32 {
namespace tgf02 {
using namespace iss::arch;
using namespace iss::debugger;
@ -167,7 +167,7 @@ private:
compile_func op;
};
const std::array<InstructionDesriptor, 80> instr_descr = {{
const std::array<InstructionDesriptor, 88> instr_descr = {{
/* entries are: size, valid value, valid mask, function ptr */
/* instruction LUI */
{32, 0b00000000000000000000000000110111, 0b00000000000000000000000001111111, &this_class::__lui},
@ -273,6 +273,22 @@ private:
{32, 0b00000000000000000110000001110011, 0b00000000000000000111000001111111, &this_class::__csrrsi},
/* instruction CSRRCI */
{32, 0b00000000000000000111000001110011, 0b00000000000000000111000001111111, &this_class::__csrrci},
/* instruction MUL */
{32, 0b00000010000000000000000000110011, 0b11111110000000000111000001111111, &this_class::__mul},
/* instruction MULH */
{32, 0b00000010000000000001000000110011, 0b11111110000000000111000001111111, &this_class::__mulh},
/* instruction MULHSU */
{32, 0b00000010000000000010000000110011, 0b11111110000000000111000001111111, &this_class::__mulhsu},
/* instruction MULHU */
{32, 0b00000010000000000011000000110011, 0b11111110000000000111000001111111, &this_class::__mulhu},
/* instruction DIV */
{32, 0b00000010000000000100000000110011, 0b11111110000000000111000001111111, &this_class::__div},
/* instruction DIVU */
{32, 0b00000010000000000101000000110011, 0b11111110000000000111000001111111, &this_class::__divu},
/* instruction REM */
{32, 0b00000010000000000110000000110011, 0b11111110000000000111000001111111, &this_class::__rem},
/* instruction REMU */
{32, 0b00000010000000000111000000110011, 0b11111110000000000111000001111111, &this_class::__remu},
/* instruction C.ADDI4SPN */
{16, 0b0000000000000000, 0b1110000000000011, &this_class::__c_addi4spn},
/* instruction C.LW */
@ -2052,10 +2068,334 @@ private:
return pc;
}
/* instruction 52: C.ADDI4SPN */
compile_ret_t __c_addi4spn(virt_addr_t& pc, code_word_t instr){
/* instruction 52: MUL */
compile_ret_t __mul(virt_addr_t& pc, code_word_t instr){
this->do_sync(PRE_SYNC, 52);
uint8_t rd = ((bit_sub<7,5>(instr)));
uint8_t rs1 = ((bit_sub<15,5>(instr)));
uint8_t rs2 = ((bit_sub<20,5>(instr)));
if(this->disass_enabled){
/* generate console output when executing the command */
auto mnemonic = fmt::format(
"{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "mul"),
fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
this->core.disass_output(pc.val, mnemonic);
}
auto cur_pc_val = pc.val;
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = cur_pc_val + 4;
if(rd != 0){
auto res_val = (super::template zext<uint64_t>(super::template get_reg<reg_t>(rs1 + traits<ARCH>::X0)) * super::template zext<uint64_t>(super::template get_reg<reg_t>(rs2 + traits<ARCH>::X0)));
auto Xtmp0_val = super::template zext<uint32_t>(res_val);
super::template get_reg<reg_t>(rd + traits<ARCH>::X0)=Xtmp0_val;
}
this->do_sync(POST_SYNC, 52);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
// trap check
if(trap_state!=0){
auto& last_br = super::template get_reg<uint32_t>(arch::traits<ARCH>::LAST_BRANCH);
last_br = std::numeric_limits<uint32_t>::max();
super::core.enter_trap(trap_state, cur_pc_val);
}
pc.val=super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC);
return pc;
}
/* instruction 53: MULH */
compile_ret_t __mulh(virt_addr_t& pc, code_word_t instr){
this->do_sync(PRE_SYNC, 53);
uint8_t rd = ((bit_sub<7,5>(instr)));
uint8_t rs1 = ((bit_sub<15,5>(instr)));
uint8_t rs2 = ((bit_sub<20,5>(instr)));
if(this->disass_enabled){
/* generate console output when executing the command */
auto mnemonic = fmt::format(
"{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "mulh"),
fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
this->core.disass_output(pc.val, mnemonic);
}
auto cur_pc_val = pc.val;
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = cur_pc_val + 4;
if(rd != 0){
auto res_val = (super::template sext<int64_t>(super::template get_reg<reg_t>(rs1 + traits<ARCH>::X0)) * super::template sext<int64_t>(super::template get_reg<reg_t>(rs2 + traits<ARCH>::X0)));
auto Xtmp0_val = super::template zext<uint32_t>((res_val >> (32)));
super::template get_reg<reg_t>(rd + traits<ARCH>::X0)=Xtmp0_val;
}
this->do_sync(POST_SYNC, 53);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
// trap check
if(trap_state!=0){
auto& last_br = super::template get_reg<uint32_t>(arch::traits<ARCH>::LAST_BRANCH);
last_br = std::numeric_limits<uint32_t>::max();
super::core.enter_trap(trap_state, cur_pc_val);
}
pc.val=super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC);
return pc;
}
/* instruction 54: MULHSU */
compile_ret_t __mulhsu(virt_addr_t& pc, code_word_t instr){
this->do_sync(PRE_SYNC, 54);
uint8_t rd = ((bit_sub<7,5>(instr)));
uint8_t rs1 = ((bit_sub<15,5>(instr)));
uint8_t rs2 = ((bit_sub<20,5>(instr)));
if(this->disass_enabled){
/* generate console output when executing the command */
auto mnemonic = fmt::format(
"{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "mulhsu"),
fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
this->core.disass_output(pc.val, mnemonic);
}
auto cur_pc_val = pc.val;
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = cur_pc_val + 4;
if(rd != 0){
auto res_val = (super::template sext<int64_t>(super::template get_reg<reg_t>(rs1 + traits<ARCH>::X0)) * super::template zext<uint64_t>(super::template get_reg<reg_t>(rs2 + traits<ARCH>::X0)));
auto Xtmp0_val = super::template zext<uint32_t>((res_val >> (32)));
super::template get_reg<reg_t>(rd + traits<ARCH>::X0)=Xtmp0_val;
}
this->do_sync(POST_SYNC, 54);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
// trap check
if(trap_state!=0){
auto& last_br = super::template get_reg<uint32_t>(arch::traits<ARCH>::LAST_BRANCH);
last_br = std::numeric_limits<uint32_t>::max();
super::core.enter_trap(trap_state, cur_pc_val);
}
pc.val=super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC);
return pc;
}
/* instruction 55: MULHU */
compile_ret_t __mulhu(virt_addr_t& pc, code_word_t instr){
this->do_sync(PRE_SYNC, 55);
uint8_t rd = ((bit_sub<7,5>(instr)));
uint8_t rs1 = ((bit_sub<15,5>(instr)));
uint8_t rs2 = ((bit_sub<20,5>(instr)));
if(this->disass_enabled){
/* generate console output when executing the command */
auto mnemonic = fmt::format(
"{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "mulhu"),
fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
this->core.disass_output(pc.val, mnemonic);
}
auto cur_pc_val = pc.val;
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = cur_pc_val + 4;
if(rd != 0){
auto res_val = (super::template zext<uint64_t>(super::template get_reg<reg_t>(rs1 + traits<ARCH>::X0)) * super::template zext<uint64_t>(super::template get_reg<reg_t>(rs2 + traits<ARCH>::X0)));
auto Xtmp0_val = super::template zext<uint32_t>((res_val >> (32)));
super::template get_reg<reg_t>(rd + traits<ARCH>::X0)=Xtmp0_val;
}
this->do_sync(POST_SYNC, 55);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
// trap check
if(trap_state!=0){
auto& last_br = super::template get_reg<uint32_t>(arch::traits<ARCH>::LAST_BRANCH);
last_br = std::numeric_limits<uint32_t>::max();
super::core.enter_trap(trap_state, cur_pc_val);
}
pc.val=super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC);
return pc;
}
/* instruction 56: DIV */
compile_ret_t __div(virt_addr_t& pc, code_word_t instr){
this->do_sync(PRE_SYNC, 56);
uint8_t rd = ((bit_sub<7,5>(instr)));
uint8_t rs1 = ((bit_sub<15,5>(instr)));
uint8_t rs2 = ((bit_sub<20,5>(instr)));
if(this->disass_enabled){
/* generate console output when executing the command */
auto mnemonic = fmt::format(
"{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "div"),
fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
this->core.disass_output(pc.val, mnemonic);
}
auto cur_pc_val = pc.val;
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = cur_pc_val + 4;
if(rd != 0){
{
if((super::template get_reg<reg_t>(rs2 + traits<ARCH>::X0) != 0)) {
uint32_t M1_val = - 1;
uint8_t XLM1_val = 32 - 1;
uint32_t ONE_val = 1;
uint32_t MMIN_val = ONE_val << XLM1_val;
{
if(((super::template get_reg<reg_t>(rs1 + traits<ARCH>::X0) == MMIN_val) && (super::template get_reg<reg_t>(rs2 + traits<ARCH>::X0) == M1_val))) {
auto Xtmp0_val = MMIN_val;
super::template get_reg<reg_t>(rd + traits<ARCH>::X0)=Xtmp0_val;
}
else {
auto Xtmp1_val = (static_cast<int32_t>(super::template get_reg<reg_t>(rs1 + traits<ARCH>::X0)) / static_cast<int32_t>(super::template get_reg<reg_t>(rs2 + traits<ARCH>::X0)));
super::template get_reg<reg_t>(rd + traits<ARCH>::X0)=Xtmp1_val;
}
}
}
else {
auto Xtmp2_val = -(1);
super::template get_reg<reg_t>(rd + traits<ARCH>::X0)=Xtmp2_val;
}
}
}
this->do_sync(POST_SYNC, 56);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
// trap check
if(trap_state!=0){
auto& last_br = super::template get_reg<uint32_t>(arch::traits<ARCH>::LAST_BRANCH);
last_br = std::numeric_limits<uint32_t>::max();
super::core.enter_trap(trap_state, cur_pc_val);
}
pc.val=super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC);
return pc;
}
/* instruction 57: DIVU */
compile_ret_t __divu(virt_addr_t& pc, code_word_t instr){
this->do_sync(PRE_SYNC, 57);
uint8_t rd = ((bit_sub<7,5>(instr)));
uint8_t rs1 = ((bit_sub<15,5>(instr)));
uint8_t rs2 = ((bit_sub<20,5>(instr)));
if(this->disass_enabled){
/* generate console output when executing the command */
auto mnemonic = fmt::format(
"{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "divu"),
fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
this->core.disass_output(pc.val, mnemonic);
}
auto cur_pc_val = pc.val;
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = cur_pc_val + 4;
if(rd != 0){
{
if((super::template get_reg<reg_t>(rs2 + traits<ARCH>::X0) != 0)) {
auto Xtmp0_val = (super::template get_reg<reg_t>(rs1 + traits<ARCH>::X0) / super::template get_reg<reg_t>(rs2 + traits<ARCH>::X0));
super::template get_reg<reg_t>(rd + traits<ARCH>::X0)=Xtmp0_val;
}
else {
auto Xtmp1_val = -(1);
super::template get_reg<reg_t>(rd + traits<ARCH>::X0)=Xtmp1_val;
}
}
}
this->do_sync(POST_SYNC, 57);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
// trap check
if(trap_state!=0){
auto& last_br = super::template get_reg<uint32_t>(arch::traits<ARCH>::LAST_BRANCH);
last_br = std::numeric_limits<uint32_t>::max();
super::core.enter_trap(trap_state, cur_pc_val);
}
pc.val=super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC);
return pc;
}
/* instruction 58: REM */
compile_ret_t __rem(virt_addr_t& pc, code_word_t instr){
this->do_sync(PRE_SYNC, 58);
uint8_t rd = ((bit_sub<7,5>(instr)));
uint8_t rs1 = ((bit_sub<15,5>(instr)));
uint8_t rs2 = ((bit_sub<20,5>(instr)));
if(this->disass_enabled){
/* generate console output when executing the command */
auto mnemonic = fmt::format(
"{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "rem"),
fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
this->core.disass_output(pc.val, mnemonic);
}
auto cur_pc_val = pc.val;
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = cur_pc_val + 4;
if(rd != 0){
{
if((super::template get_reg<reg_t>(rs2 + traits<ARCH>::X0) != 0)) {
uint32_t M1_val = - 1;
uint32_t XLM1_val = 32 - 1;
uint32_t ONE_val = 1;
uint32_t MMIN_val = ONE_val << XLM1_val;
{
if(((super::template get_reg<reg_t>(rs1 + traits<ARCH>::X0) == MMIN_val) && (super::template get_reg<reg_t>(rs2 + traits<ARCH>::X0) == M1_val))) {
auto Xtmp0_val = 0;
super::template get_reg<reg_t>(rd + traits<ARCH>::X0)=Xtmp0_val;
}
else {
auto Xtmp1_val = (static_cast<int32_t>(super::template get_reg<reg_t>(rs1 + traits<ARCH>::X0)) % static_cast<int32_t>(super::template get_reg<reg_t>(rs2 + traits<ARCH>::X0)));
super::template get_reg<reg_t>(rd + traits<ARCH>::X0)=Xtmp1_val;
}
}
}
else {
auto Xtmp2_val = super::template get_reg<reg_t>(rs1 + traits<ARCH>::X0);
super::template get_reg<reg_t>(rd + traits<ARCH>::X0)=Xtmp2_val;
}
}
}
this->do_sync(POST_SYNC, 58);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
// trap check
if(trap_state!=0){
auto& last_br = super::template get_reg<uint32_t>(arch::traits<ARCH>::LAST_BRANCH);
last_br = std::numeric_limits<uint32_t>::max();
super::core.enter_trap(trap_state, cur_pc_val);
}
pc.val=super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC);
return pc;
}
/* instruction 59: REMU */
compile_ret_t __remu(virt_addr_t& pc, code_word_t instr){
this->do_sync(PRE_SYNC, 59);
uint8_t rd = ((bit_sub<7,5>(instr)));
uint8_t rs1 = ((bit_sub<15,5>(instr)));
uint8_t rs2 = ((bit_sub<20,5>(instr)));
if(this->disass_enabled){
/* generate console output when executing the command */
auto mnemonic = fmt::format(
"{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "remu"),
fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
this->core.disass_output(pc.val, mnemonic);
}
auto cur_pc_val = pc.val;
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = cur_pc_val + 4;
if(rd != 0){
{
if((super::template get_reg<reg_t>(rs2 + traits<ARCH>::X0) != 0)) {
auto Xtmp0_val = (super::template get_reg<reg_t>(rs1 + traits<ARCH>::X0) % super::template get_reg<reg_t>(rs2 + traits<ARCH>::X0));
super::template get_reg<reg_t>(rd + traits<ARCH>::X0)=Xtmp0_val;
}
else {
auto Xtmp1_val = super::template get_reg<reg_t>(rs1 + traits<ARCH>::X0);
super::template get_reg<reg_t>(rd + traits<ARCH>::X0)=Xtmp1_val;
}
}
}
this->do_sync(POST_SYNC, 59);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
// trap check
if(trap_state!=0){
auto& last_br = super::template get_reg<uint32_t>(arch::traits<ARCH>::LAST_BRANCH);
last_br = std::numeric_limits<uint32_t>::max();
super::core.enter_trap(trap_state, cur_pc_val);
}
pc.val=super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC);
return pc;
}
/* instruction 60: C.ADDI4SPN */
compile_ret_t __c_addi4spn(virt_addr_t& pc, code_word_t instr){
this->do_sync(PRE_SYNC, 60);
uint8_t rd = ((bit_sub<2,3>(instr)));
uint16_t imm = ((bit_sub<5,1>(instr) << 3) | (bit_sub<6,1>(instr) << 2) | (bit_sub<7,4>(instr) << 6) | (bit_sub<11,2>(instr) << 4));
if(this->disass_enabled){
@ -2073,7 +2413,7 @@ private:
}
auto Xtmp0_val = (super::template get_reg<reg_t>(2 + traits<ARCH>::X0) + (imm));
super::template get_reg<reg_t>(rd + 8 + traits<ARCH>::X0)=Xtmp0_val;
this->do_sync(POST_SYNC, 52);
this->do_sync(POST_SYNC, 60);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
// trap check
if(trap_state!=0){
@ -2085,9 +2425,9 @@ private:
return pc;
}
/* instruction 53: C.LW */
/* instruction 61: C.LW */
compile_ret_t __c_lw(virt_addr_t& pc, code_word_t instr){
this->do_sync(PRE_SYNC, 53);
this->do_sync(PRE_SYNC, 61);
uint8_t rd = ((bit_sub<2,3>(instr)));
uint8_t uimm = ((bit_sub<5,1>(instr) << 6) | (bit_sub<6,1>(instr) << 2) | (bit_sub<10,3>(instr) << 3));
@ -2105,7 +2445,7 @@ private:
auto offs_val = (super::template get_reg<reg_t>(rs1 + 8 + traits<ARCH>::X0) + (uimm));
auto Xtmp0_val = super::template sext<int32_t>(super::template read_mem<uint32_t>(traits<ARCH>::MEM, offs_val));
super::template get_reg<reg_t>(rd + 8 + traits<ARCH>::X0)=Xtmp0_val;
this->do_sync(POST_SYNC, 53);
this->do_sync(POST_SYNC, 61);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
// trap check
if(trap_state!=0){
@ -2117,9 +2457,9 @@ private:
return pc;
}
/* instruction 54: C.SW */
/* instruction 62: C.SW */
compile_ret_t __c_sw(virt_addr_t& pc, code_word_t instr){
this->do_sync(PRE_SYNC, 54);
this->do_sync(PRE_SYNC, 62);
uint8_t rs2 = ((bit_sub<2,3>(instr)));
uint8_t uimm = ((bit_sub<5,1>(instr) << 6) | (bit_sub<6,1>(instr) << 2) | (bit_sub<10,3>(instr) << 3));
@ -2137,7 +2477,7 @@ private:
auto offs_val = (super::template get_reg<reg_t>(rs1 + 8 + traits<ARCH>::X0) + (uimm));
auto MEMtmp0_val = super::template get_reg<reg_t>(rs2 + 8 + traits<ARCH>::X0);
super::write_mem(traits<ARCH>::MEM, offs_val, static_cast<uint32_t>(MEMtmp0_val));
this->do_sync(POST_SYNC, 54);
this->do_sync(POST_SYNC, 62);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
// trap check
if(trap_state!=0){
@ -2149,9 +2489,9 @@ private:
return pc;
}
/* instruction 55: C.ADDI */
/* instruction 63: C.ADDI */
compile_ret_t __c_addi(virt_addr_t& pc, code_word_t instr){
this->do_sync(PRE_SYNC, 55);
this->do_sync(PRE_SYNC, 63);
int8_t imm = signextend<int8_t,6>((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5));
uint8_t rs1 = ((bit_sub<7,5>(instr)));
@ -2167,7 +2507,7 @@ private:
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = cur_pc_val + 2;
auto Xtmp0_val = (static_cast<int32_t>(super::template get_reg<reg_t>(rs1 + traits<ARCH>::X0)) + (imm));
super::template get_reg<reg_t>(rs1 + traits<ARCH>::X0)=Xtmp0_val;
this->do_sync(POST_SYNC, 55);
this->do_sync(POST_SYNC, 63);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
// trap check
if(trap_state!=0){
@ -2179,9 +2519,9 @@ private:
return pc;
}
/* instruction 56: C.NOP */
/* instruction 64: C.NOP */
compile_ret_t __c_nop(virt_addr_t& pc, code_word_t instr){
this->do_sync(PRE_SYNC, 56);
this->do_sync(PRE_SYNC, 64);
if(this->disass_enabled){
/* generate console output when executing the command */
@ -2191,7 +2531,7 @@ private:
auto cur_pc_val = pc.val;
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = cur_pc_val + 2;
/* TODO: describe operations for C.NOP ! */
this->do_sync(POST_SYNC, 56);
this->do_sync(POST_SYNC, 64);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
// trap check
if(trap_state!=0){
@ -2203,9 +2543,9 @@ private:
return pc;
}
/* instruction 57: C.JAL */
/* instruction 65: C.JAL */
compile_ret_t __c_jal(virt_addr_t& pc, code_word_t instr){
this->do_sync(PRE_SYNC, 57);
this->do_sync(PRE_SYNC, 65);
int16_t imm = signextend<int16_t,12>((bit_sub<2,1>(instr) << 5) | (bit_sub<3,3>(instr) << 1) | (bit_sub<6,1>(instr) << 7) | (bit_sub<7,1>(instr) << 6) | (bit_sub<8,1>(instr) << 10) | (bit_sub<9,2>(instr) << 8) | (bit_sub<11,1>(instr) << 4) | (bit_sub<12,1>(instr) << 11));
if(this->disass_enabled){
@ -2224,7 +2564,7 @@ private:
super::template get_reg(traits<ARCH>::NEXT_PC) = PC_val;
auto is_cont_v = PC_val !=pc.val;
super::template get_reg(traits<ARCH>::LAST_BRANCH) = is_cont_v?1:0;
this->do_sync(POST_SYNC, 57);
this->do_sync(POST_SYNC, 65);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
// trap check
if(trap_state!=0){
@ -2236,9 +2576,9 @@ private:
return pc;
}
/* instruction 58: C.LI */
/* instruction 66: C.LI */
compile_ret_t __c_li(virt_addr_t& pc, code_word_t instr){
this->do_sync(PRE_SYNC, 58);
this->do_sync(PRE_SYNC, 66);
int8_t imm = signextend<int8_t,6>((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5));
uint8_t rd = ((bit_sub<7,5>(instr)));
@ -2257,7 +2597,7 @@ private:
}
auto Xtmp0_val = (imm);
super::template get_reg<reg_t>(rd + traits<ARCH>::X0)=Xtmp0_val;
this->do_sync(POST_SYNC, 58);
this->do_sync(POST_SYNC, 66);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
// trap check
if(trap_state!=0){
@ -2269,9 +2609,9 @@ private:
return pc;
}
/* instruction 59: C.LUI */
/* instruction 67: C.LUI */
compile_ret_t __c_lui(virt_addr_t& pc, code_word_t instr){
this->do_sync(PRE_SYNC, 59);
this->do_sync(PRE_SYNC, 67);
int32_t imm = signextend<int32_t,18>((bit_sub<2,5>(instr) << 12) | (bit_sub<12,1>(instr) << 17));
uint8_t rd = ((bit_sub<7,5>(instr)));
@ -2293,7 +2633,7 @@ private:
}
auto Xtmp0_val = (imm);
super::template get_reg<reg_t>(rd + traits<ARCH>::X0)=Xtmp0_val;
this->do_sync(POST_SYNC, 59);
this->do_sync(POST_SYNC, 67);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
// trap check
if(trap_state!=0){
@ -2305,9 +2645,9 @@ private:
return pc;
}
/* instruction 60: C.ADDI16SP */
/* instruction 68: C.ADDI16SP */
compile_ret_t __c_addi16sp(virt_addr_t& pc, code_word_t instr){
this->do_sync(PRE_SYNC, 60);
this->do_sync(PRE_SYNC, 68);
int16_t imm = signextend<int16_t,10>((bit_sub<2,1>(instr) << 5) | (bit_sub<3,2>(instr) << 7) | (bit_sub<5,1>(instr) << 6) | (bit_sub<6,1>(instr) << 4) | (bit_sub<12,1>(instr) << 9));
if(this->disass_enabled){
@ -2322,7 +2662,7 @@ private:
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = cur_pc_val + 2;
auto Xtmp0_val = (static_cast<int32_t>(super::template get_reg<reg_t>(2 + traits<ARCH>::X0)) + (imm));
super::template get_reg<reg_t>(2 + traits<ARCH>::X0)=Xtmp0_val;
this->do_sync(POST_SYNC, 60);
this->do_sync(POST_SYNC, 68);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
// trap check
if(trap_state!=0){
@ -2334,9 +2674,9 @@ private:
return pc;
}
/* instruction 61: C.SRLI */
/* instruction 69: C.SRLI */
compile_ret_t __c_srli(virt_addr_t& pc, code_word_t instr){
this->do_sync(PRE_SYNC, 61);
this->do_sync(PRE_SYNC, 69);
uint8_t shamt = ((bit_sub<2,5>(instr)));
uint8_t rs1 = ((bit_sub<7,3>(instr)));
@ -2353,7 +2693,7 @@ private:
uint8_t rs1_idx_val = rs1 + 8;
auto Xtmp0_val = (static_cast<uint32_t>(super::template get_reg<reg_t>(rs1_idx_val + traits<ARCH>::X0))>>(shamt));
super::template get_reg<reg_t>(rs1_idx_val + traits<ARCH>::X0)=Xtmp0_val;
this->do_sync(POST_SYNC, 61);
this->do_sync(POST_SYNC, 69);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
// trap check
if(trap_state!=0){
@ -2365,9 +2705,9 @@ private:
return pc;
}
/* instruction 62: C.SRAI */
/* instruction 70: C.SRAI */
compile_ret_t __c_srai(virt_addr_t& pc, code_word_t instr){
this->do_sync(PRE_SYNC, 62);
this->do_sync(PRE_SYNC, 70);
uint8_t shamt = ((bit_sub<2,5>(instr)));
uint8_t rs1 = ((bit_sub<7,3>(instr)));
@ -2384,7 +2724,7 @@ private:
uint8_t rs1_idx_val = rs1 + 8;
auto Xtmp0_val = (static_cast<int32_t>(super::template get_reg<reg_t>(rs1_idx_val + traits<ARCH>::X0))>>(shamt));
super::template get_reg<reg_t>(rs1_idx_val + traits<ARCH>::X0)=Xtmp0_val;
this->do_sync(POST_SYNC, 62);
this->do_sync(POST_SYNC, 70);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
// trap check
if(trap_state!=0){
@ -2396,9 +2736,9 @@ private:
return pc;
}
/* instruction 63: C.ANDI */
/* instruction 71: C.ANDI */
compile_ret_t __c_andi(virt_addr_t& pc, code_word_t instr){
this->do_sync(PRE_SYNC, 63);
this->do_sync(PRE_SYNC, 71);
int8_t imm = signextend<int8_t,6>((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5));
uint8_t rs1 = ((bit_sub<7,3>(instr)));
@ -2415,7 +2755,7 @@ private:
uint8_t rs1_idx_val = rs1 + 8;
auto Xtmp0_val = (static_cast<int32_t>(super::template get_reg<reg_t>(rs1_idx_val + traits<ARCH>::X0)) & (imm));
super::template get_reg<reg_t>(rs1_idx_val + traits<ARCH>::X0)=Xtmp0_val;
this->do_sync(POST_SYNC, 63);
this->do_sync(POST_SYNC, 71);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
// trap check
if(trap_state!=0){
@ -2427,9 +2767,9 @@ private:
return pc;
}
/* instruction 64: C.SUB */
/* instruction 72: C.SUB */
compile_ret_t __c_sub(virt_addr_t& pc, code_word_t instr){
this->do_sync(PRE_SYNC, 64);
this->do_sync(PRE_SYNC, 72);
uint8_t rs2 = ((bit_sub<2,3>(instr)));
uint8_t rd = ((bit_sub<7,3>(instr)));
@ -2446,7 +2786,7 @@ private:
uint8_t rd_idx_val = rd + 8;
auto Xtmp0_val = (super::template get_reg<reg_t>(rd_idx_val + traits<ARCH>::X0) - super::template get_reg<reg_t>(rs2 + 8 + traits<ARCH>::X0));
super::template get_reg<reg_t>(rd_idx_val + traits<ARCH>::X0)=Xtmp0_val;
this->do_sync(POST_SYNC, 64);
this->do_sync(POST_SYNC, 72);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
// trap check
if(trap_state!=0){
@ -2458,9 +2798,9 @@ private:
return pc;
}
/* instruction 65: C.XOR */
/* instruction 73: C.XOR */
compile_ret_t __c_xor(virt_addr_t& pc, code_word_t instr){
this->do_sync(PRE_SYNC, 65);
this->do_sync(PRE_SYNC, 73);
uint8_t rs2 = ((bit_sub<2,3>(instr)));
uint8_t rd = ((bit_sub<7,3>(instr)));
@ -2477,7 +2817,7 @@ private:
uint8_t rd_idx_val = rd + 8;
auto Xtmp0_val = (super::template get_reg<reg_t>(rd_idx_val + traits<ARCH>::X0) ^ super::template get_reg<reg_t>(rs2 + 8 + traits<ARCH>::X0));
super::template get_reg<reg_t>(rd_idx_val + traits<ARCH>::X0)=Xtmp0_val;
this->do_sync(POST_SYNC, 65);
this->do_sync(POST_SYNC, 73);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
// trap check
if(trap_state!=0){
@ -2489,9 +2829,9 @@ private:
return pc;
}
/* instruction 66: C.OR */
/* instruction 74: C.OR */
compile_ret_t __c_or(virt_addr_t& pc, code_word_t instr){
this->do_sync(PRE_SYNC, 66);
this->do_sync(PRE_SYNC, 74);
uint8_t rs2 = ((bit_sub<2,3>(instr)));
uint8_t rd = ((bit_sub<7,3>(instr)));
@ -2508,7 +2848,7 @@ private:
uint8_t rd_idx_val = rd + 8;
auto Xtmp0_val = (super::template get_reg<reg_t>(rd_idx_val + traits<ARCH>::X0) | super::template get_reg<reg_t>(rs2 + 8 + traits<ARCH>::X0));
super::template get_reg<reg_t>(rd_idx_val + traits<ARCH>::X0)=Xtmp0_val;
this->do_sync(POST_SYNC, 66);
this->do_sync(POST_SYNC, 74);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
// trap check
if(trap_state!=0){
@ -2520,9 +2860,9 @@ private:
return pc;
}
/* instruction 67: C.AND */
/* instruction 75: C.AND */
compile_ret_t __c_and(virt_addr_t& pc, code_word_t instr){
this->do_sync(PRE_SYNC, 67);
this->do_sync(PRE_SYNC, 75);
uint8_t rs2 = ((bit_sub<2,3>(instr)));
uint8_t rd = ((bit_sub<7,3>(instr)));
@ -2539,7 +2879,7 @@ private:
uint8_t rd_idx_val = rd + 8;
auto Xtmp0_val = (super::template get_reg<reg_t>(rd_idx_val + traits<ARCH>::X0) & super::template get_reg<reg_t>(rs2 + 8 + traits<ARCH>::X0));
super::template get_reg<reg_t>(rd_idx_val + traits<ARCH>::X0)=Xtmp0_val;
this->do_sync(POST_SYNC, 67);
this->do_sync(POST_SYNC, 75);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
// trap check
if(trap_state!=0){
@ -2551,9 +2891,9 @@ private:
return pc;
}
/* instruction 68: C.J */
/* instruction 76: C.J */
compile_ret_t __c_j(virt_addr_t& pc, code_word_t instr){
this->do_sync(PRE_SYNC, 68);
this->do_sync(PRE_SYNC, 76);
int16_t imm = signextend<int16_t,12>((bit_sub<2,1>(instr) << 5) | (bit_sub<3,3>(instr) << 1) | (bit_sub<6,1>(instr) << 7) | (bit_sub<7,1>(instr) << 6) | (bit_sub<8,1>(instr) << 10) | (bit_sub<9,2>(instr) << 8) | (bit_sub<11,1>(instr) << 4) | (bit_sub<12,1>(instr) << 11));
if(this->disass_enabled){
@ -2570,7 +2910,7 @@ private:
super::template get_reg(traits<ARCH>::NEXT_PC) = PC_val;
auto is_cont_v = PC_val !=pc.val;
super::template get_reg(traits<ARCH>::LAST_BRANCH) = is_cont_v?1:0;
this->do_sync(POST_SYNC, 68);
this->do_sync(POST_SYNC, 76);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
// trap check
if(trap_state!=0){
@ -2582,9 +2922,9 @@ private:
return pc;
}
/* instruction 69: C.BEQZ */
/* instruction 77: C.BEQZ */
compile_ret_t __c_beqz(virt_addr_t& pc, code_word_t instr){
this->do_sync(PRE_SYNC, 69);
this->do_sync(PRE_SYNC, 77);
int16_t imm = signextend<int16_t,9>((bit_sub<2,1>(instr) << 5) | (bit_sub<3,2>(instr) << 1) | (bit_sub<5,2>(instr) << 6) | (bit_sub<10,2>(instr) << 3) | (bit_sub<12,1>(instr) << 8));
uint8_t rs1 = ((bit_sub<7,3>(instr)));
@ -2604,7 +2944,7 @@ private:
super::template get_reg(traits<ARCH>::NEXT_PC) = PC_val;
auto is_cont_v = PC_val !=pc.val;
super::template get_reg(traits<ARCH>::LAST_BRANCH) = is_cont_v?1:0;
this->do_sync(POST_SYNC, 69);
this->do_sync(POST_SYNC, 77);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
// trap check
if(trap_state!=0){
@ -2616,9 +2956,9 @@ private:
return pc;
}
/* instruction 70: C.BNEZ */
/* instruction 78: C.BNEZ */
compile_ret_t __c_bnez(virt_addr_t& pc, code_word_t instr){
this->do_sync(PRE_SYNC, 70);
this->do_sync(PRE_SYNC, 78);
int16_t imm = signextend<int16_t,9>((bit_sub<2,1>(instr) << 5) | (bit_sub<3,2>(instr) << 1) | (bit_sub<5,2>(instr) << 6) | (bit_sub<10,2>(instr) << 3) | (bit_sub<12,1>(instr) << 8));
uint8_t rs1 = ((bit_sub<7,3>(instr)));
@ -2638,7 +2978,7 @@ private:
super::template get_reg(traits<ARCH>::NEXT_PC) = PC_val;
auto is_cont_v = PC_val !=pc.val;
super::template get_reg(traits<ARCH>::LAST_BRANCH) = is_cont_v?1:0;
this->do_sync(POST_SYNC, 70);
this->do_sync(POST_SYNC, 78);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
// trap check
if(trap_state!=0){
@ -2650,9 +2990,9 @@ private:
return pc;
}
/* instruction 71: C.SLLI */
/* instruction 79: C.SLLI */
compile_ret_t __c_slli(virt_addr_t& pc, code_word_t instr){
this->do_sync(PRE_SYNC, 71);
this->do_sync(PRE_SYNC, 79);
uint8_t shamt = ((bit_sub<2,5>(instr)));
uint8_t rs1 = ((bit_sub<7,5>(instr)));
@ -2671,7 +3011,7 @@ private:
}
auto Xtmp0_val = (super::template get_reg<reg_t>(rs1 + traits<ARCH>::X0)<<(shamt));
super::template get_reg<reg_t>(rs1 + traits<ARCH>::X0)=Xtmp0_val;
this->do_sync(POST_SYNC, 71);
this->do_sync(POST_SYNC, 79);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
// trap check
if(trap_state!=0){
@ -2683,9 +3023,9 @@ private:
return pc;
}
/* instruction 72: C.LWSP */
/* instruction 80: C.LWSP */
compile_ret_t __c_lwsp(virt_addr_t& pc, code_word_t instr){
this->do_sync(PRE_SYNC, 72);
this->do_sync(PRE_SYNC, 80);
uint8_t uimm = ((bit_sub<2,2>(instr) << 6) | (bit_sub<4,3>(instr) << 2) | (bit_sub<12,1>(instr) << 5));
uint8_t rd = ((bit_sub<7,5>(instr)));
@ -2702,7 +3042,7 @@ private:
auto offs_val = (super::template get_reg<reg_t>(2 + traits<ARCH>::X0) + (uimm));
auto Xtmp0_val = super::template sext<int32_t>(super::template read_mem<uint32_t>(traits<ARCH>::MEM, offs_val));
super::template get_reg<reg_t>(rd + traits<ARCH>::X0)=Xtmp0_val;
this->do_sync(POST_SYNC, 72);
this->do_sync(POST_SYNC, 80);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
// trap check
if(trap_state!=0){
@ -2714,9 +3054,9 @@ private:
return pc;
}
/* instruction 73: C.MV */
/* instruction 81: C.MV */
compile_ret_t __c_mv(virt_addr_t& pc, code_word_t instr){
this->do_sync(PRE_SYNC, 73);
this->do_sync(PRE_SYNC, 81);
uint8_t rs2 = ((bit_sub<2,5>(instr)));
uint8_t rd = ((bit_sub<7,5>(instr)));
@ -2732,7 +3072,7 @@ private:
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = cur_pc_val + 2;
auto Xtmp0_val = super::template get_reg<reg_t>(rs2 + traits<ARCH>::X0);
super::template get_reg<reg_t>(rd + traits<ARCH>::X0)=Xtmp0_val;
this->do_sync(POST_SYNC, 73);
this->do_sync(POST_SYNC, 81);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
// trap check
if(trap_state!=0){
@ -2744,9 +3084,9 @@ private:
return pc;
}
/* instruction 74: C.JR */
/* instruction 82: C.JR */
compile_ret_t __c_jr(virt_addr_t& pc, code_word_t instr){
this->do_sync(PRE_SYNC, 74);
this->do_sync(PRE_SYNC, 82);
uint8_t rs1 = ((bit_sub<7,5>(instr)));
if(this->disass_enabled){
@ -2762,7 +3102,7 @@ private:
auto PC_val = super::template get_reg<reg_t>(rs1 + traits<ARCH>::X0);
super::template get_reg(traits<ARCH>::NEXT_PC) = PC_val;
super::template get_reg(traits<ARCH>::LAST_BRANCH) = std::numeric_limits<uint32_t>::max();
this->do_sync(POST_SYNC, 74);
this->do_sync(POST_SYNC, 82);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
// trap check
if(trap_state!=0){
@ -2774,9 +3114,9 @@ private:
return pc;
}
/* instruction 75: C.ADD */
/* instruction 83: C.ADD */
compile_ret_t __c_add(virt_addr_t& pc, code_word_t instr){
this->do_sync(PRE_SYNC, 75);
this->do_sync(PRE_SYNC, 83);
uint8_t rs2 = ((bit_sub<2,5>(instr)));
uint8_t rd = ((bit_sub<7,5>(instr)));
@ -2792,7 +3132,7 @@ private:
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = cur_pc_val + 2;
auto Xtmp0_val = (super::template get_reg<reg_t>(rd + traits<ARCH>::X0) + super::template get_reg<reg_t>(rs2 + traits<ARCH>::X0));
super::template get_reg<reg_t>(rd + traits<ARCH>::X0)=Xtmp0_val;
this->do_sync(POST_SYNC, 75);
this->do_sync(POST_SYNC, 83);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
// trap check
if(trap_state!=0){
@ -2804,9 +3144,9 @@ private:
return pc;
}
/* instruction 76: C.JALR */
/* instruction 84: C.JALR */
compile_ret_t __c_jalr(virt_addr_t& pc, code_word_t instr){
this->do_sync(PRE_SYNC, 76);
this->do_sync(PRE_SYNC, 84);
uint8_t rs1 = ((bit_sub<7,5>(instr)));
if(this->disass_enabled){
@ -2824,7 +3164,7 @@ private:
auto PC_val = super::template get_reg<reg_t>(rs1 + traits<ARCH>::X0);
super::template get_reg(traits<ARCH>::NEXT_PC) = PC_val;
super::template get_reg(traits<ARCH>::LAST_BRANCH) = std::numeric_limits<uint32_t>::max();
this->do_sync(POST_SYNC, 76);
this->do_sync(POST_SYNC, 84);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
// trap check
if(trap_state!=0){
@ -2836,9 +3176,9 @@ private:
return pc;
}
/* instruction 77: C.EBREAK */
/* instruction 85: C.EBREAK */
compile_ret_t __c_ebreak(virt_addr_t& pc, code_word_t instr){
this->do_sync(PRE_SYNC, 77);
this->do_sync(PRE_SYNC, 85);
if(this->disass_enabled){
/* generate console output when executing the command */
@ -2848,7 +3188,7 @@ private:
auto cur_pc_val = pc.val;
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = cur_pc_val + 2;
raise_trap(0, 3);
this->do_sync(POST_SYNC, 77);
this->do_sync(POST_SYNC, 85);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
// trap check
if(trap_state!=0){
@ -2860,9 +3200,9 @@ private:
return pc;
}
/* instruction 78: C.SWSP */
/* instruction 86: C.SWSP */
compile_ret_t __c_swsp(virt_addr_t& pc, code_word_t instr){
this->do_sync(PRE_SYNC, 78);
this->do_sync(PRE_SYNC, 86);
uint8_t rs2 = ((bit_sub<2,5>(instr)));
uint8_t uimm = ((bit_sub<7,2>(instr) << 6) | (bit_sub<9,4>(instr) << 2));
@ -2879,7 +3219,7 @@ private:
auto offs_val = (super::template get_reg<reg_t>(2 + traits<ARCH>::X0) + (uimm));
auto MEMtmp0_val = super::template get_reg<reg_t>(rs2 + traits<ARCH>::X0);
super::write_mem(traits<ARCH>::MEM, offs_val, static_cast<uint32_t>(MEMtmp0_val));
this->do_sync(POST_SYNC, 78);
this->do_sync(POST_SYNC, 86);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
// trap check
if(trap_state!=0){
@ -2891,9 +3231,9 @@ private:
return pc;
}
/* instruction 79: DII */
/* instruction 87: DII */
compile_ret_t __dii(virt_addr_t& pc, code_word_t instr){
this->do_sync(PRE_SYNC, 79);
this->do_sync(PRE_SYNC, 87);
if(this->disass_enabled){
/* generate console output when executing the command */
@ -2903,7 +3243,7 @@ private:
auto cur_pc_val = pc.val;
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = cur_pc_val + 2;
raise_trap(0, 2);
this->do_sync(POST_SYNC, 79);
this->do_sync(POST_SYNC, 87);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
// trap check
if(trap_state!=0){
@ -2974,8 +3314,8 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(virt_addr_t star
} // namespace mnrv32
template <>
std::unique_ptr<vm_if> create<arch::mnrv32>(arch::mnrv32 *core, unsigned short port, bool dump) {
auto ret = new mnrv32::vm_impl<arch::mnrv32>(*core, dump);
std::unique_ptr<vm_if> create<arch::tgf02>(arch::tgf02 *core, unsigned short port, bool dump) {
auto ret = new tgf02::vm_impl<arch::tgf02>(*core, dump);
if (port != 0) debugger::server<debugger::gdb_session>::run_server(ret, port);
return std::unique_ptr<vm_if>(ret);
}