change source code to unified layout
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@@ -38,7 +38,7 @@
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#include <iss/iss.h>
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#include <iss/vm_types.h>
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#include <iss/plugin/loader.h>
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#include <sysc/core_complex.h>
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#include "core_complex.h"
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#include <iss/arch/tgc_mapper.h>
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#include <scc/report.h>
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#include <util/ities.h>
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201
src/sysc/core_complex.h
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201
src/sysc/core_complex.h
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/*******************************************************************************
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* Copyright (C) 2017-2021 MINRES Technologies GmbH
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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*******************************************************************************/
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#ifndef _SYSC_CORE_COMPLEX_H_
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#define _SYSC_CORE_COMPLEX_H_
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#include <tlm/scc/initiator_mixin.h>
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#include <scc/traceable.h>
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#include <scc/tick2time.h>
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#include <scc/utilities.h>
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#include <tlm/scc/scv/tlm_rec_initiator_socket.h>
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#ifdef CWR_SYSTEMC
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#include <scmlinc/scml_property.h>
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#else
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#include <cci_configuration>
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#endif
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#include <tlm>
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#include <tlm_utils/tlm_quantumkeeper.h>
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#include <util/range_lut.h>
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#include <memory>
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namespace iss {
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class vm_plugin;
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}
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namespace sysc {
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class tlm_dmi_ext : public tlm::tlm_dmi {
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public:
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bool operator==(const tlm_dmi_ext &o) const {
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return this->get_granted_access() == o.get_granted_access() &&
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this->get_start_address() == o.get_start_address() && this->get_end_address() == o.get_end_address();
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}
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bool operator!=(const tlm_dmi_ext &o) const { return !operator==(o); }
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};
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namespace tgfs {
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class core_wrapper;
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struct core_trace;
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class core_complex : public sc_core::sc_module, public scc::traceable {
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public:
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tlm::scc::initiator_mixin<tlm::scc::scv::tlm_rec_initiator_socket<32>> initiator{"intor"};
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sc_core::sc_in<bool> rst_i{"rst_i"};
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sc_core::sc_in<bool> global_irq_i{"global_irq_i"};
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sc_core::sc_in<bool> timer_irq_i{"timer_irq_i"};
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sc_core::sc_in<bool> sw_irq_i{"sw_irq_i"};
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sc_core::sc_vector<sc_core::sc_in<bool>> local_irq_i{"local_irq_i", 16};
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#ifndef CWR_SYSTEMC
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sc_core::sc_in<sc_core::sc_time> clk_i{"clk_i"};
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sc_core::sc_port<tlm::tlm_peek_if<uint64_t>, 1, sc_core::SC_ZERO_OR_MORE_BOUND> mtime_o;
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cci::cci_param<std::string> elf_file{"elf_file", ""};
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cci::cci_param<bool> enable_disass{"enable_disass", false};
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cci::cci_param<uint64_t> reset_address{"reset_address", 0ULL};
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cci::cci_param<std::string> core_type{"core_type", "tgc_c"};
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cci::cci_param<std::string> backend{"backend", "interp"};
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cci::cci_param<unsigned short> gdb_server_port{"gdb_server_port", 0};
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cci::cci_param<bool> dump_ir{"dump_ir", false};
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cci::cci_param<uint32_t> mhartid{"mhartid", 0};
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cci::cci_param<std::string> plugins{"plugins", ""};
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core_complex(sc_core::sc_module_name const& name);
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#else
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sc_core::sc_in<bool> clk_i{"clk_i"};
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sc_core::sc_in<uint64_t> mtime_i{"mtime_i"};
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scml_property<std::string> elf_file{"elf_file", ""};
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scml_property<bool> enable_disass{"enable_disass", false};
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scml_property<unsigned long long> reset_address{"reset_address", 0ULL};
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scml_property<std::string> core_type{"core_type", "tgc_c"};
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scml_property<std::string> backend{"backend", "interp"};
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scml_property<unsigned> gdb_server_port{"gdb_server_port", 0};
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scml_property<bool> dump_ir{"dump_ir", false};
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scml_property<uint32_t> mhartid{"mhartid", 0};
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scml_property<std::string> plugins{"plugins", ""};
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core_complex(sc_core::sc_module_name const& name)
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: sc_module(name)
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, local_irq_i{"local_irq_i", 16}
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, elf_file{"elf_file", ""}
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, enable_disass{"enable_disass", false}
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, reset_address{"reset_address", 0ULL}
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, core_type{"core_type", "tgc_c"}
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, backend{"backend", "interp"}
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, gdb_server_port{"gdb_server_port", 0}
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, dump_ir{"dump_ir", false}
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, mhartid{"mhartid", 0}
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, read_lut(tlm_dmi_ext())
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, write_lut(tlm_dmi_ext())
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{
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init();
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}
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#endif
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~core_complex();
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inline void sync(uint64_t cycle) {
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auto time = curr_clk * (cycle - last_sync_cycle);
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quantum_keeper.inc(time);
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if (quantum_keeper.need_sync()) {
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wait(quantum_keeper.get_local_time());
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quantum_keeper.reset();
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}
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last_sync_cycle = cycle;
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}
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bool read_mem(uint64_t addr, unsigned length, uint8_t *const data, bool is_fetch);
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bool write_mem(uint64_t addr, unsigned length, const uint8_t *const data);
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bool read_mem_dbg(uint64_t addr, unsigned length, uint8_t *const data);
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bool write_mem_dbg(uint64_t addr, unsigned length, const uint8_t *const data);
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void trace(sc_core::sc_trace_file *trf) const override;
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bool disass_output(uint64_t pc, const std::string instr);
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void set_clock_period(sc_core::sc_time period);
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protected:
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void before_end_of_elaboration() override;
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void start_of_simulation() override;
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void forward();
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void run();
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void rst_cb();
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void sw_irq_cb();
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void timer_irq_cb();
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void global_irq_cb();
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uint64_t last_sync_cycle = 0;
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util::range_lut<tlm_dmi_ext> read_lut, write_lut;
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tlm_utils::tlm_quantumkeeper quantum_keeper;
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std::vector<uint8_t> write_buf;
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core_wrapper* cpu{nullptr};
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sc_core::sc_signal<sc_core::sc_time> curr_clk;
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core_trace* trc{nullptr};
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std::unique_ptr<scc::tick2time> t2t;
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private:
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void init();
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std::vector<iss::vm_plugin *> plugin_list;
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};
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} /* namespace SiFive */
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} /* namespace sysc */
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#endif /* _SYSC_CORE_COMPLEX_H_ */
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