change source code to unified layout
This commit is contained in:
1
src/iss/arch/.gitignore
vendored
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1
src/iss/arch/.gitignore
vendored
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@ -0,0 +1 @@
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/tgc_*.h
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100
src/iss/arch/hwl.h
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100
src/iss/arch/hwl.h
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/*******************************************************************************
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* Copyright (C) 2022 MINRES Technologies GmbH
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* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of the copyright holder nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
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||||
*
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* Contributors:
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* eyck@minres.com - initial implementation
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******************************************************************************/
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#ifndef _RISCV_HART_M_P_HWL_H
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#define _RISCV_HART_M_P_HWL_H
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#include <iss/vm_types.h>
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namespace iss {
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namespace arch {
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template <typename BASE> class hwl : public BASE {
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public:
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using base_class = BASE;
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using this_class = hwl<BASE>;
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using reg_t = typename BASE::reg_t;
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hwl();
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virtual ~hwl() = default;
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protected:
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iss::status read_custom_csr_reg(unsigned addr, reg_t &val) override;
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iss::status write_custom_csr_reg(unsigned addr, reg_t val) override;
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};
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template<typename BASE>
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inline hwl<BASE>::hwl() {
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for (unsigned addr = 0x800; addr < 0x803; ++addr){
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this->register_custom_csr_rd(addr);
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this->register_custom_csr_wr(addr);
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}
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for (unsigned addr = 0x804; addr < 0x807; ++addr){
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this->register_custom_csr_rd(addr);
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this->register_custom_csr_wr(addr);
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}
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}
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template<typename BASE>
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inline iss::status iss::arch::hwl<BASE>::read_custom_csr_reg(unsigned addr, reg_t &val) {
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switch(addr){
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case 0x800: val = this->reg.lpstart0; break;
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case 0x801: val = this->reg.lpend0; break;
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case 0x802: val = this->reg.lpcount0; break;
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case 0x804: val = this->reg.lpstart1; break;
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case 0x805: val = this->reg.lpend1; break;
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case 0x806: val = this->reg.lpcount1; break;
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}
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return iss::Ok;
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}
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template<typename BASE>
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inline iss::status iss::arch::hwl<BASE>::write_custom_csr_reg(unsigned addr, reg_t val) {
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switch(addr){
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case 0x800: this->reg.lpstart0 = val; break;
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case 0x801: this->reg.lpend0 = val; break;
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case 0x802: this->reg.lpcount0 = val; break;
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case 0x804: this->reg.lpstart1 = val; break;
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case 0x805: this->reg.lpend1 = val; break;
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case 0x806: this->reg.lpcount1 = val; break;
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}
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return iss::Ok;
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}
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} // namespace arch
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} // namespace iss
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#endif /* _RISCV_HART_M_P_H */
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296
src/iss/arch/riscv_hart_common.h
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296
src/iss/arch/riscv_hart_common.h
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@ -0,0 +1,296 @@
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/*******************************************************************************
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* Copyright (C) 2017, 2018, 2021 MINRES Technologies GmbH
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* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of the copyright holder nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
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* Contributors:
|
||||
* eyck@minres.com - initial implementation
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******************************************************************************/
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#ifndef _RISCV_HART_COMMON
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#define _RISCV_HART_COMMON
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#include "iss/arch_if.h"
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#include <cstdint>
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namespace iss {
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namespace arch {
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enum { tohost_dflt = 0xF0001000, fromhost_dflt = 0xF0001040 };
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enum features_e{FEAT_NONE, FEAT_PMP=1, FEAT_EXT_N=2, FEAT_CLIC=4, FEAT_DEBUG=8, FEAT_TCM=16};
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enum riscv_csr {
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/* user-level CSR */
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// User Trap Setup
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ustatus = 0x000,
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uie = 0x004,
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utvec = 0x005,
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// User Trap Handling
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uscratch = 0x040,
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uepc = 0x041,
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ucause = 0x042,
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utval = 0x043,
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uip = 0x044,
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// User Floating-Point CSRs
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fflags = 0x001,
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frm = 0x002,
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fcsr = 0x003,
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// User Counter/Timers
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cycle = 0xC00,
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time = 0xC01,
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instret = 0xC02,
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hpmcounter3 = 0xC03,
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hpmcounter4 = 0xC04,
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/*...*/
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hpmcounter31 = 0xC1F,
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cycleh = 0xC80,
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timeh = 0xC81,
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instreth = 0xC82,
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hpmcounter3h = 0xC83,
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hpmcounter4h = 0xC84,
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/*...*/
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hpmcounter31h = 0xC9F,
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/* supervisor-level CSR */
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// Supervisor Trap Setup
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sstatus = 0x100,
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sedeleg = 0x102,
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sideleg = 0x103,
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sie = 0x104,
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stvec = 0x105,
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scounteren = 0x106,
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// Supervisor Trap Handling
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sscratch = 0x140,
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sepc = 0x141,
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scause = 0x142,
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stval = 0x143,
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sip = 0x144,
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// Supervisor Protection and Translation
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satp = 0x180,
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/* machine-level CSR */
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// Machine Information Registers
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mvendorid = 0xF11,
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marchid = 0xF12,
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mimpid = 0xF13,
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mhartid = 0xF14,
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// Machine Trap Setup
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mstatus = 0x300,
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misa = 0x301,
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medeleg = 0x302,
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mideleg = 0x303,
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mie = 0x304,
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mtvec = 0x305,
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mcounteren = 0x306,
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mtvt = 0x307, //CLIC
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// Machine Trap Handling
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mscratch = 0x340,
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mepc = 0x341,
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mcause = 0x342,
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mtval = 0x343,
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mip = 0x344,
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mxnti = 0x345, //CLIC
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mintstatus = 0x346, // MRW Current interrupt levels (CLIC) - addr subject to change
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mscratchcsw = 0x348, // MRW Conditional scratch swap on priv mode change (CLIC)
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mscratchcswl = 0x349, // MRW Conditional scratch swap on level change (CLIC)
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mintthresh = 0x350, // MRW Interrupt-level threshold (CLIC) - addr subject to change
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mclicbase = 0x351, // MRW Base address for CLIC memory mapped registers (CLIC) - addr subject to change
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// Physical Memory Protection
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pmpcfg0 = 0x3A0,
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pmpcfg1 = 0x3A1,
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pmpcfg2 = 0x3A2,
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pmpcfg3 = 0x3A3,
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pmpaddr0 = 0x3B0,
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pmpaddr1 = 0x3B1,
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pmpaddr2 = 0x3B2,
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pmpaddr3 = 0x3B3,
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pmpaddr4 = 0x3B4,
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pmpaddr5 = 0x3B5,
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pmpaddr6 = 0x3B6,
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pmpaddr7 = 0x3B7,
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pmpaddr8 = 0x3B8,
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pmpaddr9 = 0x3B9,
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pmpaddr10 = 0x3BA,
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pmpaddr11 = 0x3BB,
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pmpaddr12 = 0x3BC,
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pmpaddr13 = 0x3BD,
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pmpaddr14 = 0x3BE,
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pmpaddr15 = 0x3BF,
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// Machine Counter/Timers
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mcycle = 0xB00,
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minstret = 0xB02,
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mhpmcounter3 = 0xB03,
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mhpmcounter4 = 0xB04,
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/*...*/
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mhpmcounter31 = 0xB1F,
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mcycleh = 0xB80,
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minstreth = 0xB82,
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mhpmcounter3h = 0xB83,
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mhpmcounter4h = 0xB84,
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/*...*/
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mhpmcounter31h = 0xB9F,
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// Machine Counter Setup
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mhpmevent3 = 0x323,
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mhpmevent4 = 0x324,
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/*...*/
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mhpmevent31 = 0x33F,
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// Debug/Trace Registers (shared with Debug Mode)
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tselect = 0x7A0,
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tdata1 = 0x7A1,
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tdata2 = 0x7A2,
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tdata3 = 0x7A3,
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// Debug Mode Registers
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dcsr = 0x7B0,
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dpc = 0x7B1,
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dscratch0 = 0x7B2,
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dscratch1 = 0x7B3
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};
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enum {
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PGSHIFT = 12,
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PTE_PPN_SHIFT = 10,
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// page table entry (PTE) fields
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PTE_V = 0x001, // Valid
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PTE_R = 0x002, // Read
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PTE_W = 0x004, // Write
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PTE_X = 0x008, // Execute
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PTE_U = 0x010, // User
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PTE_G = 0x020, // Global
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PTE_A = 0x040, // Accessed
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PTE_D = 0x080, // Dirty
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PTE_SOFT = 0x300 // Reserved for Software
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};
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template <typename T> inline bool PTE_TABLE(T PTE) { return (((PTE) & (PTE_V | PTE_R | PTE_W | PTE_X)) == PTE_V); }
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enum { PRIV_U = 0, PRIV_S = 1, PRIV_M = 3, PRIV_D = 4};
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enum {
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ISA_A = 1,
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ISA_B = 1 << 1,
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ISA_C = 1 << 2,
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ISA_D = 1 << 3,
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||||
ISA_E = 1 << 4,
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ISA_F = 1 << 5,
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ISA_G = 1 << 6,
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ISA_I = 1 << 8,
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ISA_M = 1 << 12,
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ISA_N = 1 << 13,
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ISA_Q = 1 << 16,
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||||
ISA_S = 1 << 18,
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ISA_U = 1 << 20
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};
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struct vm_info {
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int levels;
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int idxbits;
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int ptesize;
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uint64_t ptbase;
|
||||
bool is_active() { return levels; }
|
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};
|
||||
|
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struct feature_config {
|
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uint64_t clic_base{0xc0000000};
|
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unsigned clic_num_irq{16};
|
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unsigned clic_num_trigger{0};
|
||||
uint64_t tcm_base{0x10000000};
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uint64_t tcm_size{0x8000};
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||||
};
|
||||
|
||||
class trap_load_access_fault : public trap_access {
|
||||
public:
|
||||
trap_load_access_fault(uint64_t badaddr)
|
||||
: trap_access(5 << 16, badaddr) {}
|
||||
};
|
||||
class illegal_instruction_fault : public trap_access {
|
||||
public:
|
||||
illegal_instruction_fault(uint64_t badaddr)
|
||||
: trap_access(2 << 16, badaddr) {}
|
||||
};
|
||||
class trap_instruction_page_fault : public trap_access {
|
||||
public:
|
||||
trap_instruction_page_fault(uint64_t badaddr)
|
||||
: trap_access(12 << 16, badaddr) {}
|
||||
};
|
||||
class trap_load_page_fault : public trap_access {
|
||||
public:
|
||||
trap_load_page_fault(uint64_t badaddr)
|
||||
: trap_access(13 << 16, badaddr) {}
|
||||
};
|
||||
class trap_store_page_fault : public trap_access {
|
||||
public:
|
||||
trap_store_page_fault(uint64_t badaddr)
|
||||
: trap_access(15 << 16, badaddr) {}
|
||||
};
|
||||
|
||||
inline void read_reg_uint32(uint64_t offs, uint32_t& reg, uint8_t *const data, unsigned length) {
|
||||
auto reg_ptr = reinterpret_cast<uint8_t*>(®);
|
||||
switch (offs & 0x3) {
|
||||
case 0:
|
||||
for (auto i = 0U; i < length; ++i)
|
||||
*(data + i) = *(reg_ptr + i);
|
||||
break;
|
||||
case 1:
|
||||
for (auto i = 0U; i < length; ++i)
|
||||
*(data + i) = *(reg_ptr + 1 + i);
|
||||
break;
|
||||
case 2:
|
||||
for (auto i = 0U; i < length; ++i)
|
||||
*(data + i) = *(reg_ptr + 2 + i);
|
||||
break;
|
||||
case 3:
|
||||
*data = *(reg_ptr + 3);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
inline void write_reg_uint32(uint64_t offs, uint32_t& reg, const uint8_t *const data, unsigned length) {
|
||||
auto reg_ptr = reinterpret_cast<uint8_t*>(®);
|
||||
switch (offs & 0x3) {
|
||||
case 0:
|
||||
for (auto i = 0U; i < length; ++i)
|
||||
*(reg_ptr + i) = *(data + i);
|
||||
break;
|
||||
case 1:
|
||||
for (auto i = 0U; i < length; ++i)
|
||||
*(reg_ptr + 1 + i) = *(data + i);
|
||||
break;
|
||||
case 2:
|
||||
for (auto i = 0U; i < length; ++i)
|
||||
*(reg_ptr + 2 + i) = *(data + i);
|
||||
break;
|
||||
case 3:
|
||||
*(reg_ptr + 3) = *data ;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
#endif
|
1219
src/iss/arch/riscv_hart_m_p.h
Normal file
1219
src/iss/arch/riscv_hart_m_p.h
Normal file
File diff suppressed because it is too large
Load Diff
1422
src/iss/arch/riscv_hart_msu_vp.h
Normal file
1422
src/iss/arch/riscv_hart_msu_vp.h
Normal file
File diff suppressed because it is too large
Load Diff
1425
src/iss/arch/riscv_hart_mu_p.h
Normal file
1425
src/iss/arch/riscv_hart_mu_p.h
Normal file
File diff suppressed because it is too large
Load Diff
69
src/iss/arch/tgc_c.cpp
Normal file
69
src/iss/arch/tgc_c.cpp
Normal file
@ -0,0 +1,69 @@
|
||||
/*******************************************************************************
|
||||
* Copyright (C) 2017 - 2020 MINRES Technologies GmbH
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of the copyright holder nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*******************************************************************************/
|
||||
|
||||
#include "util/ities.h"
|
||||
#include <util/logging.h>
|
||||
#include "tgc_c.h"
|
||||
#include <cstdio>
|
||||
#include <cstring>
|
||||
#include <fstream>
|
||||
|
||||
using namespace iss::arch;
|
||||
|
||||
constexpr std::array<const char*, 36> iss::arch::traits<iss::arch::tgc_c>::reg_names;
|
||||
constexpr std::array<const char*, 36> iss::arch::traits<iss::arch::tgc_c>::reg_aliases;
|
||||
constexpr std::array<const uint32_t, 36> iss::arch::traits<iss::arch::tgc_c>::reg_bit_widths;
|
||||
constexpr std::array<const uint32_t, 36> iss::arch::traits<iss::arch::tgc_c>::reg_byte_offsets;
|
||||
|
||||
tgc_c::tgc_c() = default;
|
||||
|
||||
tgc_c::~tgc_c() = default;
|
||||
|
||||
void tgc_c::reset(uint64_t address) {
|
||||
auto base_ptr = reinterpret_cast<traits<tgc_c>::reg_t*>(get_regs_base_ptr());
|
||||
for(size_t i=0; i<traits<tgc_c>::NUM_REGS; ++i)
|
||||
*(base_ptr+i)=0;
|
||||
reg.PC=address;
|
||||
reg.NEXT_PC=reg.PC;
|
||||
reg.PRIV=0x3;
|
||||
trap_state=0;
|
||||
icount=0;
|
||||
}
|
||||
|
||||
uint8_t *tgc_c::get_regs_base_ptr() {
|
||||
return reinterpret_cast<uint8_t*>(®);
|
||||
}
|
||||
|
||||
tgc_c::phys_addr_t tgc_c::virt2phys(const iss::addr_t &pc) {
|
||||
return phys_addr_t(pc); // change logical address to physical address
|
||||
}
|
||||
|
273
src/iss/arch/tgc_c.h
Normal file
273
src/iss/arch/tgc_c.h
Normal file
@ -0,0 +1,273 @@
|
||||
/*******************************************************************************
|
||||
* Copyright (C) 2017 - 2021 MINRES Technologies GmbH
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of the copyright holder nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef _TGC_C_H_
|
||||
#define _TGC_C_H_
|
||||
|
||||
#include <array>
|
||||
#include <iss/arch/traits.h>
|
||||
#include <iss/arch_if.h>
|
||||
#include <iss/vm_if.h>
|
||||
|
||||
namespace iss {
|
||||
namespace arch {
|
||||
|
||||
struct tgc_c;
|
||||
|
||||
template <> struct traits<tgc_c> {
|
||||
|
||||
constexpr static char const* const core_type = "TGC_C";
|
||||
|
||||
static constexpr std::array<const char*, 36> reg_names{
|
||||
{"X0", "X1", "X2", "X3", "X4", "X5", "X6", "X7", "X8", "X9", "X10", "X11", "X12", "X13", "X14", "X15", "X16", "X17", "X18", "X19", "X20", "X21", "X22", "X23", "X24", "X25", "X26", "X27", "X28", "X29", "X30", "X31", "PC", "NEXT_PC", "PRIV", "DPC"}};
|
||||
|
||||
static constexpr std::array<const char*, 36> reg_aliases{
|
||||
{"ZERO", "RA", "SP", "GP", "TP", "T0", "T1", "T2", "S0", "S1", "A0", "A1", "A2", "A3", "A4", "A5", "A6", "A7", "S2", "S3", "S4", "S5", "S6", "S7", "S8", "S9", "S10", "S11", "T3", "T4", "T5", "T6", "PC", "NEXT_PC", "PRIV", "DPC"}};
|
||||
|
||||
enum constants {MISA_VAL=0b01000000000000000001000100000100, MARCHID_VAL=0x80000003, RFS=32, INSTR_ALIGNMENT=2, XLEN=32, CSR_SIZE=4096, fence=0, fencei=1, fencevmal=2, fencevmau=3, MUL_LEN=64};
|
||||
|
||||
constexpr static unsigned FP_REGS_SIZE = 0;
|
||||
|
||||
enum reg_e {
|
||||
X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X12, X13, X14, X15, X16, X17, X18, X19, X20, X21, X22, X23, X24, X25, X26, X27, X28, X29, X30, X31, PC, NEXT_PC, PRIV, DPC, NUM_REGS
|
||||
};
|
||||
|
||||
using reg_t = uint32_t;
|
||||
|
||||
using addr_t = uint32_t;
|
||||
|
||||
using code_word_t = uint32_t; //TODO: check removal
|
||||
|
||||
using virt_addr_t = iss::typed_addr_t<iss::address_type::VIRTUAL>;
|
||||
|
||||
using phys_addr_t = iss::typed_addr_t<iss::address_type::PHYSICAL>;
|
||||
|
||||
static constexpr std::array<const uint32_t, 36> reg_bit_widths{
|
||||
{32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,8,32}};
|
||||
|
||||
static constexpr std::array<const uint32_t, 36> reg_byte_offsets{
|
||||
{0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,137}};
|
||||
|
||||
static const uint64_t addr_mask = (reg_t(1) << (XLEN - 1)) | ((reg_t(1) << (XLEN - 1)) - 1);
|
||||
|
||||
enum sreg_flag_e { FLAGS };
|
||||
|
||||
enum mem_type_e { MEM, CSR, FENCE, RES };
|
||||
|
||||
enum class opcode_e : unsigned short {
|
||||
LUI = 0,
|
||||
AUIPC = 1,
|
||||
JAL = 2,
|
||||
JALR = 3,
|
||||
BEQ = 4,
|
||||
BNE = 5,
|
||||
BLT = 6,
|
||||
BGE = 7,
|
||||
BLTU = 8,
|
||||
BGEU = 9,
|
||||
LB = 10,
|
||||
LH = 11,
|
||||
LW = 12,
|
||||
LBU = 13,
|
||||
LHU = 14,
|
||||
SB = 15,
|
||||
SH = 16,
|
||||
SW = 17,
|
||||
ADDI = 18,
|
||||
SLTI = 19,
|
||||
SLTIU = 20,
|
||||
XORI = 21,
|
||||
ORI = 22,
|
||||
ANDI = 23,
|
||||
SLLI = 24,
|
||||
SRLI = 25,
|
||||
SRAI = 26,
|
||||
ADD = 27,
|
||||
SUB = 28,
|
||||
SLL = 29,
|
||||
SLT = 30,
|
||||
SLTU = 31,
|
||||
XOR = 32,
|
||||
SRL = 33,
|
||||
SRA = 34,
|
||||
OR = 35,
|
||||
AND = 36,
|
||||
FENCE = 37,
|
||||
ECALL = 38,
|
||||
EBREAK = 39,
|
||||
URET = 40,
|
||||
SRET = 41,
|
||||
MRET = 42,
|
||||
WFI = 43,
|
||||
DRET = 44,
|
||||
CSRRW = 45,
|
||||
CSRRS = 46,
|
||||
CSRRC = 47,
|
||||
CSRRWI = 48,
|
||||
CSRRSI = 49,
|
||||
CSRRCI = 50,
|
||||
FENCE_I = 51,
|
||||
MUL = 52,
|
||||
MULH = 53,
|
||||
MULHSU = 54,
|
||||
MULHU = 55,
|
||||
DIV = 56,
|
||||
DIVU = 57,
|
||||
REM = 58,
|
||||
REMU = 59,
|
||||
CADDI4SPN = 60,
|
||||
CLW = 61,
|
||||
CSW = 62,
|
||||
CADDI = 63,
|
||||
CNOP = 64,
|
||||
CJAL = 65,
|
||||
CLI = 66,
|
||||
CLUI = 67,
|
||||
CADDI16SP = 68,
|
||||
__reserved_clui = 69,
|
||||
CSRLI = 70,
|
||||
CSRAI = 71,
|
||||
CANDI = 72,
|
||||
CSUB = 73,
|
||||
CXOR = 74,
|
||||
COR = 75,
|
||||
CAND = 76,
|
||||
CJ = 77,
|
||||
CBEQZ = 78,
|
||||
CBNEZ = 79,
|
||||
CSLLI = 80,
|
||||
CLWSP = 81,
|
||||
CMV = 82,
|
||||
CJR = 83,
|
||||
__reserved_cmv = 84,
|
||||
CADD = 85,
|
||||
CJALR = 86,
|
||||
CEBREAK = 87,
|
||||
CSWSP = 88,
|
||||
DII = 89,
|
||||
MAX_OPCODE
|
||||
};
|
||||
};
|
||||
|
||||
struct tgc_c: public arch_if {
|
||||
|
||||
using virt_addr_t = typename traits<tgc_c>::virt_addr_t;
|
||||
using phys_addr_t = typename traits<tgc_c>::phys_addr_t;
|
||||
using reg_t = typename traits<tgc_c>::reg_t;
|
||||
using addr_t = typename traits<tgc_c>::addr_t;
|
||||
|
||||
tgc_c();
|
||||
~tgc_c();
|
||||
|
||||
void reset(uint64_t address=0) override;
|
||||
|
||||
uint8_t* get_regs_base_ptr() override;
|
||||
|
||||
inline uint64_t get_icount() { return icount; }
|
||||
|
||||
inline bool should_stop() { return interrupt_sim; }
|
||||
|
||||
inline uint64_t stop_code() { return interrupt_sim; }
|
||||
|
||||
inline phys_addr_t v2p(const iss::addr_t& addr){
|
||||
if (addr.space != traits<tgc_c>::MEM || addr.type == iss::address_type::PHYSICAL ||
|
||||
addr_mode[static_cast<uint16_t>(addr.access)&0x3]==address_type::PHYSICAL) {
|
||||
return phys_addr_t(addr.access, addr.space, addr.val&traits<tgc_c>::addr_mask);
|
||||
} else
|
||||
return virt2phys(addr);
|
||||
}
|
||||
|
||||
virtual phys_addr_t virt2phys(const iss::addr_t& addr);
|
||||
|
||||
virtual iss::sync_type needed_sync() const { return iss::NO_SYNC; }
|
||||
|
||||
inline uint32_t get_last_branch() { return last_branch; }
|
||||
|
||||
|
||||
#pragma pack(push, 1)
|
||||
struct TGC_C_regs {
|
||||
uint32_t X0 = 0;
|
||||
uint32_t X1 = 0;
|
||||
uint32_t X2 = 0;
|
||||
uint32_t X3 = 0;
|
||||
uint32_t X4 = 0;
|
||||
uint32_t X5 = 0;
|
||||
uint32_t X6 = 0;
|
||||
uint32_t X7 = 0;
|
||||
uint32_t X8 = 0;
|
||||
uint32_t X9 = 0;
|
||||
uint32_t X10 = 0;
|
||||
uint32_t X11 = 0;
|
||||
uint32_t X12 = 0;
|
||||
uint32_t X13 = 0;
|
||||
uint32_t X14 = 0;
|
||||
uint32_t X15 = 0;
|
||||
uint32_t X16 = 0;
|
||||
uint32_t X17 = 0;
|
||||
uint32_t X18 = 0;
|
||||
uint32_t X19 = 0;
|
||||
uint32_t X20 = 0;
|
||||
uint32_t X21 = 0;
|
||||
uint32_t X22 = 0;
|
||||
uint32_t X23 = 0;
|
||||
uint32_t X24 = 0;
|
||||
uint32_t X25 = 0;
|
||||
uint32_t X26 = 0;
|
||||
uint32_t X27 = 0;
|
||||
uint32_t X28 = 0;
|
||||
uint32_t X29 = 0;
|
||||
uint32_t X30 = 0;
|
||||
uint32_t X31 = 0;
|
||||
uint32_t PC = 0;
|
||||
uint32_t NEXT_PC = 0;
|
||||
uint8_t PRIV = 0;
|
||||
uint32_t DPC = 0;
|
||||
} reg;
|
||||
#pragma pack(pop)
|
||||
uint32_t trap_state = 0, pending_trap = 0;
|
||||
uint64_t icount = 0;
|
||||
uint64_t cycle = 0;
|
||||
uint64_t instret = 0;
|
||||
uint32_t instruction = 0;
|
||||
uint32_t last_branch = 0;
|
||||
std::array<address_type, 4> addr_mode;
|
||||
|
||||
uint64_t interrupt_sim=0;
|
||||
|
||||
uint32_t get_fcsr(){return 0;}
|
||||
void set_fcsr(uint32_t val){}
|
||||
|
||||
};
|
||||
|
||||
}
|
||||
}
|
||||
#endif /* _TGC_C_H_ */
|
43
src/iss/arch/tgc_mapper.h
Normal file
43
src/iss/arch/tgc_mapper.h
Normal file
@ -0,0 +1,43 @@
|
||||
#ifndef _ISS_ARCH_TGC_MAPPER_H
|
||||
#define _ISS_ARCH_TGC_MAPPER_H
|
||||
|
||||
#include "riscv_hart_m_p.h"
|
||||
#include "tgc_c.h"
|
||||
using tgc_c_plat_type = iss::arch::riscv_hart_m_p<iss::arch::tgc_c>;
|
||||
#ifdef CORE_TGC_B
|
||||
#include "riscv_hart_m_p.h"
|
||||
#include "tgc_b.h"
|
||||
using tgc_b_plat_type = iss::arch::riscv_hart_m_p<iss::arch::tgc_b>;
|
||||
#endif
|
||||
#ifdef CORE_TGC_C_XRB_NN
|
||||
#include "riscv_hart_m_p.h"
|
||||
#include "tgc_c_xrb_nn.h"
|
||||
using tgc_c_xrb_nn_plat_type = iss::arch::riscv_hart_m_p<iss::arch::tgc_c_xrb_nn>;
|
||||
#endif
|
||||
#ifdef CORE_TGC_D
|
||||
#include "riscv_hart_mu_p.h"
|
||||
#include "tgc_d.h"
|
||||
using tgc_d_plat_type = iss::arch::riscv_hart_mu_p<iss::arch::tgc_d, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_CLIC | iss::arch::FEAT_EXT_N)>;
|
||||
#endif
|
||||
#ifdef CORE_TGC_D_XRB_MAC
|
||||
#include "riscv_hart_mu_p.h"
|
||||
#include "tgc_d_xrb_mac.h"
|
||||
using tgc_d_xrb_mac_plat_type = iss::arch::riscv_hart_mu_p<iss::arch::tgc_d_xrb_mac, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_CLIC | iss::arch::FEAT_EXT_N)>;
|
||||
#endif
|
||||
#ifdef CORE_TGC_D_XRB_NN
|
||||
#include "riscv_hart_mu_p.h"
|
||||
#include "tgc_d_xrb_nn.h"
|
||||
using tgc_d_xrb_nn_plat_type = iss::arch::riscv_hart_mu_p<iss::arch::tgc_d_xrb_nn, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_CLIC | iss::arch::FEAT_EXT_N)>;
|
||||
#endif
|
||||
#ifdef CORE_TGC_E
|
||||
#include "riscv_hart_mu_p.h"
|
||||
#include "tgc_e.h"
|
||||
using tgc_e_plat_type = iss::arch::riscv_hart_mu_p<iss::arch::tgc_e, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_CLIC | iss::arch::FEAT_EXT_N)>;
|
||||
#endif
|
||||
#ifdef CORE_TGC_X
|
||||
#include "riscv_hart_mu_p.h"
|
||||
#include "tgc_x.h"
|
||||
using tgc_x_plat_type = iss::arch::riscv_hart_mu_p<iss::arch::tgc_x, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_CLIC | iss::arch::FEAT_EXT_N | iss::arch::FEAT_TCM)>;
|
||||
#endif
|
||||
|
||||
#endif
|
Reference in New Issue
Block a user