does some cleanup of the directory structure
This commit is contained in:
3
contrib/pa/.gitignore
vendored
Normal file
3
contrib/pa/.gitignore
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@ -0,0 +1,3 @@
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/results
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/cwr
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/*.xml
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43
contrib/pa/README.md
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43
contrib/pa/README.md
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# Notes
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* requires conan version 1.59
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* requires decent cmake version 3.23
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Setup for tcsh:
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```
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git clone --recursive -b develop https://git.minres.com/TGFS/TGC-ISS.git
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cd TGC-ISS/
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setenv TGFS_INSTALL_ROOT `pwd`/install
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setenv COWAREHOME <your SNPS PA installation>
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setenv SNPSLMD_LICENSE_FILE <your SNPS PA license file>
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source $COWAREHOME/SLS/linux/setup.csh pae
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setenv SNPS_ENABLE_MEM_ON_DEMAND_IN_GENERIC_MEM 1
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setenv PATH $COWAREHOME/common/bin/:${PATH}
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setenv CC $COWAREHOME/SLS/linux/common/bin/gcc
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setenv CXX $COWAREHOME/SLS/linux/common/bin/g++
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cmake -S . -B build/PA -DCMAKE_BUILD_TYPE=Debug -DUSE_CWR_SYSTEMC=ON -DBUILD_SHARED_LIBS=ON \
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-DCODEGEN=OFF -DCMAKE_INSTALL_PREFIX=${TGFS_INSTALL_ROOT}
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cmake --build build/PA --target install -j16
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cd dbt-rise-tgc/contrib/pa
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# import the TGC core itself
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pct tgc_import_tb.tcl
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```
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Setup for bash:
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```
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git clone --recursive -b develop https://git.minres.com/TGFS/TGC-ISS.git
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cd TGC-ISS/
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export TGFS_INSTALL_ROOT `pwd`/install
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module load tools/pa/T-2022.06
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export SNPS_ENABLE_MEM_ON_DEMAND_IN_GENERIC_MEM=1
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export CC=$COWAREHOME/SLS/linux/common/bin/gcc
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export CXX=$COWAREHOME/SLS/linux/common/bin/g++
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cmake -S . -B build/PA -DCMAKE_BUILD_TYPE=Debug -DUSE_CWR_SYSTEMC=ON -DBUILD_SHARED_LIBS=ON \
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-DCODEGEN=OFF -DCMAKE_INSTALL_PREFIX=${TGFS_INSTALL_ROOT}
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cmake --build build/PA --target install -j16
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cd dbt-rise-tgc/contrib/pa
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# import the TGC core itself
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pct tgc_import_tb.tcl
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```
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30
contrib/pa/build.tcl
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30
contrib/pa/build.tcl
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namespace eval Specification {
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proc buildproc { args } {
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global env
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variable installDir
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variable compiler
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variable compiler [::scsh::get_backend_compiler]
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# set target $machine
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set target [::scsh::machine]
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set linkerOptions ""
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set preprocessorOptions ""
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set libversion $compiler
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switch -exact -- $target {
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"linux" {
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set install_dir $::env(TGFS_INSTALL_ROOT)
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set incldir "${install_dir}/include"
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set libdir "${install_dir}/lib64"
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set preprocessorOptions [concat $preprocessorOptions "-I${incldir}"]
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# Set the Linker paths.
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set linkerOptions [concat $linkerOptions "-Wl,-rpath,${libdir} -L${libdir} -ldbt-rise-tgc_sc -lscc-sysc"]
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}
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default {
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puts stderr "ERROR: \"$target\" is not supported, [::scsh::version]"
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return
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}
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}
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::scsh::cwr_append_ipsimbld_opts preprocessor "$preprocessorOptions"
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::scsh::cwr_append_ipsimbld_opts linker "$linkerOptions"
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}
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::scsh::add_build_callback [namespace current]::buildproc
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}
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2092
contrib/pa/hello.dis
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2092
contrib/pa/hello.dis
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File diff suppressed because it is too large
Load Diff
BIN
contrib/pa/hello.elf
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BIN
contrib/pa/hello.elf
Executable file
Binary file not shown.
BIN
contrib/pa/minres.png
Executable file
BIN
contrib/pa/minres.png
Executable file
Binary file not shown.
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After Width: | Height: | Size: 25 KiB |
4
contrib/pa/tgc_import.cc
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contrib/pa/tgc_import.cc
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#include "sysc/core_complex.h"
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void modules() { sysc::tgfs::core_complex i_core_complex("core_complex"); }
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50
contrib/pa/tgc_import.tcl
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contrib/pa/tgc_import.tcl
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#############################################################################
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#
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#############################################################################
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proc getScriptDirectory {} {
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set dispScriptFile [file normalize [info script]]
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set scriptFolder [file dirname $dispScriptFile]
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return $scriptFolder
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}
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set hardware /HARDWARE/HW/HW
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set scriptDir [getScriptDirectory]
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set top_design_name core_complex
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set encap_name sysc::tgfs::${top_design_name}
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set clocks clk_i
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set resets rst_i
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set model_prefix "i_"
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set model_postfix ""
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::pct::new_project
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::pct::open_library TLM2_PL
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::pct::clear_systemc_defines
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::pct::clear_systemc_include_path
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::pct::add_to_systemc_include_path $::env(TGFS_INSTALL_ROOT)/include
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::pct::set_import_protocol_generation_flag false
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::pct::set_update_existing_encaps_flag true
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::pct::set_dynamic_port_arrays_flag true
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::pct::set_import_scml_properties_flag true
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::pct::set_import_encap_prop_as_extra_prop_flag true
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::pct::load_modules --set-category modules ${scriptDir}/tgc_import.cc
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# Set Port Protocols correctly
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set block ${top_design_name}
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foreach clock ${clocks} {
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::pct::set_block_port_protocol --set-category SYSTEM_LIBRARY:$block/${clock} SYSTEM_LIBRARY:CLOCK
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}
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foreach reset ${resets} {
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::pct::set_block_port_protocol --set-category SYSTEM_LIBRARY:$block/${reset} SYSTEM_LIBRARY:RESET
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}
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#::pct::set_encap_port_array_size SYSTEM_LIBRARY:$block/local_irq_i 16
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# Set compile settings and look
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set block SYSTEM_LIBRARY:${top_design_name}
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::pct::set_encap_build_script $block/${encap_name} $scriptDir/build.tcl
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::pct::set_background_color_rgb $block 255 255 255 255
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::pct::create_instance SYSTEM_LIBRARY:${top_design_name} ${hardware} ${model_prefix}${top_design_name}${model_postfix} ${encap_name} ${encap_name}()
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::pct::set_bounds i_${top_design_name} 200 300 100 400
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::pct::set_image i_${top_design_name} "$scriptDir/minres.png" center center false true
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# export the result as component
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::pct::export_system_library ${top_design_name} ${top_design_name}.xml
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71
contrib/pa/tgc_import_tb.tcl
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71
contrib/pa/tgc_import_tb.tcl
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@ -0,0 +1,71 @@
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source tgc_import.tcl
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set hardware /HARDWARE/HW/HW
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set FW_name ${scriptDir}/hello.elf
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puts "instantiate testbench elements"
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::paultra::add_hw_instance GenericIPlib:Memory_Generic -inst_name i_Memory_Generic
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::pct::set_param_value i_Memory_Generic/MEM:protocol {Protocol Common Parameters} address_width 30
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::pct::set_param_value i_Memory_Generic {Scml Properties} /timing/LT/clock_period_in_ns 1
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::pct::set_param_value i_Memory_Generic {Scml Properties} /timing/read/cmd_accept_cycles 1
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::pct::set_param_value i_Memory_Generic {Scml Properties} /timing/write/cmd_accept_cycles 1
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::pct::set_bounds i_Memory_Generic 1000 300 100 100
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::paultra::add_hw_instance Bus:Bus -inst_name i_Bus
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::BLWizard::generateFramework i_Bus SBLTLM2FT * {} \
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{ common_configuration:BackBone:/advanced/num_resources_per_target:1 }
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::pct::set_bounds i_Bus 700 300 100 400
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::pct::create_connection C_ibus i_core_complex/ibus i_Bus/i_core_complex_ibus
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::pct::set_location_on_owner i_Bus/i_core_complex_ibus 10
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::pct::create_connection C_dbus i_core_complex/dbus i_Bus/i_core_complex_dbus
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::pct::set_location_on_owner i_Bus/i_core_complex_dbus 10
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::pct::create_connection C_mem i_Bus/i_Memory_Generic_MEM i_Memory_Generic/MEM
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puts "instantiating clock manager"
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set clock "Clk"
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::hw::create_hw_instance "" GenericIPlib:ClockGenerator ${clock}_clock
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::pct::set_bounds ${clock}_clock 100 100 100 100
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::pct::set_param_value $hardware/${clock}_clock {Constructor Arguments} period 1000
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::pct::set_param_value $hardware/${clock}_clock {Constructor Arguments} period_unit sc_core::SC_PS
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puts "instantiating reset manager"
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set reset "Rst"
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::hw::create_hw_instance "" GenericIPlib:ResetGenerator ${reset}_reset
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::pct::set_param_value $hardware/${reset}_reset {Constructor Arguments} start_time 0
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::pct::set_param_value $hardware/${reset}_reset {Constructor Arguments} start_time_unit sc_core::SC_PS
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::pct::set_param_value $hardware/${reset}_reset {Constructor Arguments} duration 10000
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::pct::set_param_value $hardware/${reset}_reset {Constructor Arguments} duration_unit sc_core::SC_PS
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::pct::set_param_value $hardware/${reset}_reset {Constructor Arguments} active_level true
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::pct::set_bounds ${reset}_reset 300 100 100 100
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puts "connecting reset/clock"
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::pct::create_connection C_clk . Clk_clock/CLK i_core_complex/clk_i
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::pct::add_ports_to_connection C_clk i_Bus/Clk
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::pct::add_ports_to_connection C_clk i_Memory_Generic/CLK
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::pct::create_connection C_rst . Rst_reset/RST i_core_complex/rst_i
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::pct::add_ports_to_connection C_rst i_Bus/Rst
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puts "setting parameters for DBT-RISE-TGC/Bus and memory components"
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::pct::set_param_value $hardware/i_${top_design_name} {Extra properties} elf_file ${FW_name}
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::pct::set_address $hardware/i_${top_design_name}/ibus:i_Memory_Generic/MEM 0x0
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::pct::set_address $hardware/i_${top_design_name}/dbus:i_Memory_Generic/MEM 0x0
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::BLWizard::updateFramework i_Bus {} { common_configuration:BackBone:/advanced/num_resources_per_target:1 }
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::pct::set_main_configuration Default {{#include <scc/report.h>} {::scc::init_logging(::scc::LogConfig().logLevel(::scc::log::INFO).coloredOutput(false).logAsync(false));} {} {} {}}
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::pct::set_main_configuration Debug {{#include <scc/report.h>} {::scc::init_logging(::scc::LogConfig().logLevel(::scc::log::DEBUG).coloredOutput(false).logAsync(false));} {} {} {}}
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::pct::create_simulation_build_config Debug
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::pct::set_simulation_build_project_setting Debug "Main Configuration" Default
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# add build settings and save design for next steps
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#::pct::set_simulation_build_project_setting "Debug" "Linker Flags" "-Wl,-z,muldefs $::env(VERILATOR_ROOT)/include/verilated.cpp $::env(VERILATOR_ROOT)/include/verilated_vcd_sc.cpp $::env(VERILATOR_ROOT)/include/verilated_vcd_c.cpp"
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#::pct::set_simulation_build_project_setting "Debug" "Include Paths" $::env(VERILATOR_ROOT)/include/
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#::simulation::set_simulation_property Simulation [list run_for_duration:200ns results_dir:results/test_0 "TLM Port Trace:true"]
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#::simulation::run_simulation Simulation
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#::pct::set_simulation_build_project_setting Debug {Export Type} {STATIC NETLIST}
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#::pct::set_simulation_build_project_setting Debug {Encapsulated Netlist} false
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#::pct::export_system "export"
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#::cd "export"
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#::scsh::open-project
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#::scsh::build
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#::scsh::elab sim
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::pct::save_system testbench.xml
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