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update RISC-V descriptions

This commit is contained in:
Eyck Jentzsch 2021-02-15 18:01:33 +00:00
parent 3261055871
commit 72b09472d5
3 changed files with 24 additions and 13 deletions
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2
gen_input/CoreDSL-Instruction-Set-Description

@ -1 +1 @@
Subproject commit 919a3c861112aa1205950d9f03055adfc801f741 Subproject commit 67dbc5535d3977d6145a2a85fc53c0e6cbc5d636

20
incl/iss/arch/tgf_c.h
View File

@ -47,11 +47,11 @@ template <> struct traits<tgf_c> {
constexpr static char const* const core_type = "TGF_C"; constexpr static char const* const core_type = "TGF_C";
static constexpr std::array<const char*, 34> reg_names{ static constexpr std::array<const char*, 35> reg_names{
{"X0", "X1", "X2", "X3", "X4", "X5", "X6", "X7", "X8", "X9", "X10", "X11", "X12", "X13", "X14", "X15", "X16", "X17", "X18", "X19", "X20", "X21", "X22", "X23", "X24", "X25", "X26", "X27", "X28", "X29", "X30", "X31", "PC", "NUM_REGS"}}; {"X0", "X1", "X2", "X3", "X4", "X5", "X6", "X7", "X8", "X9", "X10", "X11", "X12", "X13", "X14", "X15", "X16", "X17", "X18", "X19", "X20", "X21", "X22", "X23", "X24", "X25", "X26", "X27", "X28", "X29", "X30", "X31", "PC", "PRIV", "NUM_REGS"}};
static constexpr std::array<const char*, 34> reg_aliases{ static constexpr std::array<const char*, 35> reg_aliases{
{"X0", "X1", "X2", "X3", "X4", "X5", "X6", "X7", "X8", "X9", "X10", "X11", "X12", "X13", "X14", "X15", "X16", "X17", "X18", "X19", "X20", "X21", "X22", "X23", "X24", "X25", "X26", "X27", "X28", "X29", "X30", "X31", "PC", "NUM_REGS"}}; {"X0", "X1", "X2", "X3", "X4", "X5", "X6", "X7", "X8", "X9", "X10", "X11", "X12", "X13", "X14", "X15", "X16", "X17", "X18", "X19", "X20", "X21", "X22", "X23", "X24", "X25", "X26", "X27", "X28", "X29", "X30", "X31", "PC", "PRIV", "NUM_REGS"}};
enum constants {XLEN=32, PCLEN=32, MISA_VAL=0b1000000000000000001000100000100, PGSIZE=0x1000, PGMASK=0xfff, CSR_SIZE=4096, fence=0, fencei=1, fencevmal=2, fencevmau=3, MUL_LEN=64}; enum constants {XLEN=32, PCLEN=32, MISA_VAL=0b1000000000000000001000100000100, PGSIZE=0x1000, PGMASK=0xfff, CSR_SIZE=4096, fence=0, fencei=1, fencevmal=2, fencevmau=3, MUL_LEN=64};
@ -91,6 +91,7 @@ template <> struct traits<tgf_c> {
X30, X30,
X31, X31,
PC, PC,
PRIV,
NUM_REGS, NUM_REGS,
NEXT_PC=NUM_REGS, NEXT_PC=NUM_REGS,
TRAP_STATE, TRAP_STATE,
@ -110,11 +111,11 @@ template <> struct traits<tgf_c> {
using phys_addr_t = iss::typed_addr_t<iss::address_type::PHYSICAL>; using phys_addr_t = iss::typed_addr_t<iss::address_type::PHYSICAL>;
static constexpr std::array<const uint32_t, 39> reg_bit_widths{ static constexpr std::array<const uint32_t, 40> reg_bit_widths{
{32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,64}}; {32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,2,32,32,32,32,32,64}};
static constexpr std::array<const uint32_t, 39> reg_byte_offsets{ static constexpr std::array<const uint32_t, 40> reg_byte_offsets{
{0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148,152}}; {0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,133,137,141,145,149,153}};
static const uint64_t addr_mask = (reg_t(1) << (XLEN - 1)) | ((reg_t(1) << (XLEN - 1)) - 1); static const uint64_t addr_mask = (reg_t(1) << (XLEN - 1)) | ((reg_t(1) << (XLEN - 1)) - 1);
@ -199,7 +200,8 @@ protected:
uint32_t X29 = 0; uint32_t X29 = 0;
uint32_t X30 = 0; uint32_t X30 = 0;
uint32_t X31 = 0; uint32_t X31 = 0;
uint32_t PC = 0; uint32_t PC = 0;
uint2_t PRIV = 0;
uint32_t NEXT_PC = 0; uint32_t NEXT_PC = 0;
uint32_t trap_state = 0, pending_trap = 0, machine_state = 0, last_branch = 0; uint32_t trap_state = 0, pending_trap = 0, machine_state = 0, last_branch = 0;
uint64_t icount = 0; uint64_t icount = 0;

15
src/vm/interp/vm_tgf_c.cpp
View File

@ -1644,7 +1644,10 @@ private:
uint8_t pred = ((bit_sub<24,4>(instr))); uint8_t pred = ((bit_sub<24,4>(instr)));
if(this->disass_enabled){ if(this->disass_enabled){
/* generate console output when executing the command */ /* generate console output when executing the command */
this->core.disass_output(pc.val, "fence"); auto mnemonic = fmt::format(
"{mnemonic:10} {pred}, {succ}, {rs1}, {rd}", fmt::arg("mnemonic", "fence"),
fmt::arg("pred", name(pred)), fmt::arg("succ", name(succ)), fmt::arg("rs1", name(rs1)), fmt::arg("rd", name(rd)));
this->core.disass_output(pc.val, mnemonic);
} }
// prepare execution // prepare execution
@ -1675,7 +1678,10 @@ private:
uint16_t imm = ((bit_sub<20,12>(instr))); uint16_t imm = ((bit_sub<20,12>(instr)));
if(this->disass_enabled){ if(this->disass_enabled){
/* generate console output when executing the command */ /* generate console output when executing the command */
this->core.disass_output(pc.val, "fence_i"); auto mnemonic = fmt::format(
"{mnemonic:10} {rs1}, {rd}, {imm}", fmt::arg("mnemonic", "fence_i"),
fmt::arg("rs1", name(rs1)), fmt::arg("rd", name(rd)), fmt::arg("imm", name(imm)));
this->core.disass_output(pc.val, mnemonic);
} }
// prepare execution // prepare execution
@ -1873,7 +1879,10 @@ private:
uint8_t rs2 = ((bit_sub<20,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr)));
if(this->disass_enabled){ if(this->disass_enabled){
/* generate console output when executing the command */ /* generate console output when executing the command */
this->core.disass_output(pc.val, "sfence_vma"); auto mnemonic = fmt::format(
"{mnemonic:10} {rs2}, {rs1}", fmt::arg("mnemonic", "sfence_vma"),
fmt::arg("rs2", name(rs2)), fmt::arg("rs1", rs1));
this->core.disass_output(pc.val, mnemonic);
} }
// prepare execution // prepare execution