reorganized layout to only contain risc-v stuff
This commit is contained in:
80
src/iss/rv32gc.cpp
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80
src/iss/rv32gc.cpp
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@@ -0,0 +1,80 @@
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/*******************************************************************************
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* Copyright (C) 2017, 2018 MINRES Technologies GmbH
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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*******************************************************************************/
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#include "util/ities.h"
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#include <util/logging.h>
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#include <elfio/elfio.hpp>
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#include <iss/arch/rv32gc.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <ihex.h>
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#ifdef __cplusplus
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}
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#endif
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#include <fstream>
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#include <cstdio>
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#include <cstring>
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using namespace iss::arch;
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constexpr std::array<const char*, 66> iss::arch::traits<iss::arch::rv32gc>::reg_names;
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constexpr std::array<const char*, 66> iss::arch::traits<iss::arch::rv32gc>::reg_aliases;
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constexpr std::array<const uint32_t, 72> iss::arch::traits<iss::arch::rv32gc>::reg_bit_widths;
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constexpr std::array<const uint32_t, 73> iss::arch::traits<iss::arch::rv32gc>::reg_byte_offsets;
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rv32gc::rv32gc() {
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reg.icount=0;
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}
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rv32gc::~rv32gc(){
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}
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void rv32gc::reset(uint64_t address) {
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for(size_t i=0; i<traits<rv32gc>::NUM_REGS; ++i) set_reg(i, std::vector<uint8_t>(sizeof(traits<rv32gc>::reg_t),0));
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reg.PC=address;
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reg.NEXT_PC=reg.PC;
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reg.trap_state=0;
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reg.machine_state=0x0;
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reg.icount=0;
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}
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uint8_t* rv32gc::get_regs_base_ptr(){
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return reinterpret_cast<uint8_t*>(®);
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}
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rv32gc::phys_addr_t rv32gc::virt2phys(const iss::addr_t &pc) {
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return phys_addr_t(pc); // change logical address to physical address
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}
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77
src/iss/rv32imac.cpp
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77
src/iss/rv32imac.cpp
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@@ -0,0 +1,77 @@
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/*******************************************************************************
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* Copyright (C) 2017, 2018 MINRES Technologies GmbH
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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*******************************************************************************/
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#include "util/ities.h"
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#include <util/logging.h>
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#include <elfio/elfio.hpp>
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#include <iss/arch/rv32imac.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <ihex.h>
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#ifdef __cplusplus
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}
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#endif
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#include <cstdio>
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#include <cstring>
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#include <fstream>
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using namespace iss::arch;
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constexpr std::array<const char*, 33> iss::arch::traits<iss::arch::rv32imac>::reg_names;
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constexpr std::array<const char*, 33> iss::arch::traits<iss::arch::rv32imac>::reg_aliases;
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constexpr std::array<const uint32_t, 39> iss::arch::traits<iss::arch::rv32imac>::reg_bit_widths;
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constexpr std::array<const uint32_t, 40> iss::arch::traits<iss::arch::rv32imac>::reg_byte_offsets;
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rv32imac::rv32imac() {
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reg.icount = 0;
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reg.machine_state = 0x3;
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}
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rv32imac::~rv32imac() = default;
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void rv32imac::reset(uint64_t address) {
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for (size_t i = 0; i < traits<rv32imac>::NUM_REGS; ++i)
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set_reg(i, std::vector<uint8_t>(sizeof(traits<rv32imac>::reg_t), 0));
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reg.PC = address;
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reg.NEXT_PC = reg.PC;
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reg.trap_state = 0;
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reg.machine_state = 0x3;
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}
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uint8_t *rv32imac::get_regs_base_ptr() { return reinterpret_cast<uint8_t *>(®); }
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rv32imac::phys_addr_t rv32imac::virt2phys(const iss::addr_t &pc) {
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return phys_addr_t(pc); // change logical address to physical address
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}
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81
src/iss/rv64gc.cpp
Normal file
81
src/iss/rv64gc.cpp
Normal file
@@ -0,0 +1,81 @@
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/*******************************************************************************
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* Copyright (C) 2017, 2018 MINRES Technologies GmbH
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
|
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*
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* 1. Redistributions of source code must retain the above copyright notice,
|
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* this list of conditions and the following disclaimer.
|
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
|
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* this list of conditions and the following disclaimer in the documentation
|
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* and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its contributors
|
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* may be used to endorse or promote products derived from this software
|
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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*******************************************************************************/
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#include "util/ities.h"
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#include <util/logging.h>
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#include <elfio/elfio.hpp>
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#include <iss/arch/rv64gc.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <ihex.h>
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#ifdef __cplusplus
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}
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#endif
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#include <cstdio>
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#include <cstring>
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#include <fstream>
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using namespace iss::arch;
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constexpr std::array<const char*, 66> iss::arch::traits<iss::arch::rv64gc>::reg_names;
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constexpr std::array<const char*, 66> iss::arch::traits<iss::arch::rv64gc>::reg_aliases;
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constexpr std::array<const uint32_t, 72> iss::arch::traits<iss::arch::rv64gc>::reg_bit_widths;
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constexpr std::array<const uint32_t, 73> iss::arch::traits<iss::arch::rv64gc>::reg_byte_offsets;
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rv64gc::rv64gc() {
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reg.icount = 0;
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}
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rv64gc::~rv64gc() = default;
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void rv64gc::reset(uint64_t address) {
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for(size_t i=0; i<traits<rv64gc>::NUM_REGS; ++i) set_reg(i, std::vector<uint8_t>(sizeof(traits<rv64gc>::reg_t),0));
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reg.PC=address;
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reg.NEXT_PC=reg.PC;
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reg.trap_state=0;
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reg.machine_state=0x0;
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reg.icount=0;
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}
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uint8_t *rv64gc::get_regs_base_ptr() {
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return reinterpret_cast<uint8_t*>(®);
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}
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rv64gc::phys_addr_t rv64gc::virt2phys(const iss::addr_t &pc) {
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return phys_addr_t(pc); // change logical address to physical address
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}
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79
src/iss/rv64i.cpp
Normal file
79
src/iss/rv64i.cpp
Normal file
@@ -0,0 +1,79 @@
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/*******************************************************************************
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* Copyright (C) 2017, 2018 MINRES Technologies GmbH
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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||||
* modification, are permitted provided that the following conditions are met:
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||||
*
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||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
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||||
*
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||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
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||||
*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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*******************************************************************************/
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#include "util/ities.h"
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#include <util/logging.h>
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#include <elfio/elfio.hpp>
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#include <iss/arch/rv64i.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <ihex.h>
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#ifdef __cplusplus
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}
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#endif
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#include <cstdio>
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#include <cstring>
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#include <fstream>
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using namespace iss::arch;
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constexpr std::array<const char*, 33> iss::arch::traits<iss::arch::rv64i>::reg_names;
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constexpr std::array<const char*, 33> iss::arch::traits<iss::arch::rv64i>::reg_aliases;
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constexpr std::array<const uint32_t, 39> iss::arch::traits<iss::arch::rv64i>::reg_bit_widths;
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constexpr std::array<const uint32_t, 40> iss::arch::traits<iss::arch::rv64i>::reg_byte_offsets;
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rv64i::rv64i() {
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reg.icount = 0;
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}
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rv64i::~rv64i() = default;
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void rv64i::reset(uint64_t address) {
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for(size_t i=0; i<traits<rv64i>::NUM_REGS; ++i) set_reg(i, std::vector<uint8_t>(sizeof(traits<rv64i>::reg_t),0));
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reg.PC=address;
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reg.NEXT_PC=reg.PC;
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reg.trap_state=0;
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reg.machine_state=0x0;
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reg.icount=0;
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}
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uint8_t *rv64i::get_regs_base_ptr() {
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return reinterpret_cast<uint8_t*>(®);
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}
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rv64i::phys_addr_t rv64i::virt2phys(const iss::addr_t &pc) {
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return phys_addr_t(pc); // change logical address to physical address
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}
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