reorganized layout to only contain risc-v stuff
This commit is contained in:
360
gen_input/RVD.core_desc
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360
gen_input/RVD.core_desc
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@ -0,0 +1,360 @@
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import "RISCVBase.core_desc"
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InsructionSet RV32D extends RISCVBase{
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constants {
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FLEN, FFLAG_MASK := 0x1f
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}
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registers {
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[31:0] F[FLEN], FCSR[32]
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}
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instructions{
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FLD {
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encoding: imm[11:0]s | rs1[4:0] | b011 | rd[4:0] | b0000111;
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args_disass:"f{rd}, {imm}({name(rs1)})";
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val offs[XLEN] <= X[rs1]'s + imm;
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val res[64] <= MEM[offs]{64};
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if(FLEN==64)
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F[rd] <= res;
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else { // NaN boxing
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val upper[FLEN] <= -1;
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F[rd] <= (upper<<64) | res;
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}
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}
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FSD {
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encoding: imm[11:5]s | rs2[4:0] | rs1[4:0] | b011 | imm[4:0]s | b0100111;
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args_disass:"f{rs2}, {imm}({name(rs1)})";
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val offs[XLEN] <= X[rs1]'s + imm;
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MEM[offs]{64}<=F[rs2]{64};
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}
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FMADD.D {
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encoding: rs3[4:0] | b01 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1000011;
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args_disass:"{name(rd)}, f{rs1}, f{rs2}, f{rs3}";
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//F[rd]f<= F[rs1]f * F[rs2]f + F[rs3]f;
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val res[64] <= fdispatch_fmadd_d(F[rs1]{64}, F[rs2]{64}, F[rs3]{64}, zext(0, 64), choose(rm<7, rm{8}, FCSR{8}));
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if(FLEN==64)
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F[rd] <= res;
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else { // NaN boxing
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val upper[FLEN] <= -1;
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F[rd] <= (upper<<64) | res;
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}
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val flags[32] <= fdispatch_fget_flags();
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FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
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}
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FMSUB.D {
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encoding: rs3[4:0] | b01 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1000111;
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args_disass:"{name(rd)}, f{rs1}, f{rs2}, f{rs3}";
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//F[rd]f<=F[rs1]f * F[rs2]f - F[rs3]f;
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val res[64] <= fdispatch_fmadd_d(F[rs1]{64}, F[rs2]{64}, F[rs3]{64}, zext(1, 32), choose(rm<7, rm{8}, FCSR{8}));
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if(FLEN==64)
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F[rd] <= res;
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else { // NaN boxing
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val upper[FLEN] <= -1;
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F[rd] <= (upper<<64) | res;
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}
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val flags[32] <= fdispatch_fget_flags();
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FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
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}
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FNMADD.D {
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encoding: rs3[4:0] | b01 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1001111;
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args_disass:"{name(rd)}, f{rs1}, f{rs2}, f{rs3}";
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//F[rd]f<=-F[rs1]f * F[rs2]f + F[rs3]f;
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val res[64] <= fdispatch_fmadd_d(F[rs1]{64}, F[rs2]{64}, F[rs3]{64}, zext(2, 32), choose(rm<7, rm{8}, FCSR{8}));
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if(FLEN==64)
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F[rd] <= res;
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else { // NaN boxing
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val upper[FLEN] <= -1;
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F[rd] <= (upper<<64) | res;
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}
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val flags[32] <= fdispatch_fget_flags();
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FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
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}
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FNMSUB.D {
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encoding: rs3[4:0] | b01 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1001011;
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args_disass:"{name(rd)}, f{rs1}, f{rs2}, f{rs3}";
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//F[rd]f<=-F[rs1]f * F[rs2]f - F[rs3]f;
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val res[64] <= fdispatch_fmadd_d(F[rs1]{64}, F[rs2]{64}, F[rs3]{64}, zext(3, 32), choose(rm<7, rm{8}, FCSR{8}));
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if(FLEN==64)
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F[rd] <= res;
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else { // NaN boxing
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val upper[FLEN] <= -1;
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F[rd] <= (upper<<64) | res;
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}
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val flags[32] <= fdispatch_fget_flags();
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FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
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}
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FADD.D {
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encoding: b0000001 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
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args_disass:"{name(rd)}, f{rs1}, f{rs2}";
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// F[rd]f <= F[rs1]f + F[rs2]f;
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val res[64] <= fdispatch_fadd_d(F[rs1]{64}, F[rs2]{64}, choose(rm<7, rm{8}, FCSR{8}));
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if(FLEN==64)
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F[rd] <= res;
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else { // NaN boxing
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val upper[FLEN] <= -1;
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F[rd] <= (upper<<64) | res;
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}
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val flags[32] <= fdispatch_fget_flags();
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FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
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}
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FSUB.D {
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encoding: b0000101 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
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args_disass:"{name(rd)}, f{rs1}, f{rs2}";
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// F[rd]f <= F[rs1]f - F[rs2]f;
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val res[64] <= fdispatch_fsub_d(F[rs1]{64}, F[rs2]{64}, choose(rm<7, rm{8}, FCSR{8}));
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if(FLEN==64)
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F[rd] <= res;
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else { // NaN boxing
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val upper[FLEN] <= -1;
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F[rd] <= (upper<<64) | res;
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}
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val flags[32] <= fdispatch_fget_flags();
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FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
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}
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FMUL.D {
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encoding: b0001001 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
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args_disass:"{name(rd)}, f{rs1}, f{rs2}";
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// F[rd]f <= F[rs1]f * F[rs2]f;
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val res[64] <= fdispatch_fmul_d(F[rs1]{64}, F[rs2]{64}, choose(rm<7, rm{8}, FCSR{8}));
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if(FLEN==64)
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F[rd] <= res;
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else { // NaN boxing
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val upper[FLEN] <= -1;
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F[rd] <= (upper<<64) | res;
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}
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val flags[32] <= fdispatch_fget_flags();
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FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
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}
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FDIV.D {
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encoding: b0001101 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
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args_disass:"{name(rd)}, f{rs1}, f{rs2}";
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// F[rd]f <= F[rs1]f / F[rs2]f;
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val res[64] <= fdispatch_fdiv_d(F[rs1]{64}, F[rs2]{64}, choose(rm<7, rm{8}, FCSR{8}));
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if(FLEN==64)
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F[rd] <= res;
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else { // NaN boxing
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val upper[FLEN] <= -1;
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F[rd] <= (upper<<64) | res;
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}
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val flags[32] <= fdispatch_fget_flags();
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FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
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}
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FSQRT.D {
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encoding: b0101101 | b00000 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
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args_disass:"{name(rd)}, f{rs1}";
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//F[rd]f<=sqrt(F[rs1]f);
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val res[64] <= fdispatch_fsqrt_d(F[rs1]{64}, choose(rm<7, rm{8}, FCSR{8}));
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if(FLEN==64)
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F[rd] <= res;
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else { // NaN boxing
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val upper[FLEN] <= -1;
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F[rd] <= (upper<<64) | res;
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}
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val flags[32] <= fdispatch_fget_flags();
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FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
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}
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FSGNJ.D {
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encoding: b0010001 | rs2[4:0] | rs1[4:0] | b000 | rd[4:0] | b1010011;
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args_disass:"f{rd}, f{rs1}, f{rs2}";
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val ONE[64] <= 1;
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val MSK1[64] <= ONE<<63;
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val MSK2[64] <= MSK1-1;
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val res[64] <= (F[rs1]{64} & MSK2) | (F[rs2]{64} & MSK1);
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if(FLEN==64)
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F[rd] <= res;
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else { // NaN boxing
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val upper[FLEN] <= -1;
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F[rd] <= (upper<<64) | res;
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}
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}
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FSGNJN.D {
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encoding: b0010001 | rs2[4:0] | rs1[4:0] | b001 | rd[4:0] | b1010011;
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args_disass:"f{rd}, f{rs1}, f{rs2}";
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val ONE[64] <= 1;
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val MSK1[64] <= ONE<<63;
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val MSK2[64] <= MSK1-1;
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val res[64] <= (F[rs1]{64} & MSK2) | (~F[rs2]{64} & MSK1);
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if(FLEN==64)
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F[rd] <= res;
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else { // NaN boxing
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val upper[FLEN] <= -1;
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F[rd] <= (upper<<64) | res;
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}
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}
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FSGNJX.D {
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encoding: b0010001 | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b1010011;
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args_disass:"f{rd}, f{rs1}, f{rs2}";
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val ONE[64] <= 1;
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val MSK1[64] <= ONE<<63;
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val res[64] <= F[rs1]{64} ^ (F[rs2]{64} & MSK1);
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if(FLEN==64)
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F[rd] <= res;
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else { // NaN boxing
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val upper[FLEN] <= -1;
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F[rd] <= (upper<<64) | res;
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}
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}
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FMIN.D {
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encoding: b0010101 | rs2[4:0] | rs1[4:0] | b000 | rd[4:0] | b1010011;
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args_disass:"f{rd}, f{rs1}, f{rs2}";
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//F[rd]f<= choose(F[rs1]f<F[rs2]f, F[rs1]f, F[rs2]f);
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val res[64] <= fdispatch_fsel_d(F[rs1]{64}, F[rs2]{64}, zext(0, 32));
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if(FLEN==64)
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F[rd] <= res;
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else { // NaN boxing
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val upper[FLEN] <= -1;
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F[rd] <= (upper<<64) | res;
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}
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val flags[32] <= fdispatch_fget_flags();
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FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
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}
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FMAX.D {
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encoding: b0010101 | rs2[4:0] | rs1[4:0] | b001 | rd[4:0] | b1010011;
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args_disass:"f{rd}, f{rs1}, f{rs2}";
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//F[rd]f<= choose(F[rs1]f>F[rs2]f, F[rs1]f, F[rs2]f);
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val res[64] <= fdispatch_fsel_d(F[rs1]{64}, F[rs2]{64}, zext(1, 32));
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if(FLEN==64)
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F[rd] <= res;
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else { // NaN boxing
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val upper[FLEN] <= -1;
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F[rd] <= (upper<<64) | res;
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}
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val flags[32] <= fdispatch_fget_flags();
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FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
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}
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FCVT.S.D {
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encoding: b0100000 | b00001 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
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args_disass:"f{rd}, f{rs1}";
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val res[32] <= fdispatch_fconv_d2f(F[rs1], rm{8});
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// NaN boxing
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val upper[FLEN] <= -1;
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F[rd] <= upper<<32 | zext(res, FLEN);
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}
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FCVT.D.S {
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encoding: b0100001 | b00000 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
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args_disass:"f{rd}, f{rs1}";
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val res[64] <= fdispatch_fconv_f2d(F[rs1]{32}, rm{8});
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if(FLEN==64){
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F[rd] <= res;
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} else {
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val upper[FLEN] <= -1;
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F[rd] <= (upper<<64) | res;
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}
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}
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FEQ.D {
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encoding: b1010001 | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b1010011;
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args_disass:"{name(rd)}, f{rs1}, f{rs2}";
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X[rd]<=zext(fdispatch_fcmp_d(F[rs1]{64}, F[rs2]{64}, zext(0, 32)));
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val flags[32] <= fdispatch_fget_flags();
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FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
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}
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FLT.D {
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encoding: b1010001 | rs2[4:0] | rs1[4:0] | b001 | rd[4:0] | b1010011;
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args_disass:"{name(rd)}, f{rs1}, f{rs2}";
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X[rd]<=zext(fdispatch_fcmp_d(F[rs1]{64}, F[rs2]{64}, zext(2, 32)));
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val flags[32] <= fdispatch_fget_flags();
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FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
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}
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FLE.D {
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encoding: b1010001 | rs2[4:0] | rs1[4:0] | b000 | rd[4:0] | b1010011;
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args_disass:"{name(rd)}, f{rs1}, f{rs2}";
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X[rd]<=zext(fdispatch_fcmp_d(F[rs1]{64}, F[rs2]{64}, zext(1, 32)));
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val flags[32] <= fdispatch_fget_flags();
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FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
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}
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FCLASS.D {
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encoding: b1110001 | b00000 | rs1[4:0] | b001 | rd[4:0] | b1010011;
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args_disass:"{name(rd)}, f{rs1}";
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X[rd]<=fdispatch_fclass_d(F[rs1]{64});
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}
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FCVT.W.D {
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encoding: b1100001 | b00000 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
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args_disass:"{name(rd)}, f{rs1}";
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X[rd]<= sext(fdispatch_fcvt_64_32(F[rs1]{64}, zext(0, 32), rm{8}), XLEN);
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val flags[32] <= fdispatch_fget_flags();
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FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
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}
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FCVT.WU.D {
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encoding: b1100001 | b00001 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
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args_disass:"{name(rd)}, f{rs1}";
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//FIXME: should be zext accodring to spec but needs to be sext according to tests
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X[rd]<= sext(fdispatch_fcvt_64_32(F[rs1]{64}, zext(1, 32), rm{8}), XLEN);
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val flags[32] <= fdispatch_fget_flags();
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FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
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}
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FCVT.D.W {
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encoding: b1101001 | b00000 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
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args_disass:"f{rd}, {name(rs1)}";
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val res[64] <= fdispatch_fcvt_32_64(sext(X[rs1]{32},64), zext(2, 32), rm{8});
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if(FLEN==64)
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F[rd] <= res;
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else { // NaN boxing
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val upper[FLEN] <= -1;
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F[rd] <= (upper<<64) | res;
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}
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}
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FCVT.D.WU {
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encoding: b1101001 | b00001 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
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args_disass:"f{rd}, {name(rs1)}";
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val res[64] <=fdispatch_fcvt_32_64(zext(X[rs1]{32},64), zext(3,32), rm{8});
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if(FLEN==64)
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F[rd] <= res;
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else { // NaN boxing
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val upper[FLEN] <= -1;
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F[rd] <= (upper<<64) | res;
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}
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}
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}
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}
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InsructionSet RV64D extends RV32D{
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instructions{
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FCVT.L.D {
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encoding: b1100001 | b00010 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
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args_disass:"{name(rd)}, f{rs1}";
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X[rd]<= sext(fdispatch_fcvt_d(F[rs1]{64}, zext(0, 32), rm{8}), XLEN);
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val flags[32] <= fdispatch_fget_flags();
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FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
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}
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FCVT.LU.D {
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encoding: b1100001 | b00011 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
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args_disass:"{name(rd)}, f{rs1}";
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X[rd]<= sext(fdispatch_fcvt_d(F[rs1]{64}, zext(1, 32), rm{8}), XLEN);
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val flags[32] <= fdispatch_fget_flags();
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FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
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}
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FCVT.D.L {
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encoding: b1101001 | b00010 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
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args_disass:"f{rd}, {name(rs1)}";
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val res[64] <= fdispatch_fcvt_d(sext(X[rs1],64), zext(2, 32), rm{8});
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if(FLEN==64)
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F[rd] <= res;
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else { // NaN boxing
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val upper[FLEN] <= -1;
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F[rd] <= (upper<<64) | res;
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}
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}
|
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FCVT.D.LU {
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encoding: b1101001 | b00011 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
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args_disass:"f{rd}, {name(rs1)}";
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val res[64] <=fdispatch_fcvt_d(zext(X[rs1],64), zext(3,32), rm{8});
|
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if(FLEN==64)
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F[rd] <= res;
|
||||
else { // NaN boxing
|
||||
val upper[FLEN] <= -1;
|
||||
F[rd] <= (upper<<64) | res;
|
||||
}
|
||||
}
|
||||
FMV.X.D {
|
||||
encoding: b1110001 | b00000 | rs1[4:0] | b000 | rd[4:0] | b1010011;
|
||||
args_disass:"{name(rd)}, f{rs1}";
|
||||
X[rd]<=sext(F[rs1]);
|
||||
}
|
||||
FMV.D.X {
|
||||
encoding: b1111001 | b00000 | rs1[4:0] | b000 | rd[4:0] | b1010011;
|
||||
args_disass:"f{rd}, {name(rs1)}";
|
||||
F[rd] <= zext(X[rs1]);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
Reference in New Issue
Block a user